DETAILED ACTION
This application has been examined. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 5/18/2026 have been fully considered but they are moot in view of the new grounds for rejection.
The Applicant presents the following argument(s) [in italics]:
… DeSanti and Peri, taken alone or in the alleged combination, fail to teach or suggest the claimed "NIC switch." DeSanti describes switch fabrics that operate at the system or chassis level to interconnect GPUs and NICs but not the claimed NIC-internal switch…
The Examiner respectfully disagrees with the a1.
While DeSanti-Peri substantially disclosed the claimed invention DeSanti-Peri does not disclose (re. Claim 1) wherein the NIC switch is internalized/integrated in the NIC.
The Examiner notes wherein DeSanti disclosed wherein chassis 202 may also house an internal switch fabric 208 along with other internal components such as NICs and GPUs.
Peri Figure 2 disclosed wherein a NIC is comprising several submodules/ subcomponents integrated into a single NIC. The Examiner notes wherein the Peri NIC circuitry 104A-B includes packet distributor circuitry 202 which is also equivalent to the claimed NIC internal switch.
Official Notice (see MPEP 2144.03) is taken that before the effective date of the claimed invention it would have been well-known in the networking art that submodules/subcomponents may be integrated into a single component on an integrated circuit board/card. In the context of the DeSanti-Peri it would have been obvious to integrate the DeSanti internal switch fabric 208 into the DeSanti NIC circuit as taught by Peri in order that the DeSanti internal switch is considered internal to the NIC as a matter of obvious engineering choice. The Examiner notes wherein the placement/location of the said NIC switch does not appear to change the operation of the NIC switch and/or impact the flow of data.
Priority
This application claims benefits of priority from Provisional Application 63/704317 filed October 7, 2024.
The effective date of the claims described in this application is October 7, 2024.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6,8-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over DeSanti (USPGPUB 2025/0184288) further in view of Peri (USPGPUB 2023/0300075) further in view of what was well-known in the networking art.
Regarding Claim 1
DeSanti Figure 11, Figure 15A, Figure 21 Paragraph 60 disclosed internal parallelism for GPUs in a computing device via an internal switch fabric in that computing device that connects each of those GPUs to parallel external fabrics that are accessible via a plurality of NICs in that computing device in order to increase the number of computing devices/GPUs that may be coupled together.
DeSanti Figure 15A Paragraph 45 disclosed wherein chassis 202 may also house an internal switch fabric 208 coupling its networking system to its processing system. In the illustrated embodiment, the internal switch fabric 208 includes four internal switch devices 208a, 208b, 208c, and 208d that each couple a pair of the NICs in the networking system to a pair of the GPUs in the processing system
DeSanti disclosed (re. Claim 1) a network interface card (NIC) for connecting a computer system to a network, the NIC comprising: a plurality of NIC communication lanes, (DeSanti-Figure 21, Paragraph 90, breakout cable 2112 includes a first connector 2112a connected to the 2×200G port 2100a, a second connector 2112b connected to the 200G port 2104a to couple the four 50G lanes (provided by the 200G MAC 2100b to the 2×200G port 2100a) from the 2×200G port 2100a to the 200G port 2104a) each NIC communication lane from among the plurality of NIC communication lanes
and a NIC switch configured to: receive a data packet from the computer system over one or more system data lanes from among a plurality of system data lanes, (DeSanti-Figure 15A ,Figure 21,Paragraph 45, chassis 202 may also house an internal switch fabric 208 coupling its networking system to its processing system)
identify a corresponding NIC communication lane from among the NIC communication lanes to route the data packet and one or more NIC data lanes from among a plurality of NIC data lanes, each NIC data lane from among the plurality of NIC data lanes (DeSanti-Figure 21,Paragraph 90, four 50G lanes provided between the 200G port 2104a and the 200G MAC 2104c (as illustrated by the four lines between the 200G port 2104a and the 200G MAC 2104c in FIG. 21) ) being associated with one of the corresponding NIC communication lanes, (DeSanti-Figure 21, Paragraph 90, breakout cable 2112 includes a first connector 2112a connected to the 2×200G port 2100a, a second connector 2112b connected to the 200G port 2104a to couple the four 50G lanes (provided by the 200G MAC 2100b to the 2×200G port 2100a) from the 2×200G port 2100a to the 200G port 2104a) and
route the data packet over the one or more NIC data lanes to the corresponding NIC communication lane for transmission to the network.(DeSanti-Figure 21, Paragraph 50, NIC that provides access to each of the plurality of external fabrics, and a plurality of GPUs. The computing device also includes an internal switch fabric that is configured to couple each of the plurality of GPUs to the at least one NIC to provide each of the plurality of GPUs access to each of the plurality of external fabrics.)
While DeSanti substantially disclosed the claimed invention DeSanti does not disclose (re. Claim 1) wherein the NIC switch is internalized/integrated in the NIC.
While DeSanti substantially disclosed the claimed invention DeSanti does not disclose (re. Claim 1) a corresponding lane controller from among a plurality of lane controllers and a corresponding lane transceiver from among a plurality of lane transceivers.
Peri Paragraph 44 disclosed wherein NIC circuitry 104A-B can divide, partition, and/or otherwise split an incoming data flow associated with a primary window into multiple parallel windows. Peri Figure 2,Paragraph 51 disclosed wherein the NIC circuitry 104A-B includes example packet distributor circuitry 202 and example packet receiver circuitry 204.
Peri disclosed (re. Claim 1) a corresponding lane controller from among a plurality of lane controllers (Peri-Figure 2,Paragraph 51,the NIC circuitry 104A-B includes packet distributor circuitry 202) and
a corresponding lane transceiver from among a plurality of lane transceivers.(Peri-Figure 2,Paragraph 51, the NIC circuitry 104A-B includes packet receiver circuitry 204.)
DeSanti and Peri are analogous art because they present concepts and practices regarding configuration and operation of network interface controllers. Before the time of the effective filing date of the claimed invention it would have been obvious to combine Peri into DeSanti. The motivation for the said combination would have been to effectuate efficient parallelization of elephant flows and improve the scaling of executing the elephant flows with an increasing number of cores.(Peri-Paragraph 35)
While DeSanti-Peri substantially disclosed the claimed invention DeSanti-Peri does not disclose (re. Claim 1) wherein the NIC switch is internalized/integrated in the NIC.
The Examiner notes wherein DeSanti disclosed wherein chassis 202 may also house an internal switch fabric 208 along with other internal components such as NICs and GPUs.
Peri Figure 2 disclosed wherein a NIC is comprising several submodules/ subcomponents integrated into a single NIC. The e1 notes wherein the Peri NIC circuitry 104A-B includes packet distributor circuitry 202 which is also equivalent to the claimed NIC internal switch.
Official Notice (see MPEP 2144.03) is taken that before the effective date of the claimed invention it would have been well-known in the networking art that submodules/subcomponents may be integrated into a single component on an integrated circuit board/card. In the context of the DeSanti-Peri it would have been obvious to integrate the DeSanti internal switch fabric 208 into the DeSanti NIC circuit as taught by Peri in order that the DeSanti internal switch is considered internal to the NIC as a matter of obvious engineering choice. The Examiner notes wherein the placement/location of the said NIC switch does not appear to change the operation of the NIC switch and/or impact the flow of data.
Regarding Claim 8
Claim 8 (re. system) recites substantially similar limitations as Claim 1. Claim 8 is rejected on the same basis as Claim 1.
Regarding Claim 14
Claim 14 (re. method) recites substantially similar limitations as Claim 1. Claim 14 is rejected on the same basis as Claim 1.
Regarding Claim 2,9,15
DeSanti-Peri disclosed (re. Claim 2,9,15) wherein each NIC communication lane from among the plurality of NIC communication lanes is physically isolated from one another. (DeSanti-Figure 21, Paragraph 90, breakout cable 2112 includes a first connector 2112a connected to the 2×200G port 2100a, a second connector 2112b connected to the 200G port 2104a to couple the four 50G lanes (provided by the 200G MAC 2100b to the 2×200G port 2100a) from the 2×200G port 2100a to the 200G port 2104a)
Regarding Claim 3,10,16
DeSanti-Peri disclosed (re. Claim 3,10,16) wherein each lane controller from among the plurality of lane controllers is physically isolated from one another, (Peri-Figure 2,Paragraph 51,the NIC circuitry 104A-B includes packet distributor circuitry 202) and wherein each lane transceiver from among the plurality of lane transceivers is physically isolated from one another. (Peri-Figure 2,Paragraph 51, the NIC circuitry 104A-B includes packet receiver circuitry 204.)
Regarding Claim 4,11,17
DeSanti-Peri disclosed (re. Claim 4,11,17) wherein the plurality of system data lanes and the plurality of NIC data lanes are compliant with a Peripheral Component Interconnect Express (PCIe) interface standard.(DeSanti-Paragraph 45, each of the switch devices 208a, 208b, 208c, and 208d may be provided by a respective Peripheral Component Interconnect express (PCIe) switch)
Regarding Claim 5,12,18
DeSanti-Peri disclosed (re. Claim 5,12,18) wherein the plurality of system data lanes comprises sixteen system data lanes, the sixteen system data lanes being bifurcated into four groups of four system data lanes, (DeSanti-Figure 21,Paragraph 90, four 50G lanes provided between the 200G port 2104a and the 200G MAC 2104c (as illustrated by the four lines between the 200G port 2104a and the 200G MAC 2104c in FIG. 21) )
wherein the NIC switch is configured to receive the data packet from the computer system over a corresponding group of four system data lanes from among the four groups of four system data lanes, wherein the plurality of NIC data lanes comprises sixteen NIC data lanes, the sixteen NIC data lanes being bifurcated into four groups of four NIC data lanes, (DeSanti-Figure 21,Paragraph 90, four 50G lanes provided between the 200G port 2104a and the 200G MAC 2104c (as illustrated by the four lines between the 200G port 2104a and the 200G MAC 2104c in FIG. 21) )
wherein the NIC switch is configured to identify a corresponding group of four NIC data lanes from among the plurality of NIC data lanes that are associated with the corresponding NIC communication lane, and wherein the NIC switch is configured to route the data packet over the corresponding group of four NIC data lanes to the corresponding NIC communication lane for transmission to the network. (DeSanti-Figure 21, Paragraph 50, NIC that provides access to each of the plurality of external fabrics, and a plurality of GPUs. The computing device also includes an internal switch fabric that is configured to couple each of the plurality of GPUs to the at least one NIC to provide each of the plurality of GPUs access to each of the plurality of external fabrics.)
Regarding Claim 6,13,19
DeSanti-Peri disclosed (re. Claim 6,13,19) wherein the NIC switch is further configured to bifurcate the plurality of system data lanes into a plurality of groups of system data lanes, ( Peri-Paragraph 44, NIC circuitry 104A-B can divide, partition, and/or otherwise split an incoming data flow associated with a primary window into multiple parallel windows)
and wherein the NIC switch is configured to receive the data packet from the computer system over a corresponding group of system data lanes from among the plurality of groups of system data lanes, (DeSanti-Figure 15A ,Figure 21,Paragraph 45, chassis 202 may also house an internal switch fabric 208 coupling its networking system to its processing system)
wherein the NIC switch is configured to identify a corresponding group of NIC data lanes from among plurality of NIC data lanes that are associated with the corresponding NIC communication lane, and wherein the NIC switch is configured to route the data packet over the corresponding group of NIC data lanes to the corresponding NIC communication lane for transmission to the network. (DeSanti-Figure 21, Paragraph 50, NIC that provides access to each of the plurality of external fabrics, and a plurality of GPUs. The computing device also includes an internal switch fabric that is configured to couple each of the plurality of GPUs to the at least one NIC to provide each of the plurality of GPUs access to each of the plurality of external fabrics.)
Claim(s) 7,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over DeSanti (USPGPUB 2025/0184288) further in view of Peri (USPGPUB 2023/0300075) further in view of Kamisetty (US Patent 12278762)
Regarding Claim 7,20
While DeSanti-Peri substantially disclosed the claimed invention DeSanti-Peridoes not disclose (re. Claim 7,20) wherein the NIC is implemented onto an expansion card that is configured to be plugged into the computer system.
Kamisetty Column 9 Lines 15 disclosed wherein a NIC is a PCIe expansion card that plugs into a server or storage box to enable connectivity to an Ethernet network.
Kamisetty disclosed (re. Claim 7,20) wherein the NIC is implemented onto an expansion card that is configured to be plugged into the computer system.( Kamisetty-Column 9 Lines 15,a NIC is a PCIe expansion card that plugs into a server or storage box to enable connectivity to an Ethernet network.)
DeSanti and Kamisetty are analogous art because they present concepts and practices regarding configuration and operation of network interface controllers. Before the time of the effective filing date of the claimed invention it would have been obvious to combine Kamisetty into DeSanti-Peri. The motivation for the said combination would have been to implement the P4 and extended P4 pipelines and various other functions to provide an improved network performance. (Kamisetty-Column 12 Lines 15-20)
Conclusion
Examiner’s Note: In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GREG C BENGZON whose telephone number is (571)272-3944. The examiner can normally be reached on Monday - Friday 8 AM - 4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Follansbee can be reached on (571) 272-3964. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GREG C BENGZON/ Primary Examiner, Art Unit 2444
Prosecution Insights