DETAILED ACTION
Amendment submitted January 26, 2026 has been considered by examiner. Claims 1-20 are pending.
Response to Arguments
Applicant’s arguments towards 35 USC 103 rejection of claims 1-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments towards 35 USC rejection of Claims 15-20 have been fully considered but they are not persuasive.
The Applicant states that the cited art does not disclose “transmitting, by the host devices an operation command to a memory device of the plurality of memory devices, the operation command determined by a host processor of the host device on the basis of current progress of a task indicated by the query plan status information, and the operation command providing an update to a query plan stored by the memory device.” The Examiner respectfully disagrees.
Gupta, at least illustrated in Figure 8A and described in paragraph [0067], states “In case, the query execution progress is not 100% complete, then the process goes to block 801 to retrieve the intermediate query execution results. In case, the query execution progress is 100% completed, then each major progress checkpoint is retrieved from the temporary memory as illustrated in the block 807.”
That is interpreted as that based on a particular progress (for example when it is less than a 100%) an operation command retrieves intermediate query results. The status is updated in at least Abdellatif [0023].
Applicant's arguments towards 35 USC rejection of Claims 1-20 have been fully considered but they are not persuasive.
The Applicant states that “The amended independent claims are believed to recite a technical improvement and an inventive concept beyond any allegedly recited abstract idea.” The Examiner respectfully disagrees.
The claims, with the newly amended features, recite abstract functionality that uses hardware to execute such functionality. As such, the claims remain abstract in view of 35 USC 101.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 15-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 15 is currently amended and states “transmitting, by the host devices an operation command to a memory device of the plurality of memory devices, the operation command determined by a host processor of the host device on the basis of current progress of a task indicated by the query plan status information, and the operation command providing an update to a query plan stored by the memory device.”
However, it does not appear that such functionality is described by the instant specification.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Independent Claims 1 and 8 recite a device that stores data and then process the data.
Specifically, the claims recite:
a device memory configured to store a query plan table and query plan status information synchronized with query plan status information stored by the host device – Synchronizing information between different data structures is something that can be performed in the mind and with aid of pen and paper. As to storing a data structure, that is a well-understood, routine and conventional activity as discussed in MPEP 2106.05.
a device processor configured to process a task according to the query plan table stored in the device memory and update the query plan status information in response to receiving an operation command from the host device through the CXL protocol - Processing a task, such as executing a query and updating a status of a query is a process that can be performed in the mind or with aid of pen and paper.
Independent Claim 15 recites a device that stores data and then process the data.
checking, by the host device, query plan status information about the plurality of memory devices - Monitoring a status is a process that can be performed in the mind.
transmitting, by the host devices an operation command to a memory device of the plurality of memory devices, the operation command determined by a host processor of the host device on the basis of current progress of a task indicated by the query plan status information, and the operation command providing an update to a query plan stored by the memory device - Processing a task, such as executing a query, that is based on particular progress of the task, is a process that can be performed in the mind or with aid of pen and paper.
updating, by the memory device that has received the operation command, a task corresponding to the operation command to the query plan stored by the memory device - Processing a task, such as executing a query and updating a status of a query is a process that can be performed in the mind or with aid of pen and paper. Storing is a well-understood, routine and conventional activity as discussed in MPEP 2106.05.
performing, by the memory device that has received the operation command, a task according to the query plan that has been updated, and replying to the host device updated content of the query plan status information - Processing a task, such as executing a query and updating a status of a query is a process that can be performed in the mind or with aid of pen and paper.
This judicial exception is not integrated into a practical application. Other, the
abstract idea, the claims recite additional elements of hardware executing the abstract
idea. The additional elements such a processor, storage device, etc are recited at a high
level of generality, i.e. as generic computer components performing generic computer
functions of information processing. Accordingly, these additional elements do not
integrate the abstract idea into a practical application because they do not impose any
meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Dependent Claims 2-7, 9-14 and 16-20 recite further mental processes that may be completed with aid of pen and paper and as such are directed to an abstract idea without significantly more.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8, 10, 12-13, are rejected under 35 U.S.C. 103 as being unpatentable over Abdellatif et al (US Patent Application Publication 2012/0130986) in view of Subrahmanyam et al (US Patent Application Publication 2024/0256459) and further in view of Das et al (US Patent Application Publication 2016/0350371).
Claim 1: Abdellatif discloses a device, the device comprising:
a device memory configured to store a query plan table and query plan status information synchronized with the host device [Fig. 2, 0014-0016]. [See at least a data structure stored on a device with query plan data, that includes status of query plans.]
a device processor configured to process a task according to the query plan table stored in the device memory and update the query plan status information in response to receiving an operation command from the host [0023]. [See at least updating the status.]
Abdellatif alone does not explicitly disclose that the memory is synchronized with query plan status information stored by the host device.
However, Abdellatif [Fig. 2, 0014-0016] discloses storing a query plan and status in memory and Das [0035, 0101] discloses synchronizing query plan statistics across devices to execute the same query plan.
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Das. One would have been motivated to do so in order to make sure that each device would execute the same query plan.
Abdellatif alone also does not explicitly disclose that the device is connected to a host device through a CXL protocol.
However, Subrahmanyam [0018] discloses a CXL device connected to a CPU.
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Subrahmanyam. One would have been motivated to do so in order to at least improve performance by at least expanding memory and/or optimizing data movement.
Claim 2: Abdellatif as modified discloses the device of Claim 1, and Subrahmanyam, for the same reasons as above, further discloses wherein the updated query plan status information is transmitted to the host device through a CXL.cache protocol [0022]. [Abdellatif [0023] discloses updating the query plan status and Subrahmanyam [0022] discloses the use of CXL.cache protocol.]
Claim 3: Abdellatif as modified discloses the device of Claim 1, and Subrahmanyam, for the same reasons as above, further discloses wherein the query plan table is stored and updated in the device memory according to a CXL.mem protocol [0022]. [Abdellatif [0023] discloses storing and updating the query plan and Subrahmanyam [0022] discloses the use of CXL.mem protocol.]
Claim 8: Abdellatif discloses a host device, the host device comprising:
a host memory configured to store query plan status information synchronized with query plan status information stored by the plurality of memory devices [Fig. 2, 0014-0016]. [See at least a data structure stored on a device with query plan data, that includes status of query plans.]
a host processor configured to transmit, to a memory device of the plurality of memory devices, on the basis of the query plan status information stored in the host memory, an operation command [Fig. 2, 0014-0016]. [See at least executing a query.]
Abdellatif alone does not explicitly disclose that the memory is synchronized with query plan status information stored by the host device.
However, Abdellatif [Fig. 2, 0014-0016] discloses storing a query plan and status in memory and Das [0035, 0101] discloses synchronizing query plan statistics across devices to execute the same query plan.
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Das. One would have been motivated to do so in order to make sure that each device would execute the same query plan.
Abdellatif alone also does not explicitly disclose that the device is connected to a host device through a CXL protocol.
However, Subrahmanyam [0018] discloses a CXL device connected to a CPU.
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Subrahmanyam. One would have been motivated to do so in order to at least improve performance by at least expanding memory and/or optimizing data movement.
Claim 10: Abdellatif as modified discloses the device of Claim 8, and Abdellatif further discloses wherein the memory device that received the operation command updates a task corresponding to the operation command to a query plan table, and performs an allocated task on the basis of the query plan table [Fig. 2, 0014-0016]. [See at least updating a status and executing a query.]
Claim 12: Abdellatif as modified discloses the device of Claim 10, and Abdellatif further discloses wherein the host device receives updated content from the memory device on the query plan table [0023].
Claim 13: Abdellatif as modified discloses the device of Claim 12, and Abdellatif further discloses wherein the query plan status information is received through a CXL.cache protocol [0022]. [Abdellatif [0023] discloses updating the query plan status and Subrahmanyam [0022] discloses the use of CXL.cache protocol.]
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Abdellatif et al (US Patent Application Publication 2012/0130986) in view of Subrahmanyam et al (US Patent Application Publication 2024/0256459) further in view of Das et al (US Patent Application Publication 2016/0350371) and further in view of Kuno et al (US Patent Application Publication 2010/0235349).
Claim 4: Abdellatif as modified discloses the device of Claim 1, but Abdellatif alone does not explicitly disclose wherein the query plan status information includes a task progress status, a current progress stage, a progress stage for each device, and a delay time.
However, Abdellatif [Fig. 2, 0014-0016] discloses at least a data structure stored on a device with query plan data, that includes status/stage of query plans. In addition, Kuno [0016] discloses progress indicator for each executing query that includes progress status of each query and time remaining of the query (time remaining is analogous to delay time based at least on para [0042] of the instant specification.]
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Kuno. One would have been motivated to do so in order to keep track of queries and their progress.
Claims 5-7, 11, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Abdellatif et al (US Patent Application Publication 2012/0130986) in view of Subrahmanyam et al (US Patent Application Publication 2024/0256459) further in view of Das et al (US Patent Application Publication 2016/0350371) and further in view of Nishizawa et al (US Patent Application Publication 2010/0106710).
Claim 5: Abdellatif as modified discloses the device of Claim 1, but Abdellatif alone does not explicitly disclose wherein the query plan table includes a stage for each query of the memory device, a local stage process, an input address for the device memory, an output address for a host memory, and a computation level.
However, Abdellatif [Fig. 2, 0014-0016] discloses at least a data structure stored on a device with query plan data for devices; Nishizawa [0043] further discloses a data structure that includes a format address for each query; And Subrahmanyam [0018] discloses translating between logical and physical addresses (i.e. input and output addresses).
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Nishizawa and Subrahmanyam. One would have been motivated to do so in order to keep track of where a query is executed.
Claim 6: Abdellatif as modified discloses the device of Claim 1, and Abdellatif in view of Nishizawa and Subrahmanyam, further disclose wherein the local stage process indicates a progress stage of an internal stage of the memory device in the stage for each query [Fig. 2, 0014-0016].
Claim 7: Abdellatif as modified discloses the device of Claim 1, and Abdellatif in view of Nishizawa and Subrahmanyam further disclose wherein the input address and the output address are determined on the basis of the progress stage of the local stage process [See at least Subrahmanyam [0018] disclosing mapping between logical and physical addresses.]
Claim 11: Abdellatif as modified discloses the device of Claim 10, but Abdellatif alone does not explicitly disclose wherein the query plan table includes a stage for each query of the memory device, a local stage process, an input address for a memory device memory, an output address for a host memory, and a computation level.
However, Abdellatif [Fig. 2, 0014-0016] discloses at least a data structure stored on a device with query plan data for devices; Nishizawa [0043] further discloses a data structure that includes a format address for each query; And Subrahmanyam [0018] discloses translating between logical and physical addresses (i.e. input and output addresses).
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Nishizawa and Subrahmanyam. One would have been motivated to do so in order to keep track of where a query is executed.
Claim 14: Abdellatif as modified discloses the device of Claim 11, and Abdellatif in view of Nishizawa and Subrahmanyam further disclose wherein the memory device accesses an output address of the host memory determined on the basis of the progress stage of the local stage process [See at least Subrahmanyam [0018] disclosing mapping between logical and physical addresses.]
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Abdellatif et al (US Patent Application Publication 2012/0130986) in view of Subrahmanyam et al (US Patent Application Publication 2024/0256459) further in view of Das et al (US Patent Application Publication 2016/0350371) further in view of Kuno et al (US Patent Application Publication 2010/0235349) and further in view of Gupta et al (US Patent Application Publication 2017/0199911).
Claim 9: Abdellatif as modified discloses the device of Claim 8 above, but Abdellatif alone does not explicitly disclose wherein the query plan status information includes a task progress status of a query request of the host device for each memory device of the plurality of memory devices, a current progress stage, a progress status for the memory device, and a delay time.
However, Abdellatif [Fig. 2, 0014-0016] discloses at least a data structure stored on a device with query plan data, that includes status/stage of query plans; Kuno [0016] discloses progress indicator for each executing query that includes progress status of each query and time remaining of the query (time remaining is analogous to delay time based at least on para [0042] of the instant specification.] and Gupta [0042] discloses progress status of a query for each device.
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Kuno and Gupta. One would have been motivated to do so in order to keep track of queries and their progress.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Abdellatif et al (US Patent Application Publication 2012/0130986) in view of Gupta et al (US Patent Application Publication 2017/0199911).
Claim 15: Abdellatif discloses an I/O scheduling method between a host device and a plurality of memory devices, the I/O scheduling method comprising:
checking by the host device query plan status information about the plurality of memory devices [0016]. [See at least identifying a status in a query plan.]
transmitting by the host device an operation command to a memory device on the basis of the query plan status information [Fig. 2, 0014-0016]. [See at least executing a query.]
Abdellatif alone does not explicitly disclose transmitting, by the host devices an operation command to a memory device of the plurality of memory devices, the operation command determined by a host processor of the host device on the basis of current progress of a task indicated by the query plan status information, and the operation command providing an update to a query plan stored by the memory device.
However, Gupta [0042] discloses providing queries to various devices and monitor the status of the queries and Gupta [Figure 8A, 0067] states, “In case, the query execution progress is not 100% complete, then the process goes to block 801 to retrieve the intermediate query execution results. In case, the query execution progress is 100% completed, then each major progress checkpoint is retrieved from the temporary memory as illustrated in the block 807.” That is interpreted as that based on a particular progress (for example when it is less than a 100%) an operation command retrieves intermediate query results. The status is updated in at least Abdellatif [0023].
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Gupta. One would have been motivated to do so in order to keep track of queries, their progress and actions to take based on the progress.
Abdellatif as modified further discloses:
updating, by the memory device that has received the operation command, a task corresponding to the operation command to the query plan stored by the memory device [0023]. [See at least updating the status.]
performing, by the memory device that has received the operation command, a task according to the query plan that has been updated, and replying to the host device updated content of the query plan status information [0023]. [See at least updating the status and executing the plan.]
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Abdellatif et al (US Patent Application Publication 2012/0130986) in view of Gupta et al (US Patent Application Publication 2017/0199911) and further in view of Subrahmanyam et al (US Patent Application Publication 2024/0256459).
Claim 16: Abdellatif as modified discloses the method of Claim 15 above, but Abdellatif alone does not explicitly disclose wherein the query plan status information of the host device is updated and synchronized with the plurality of memory devices through a CXL.cache protocol.
However, Subrahmanyam [0018] discloses a CXL device connected to a CPUs and Subrahmanyam [0022] discloses the use of CXL.cache protocol.
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Subrahmanyam. One would have been motivated to do so in order to at least improve performance by at least expanding memory and/or optimizing data movement.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Abdellatif et al (US Patent Application Publication 2012/0130986) in view of Gupta et al (US Patent Application Publication 2017/0199911) and further in view of Kuno et al (US Patent Application Publication 2010/0235349).
Claim 17: Abdellatif as modified discloses the method of Claim 15 above, but Abdellatif alone does not explicitly disclose wherein the query plan status information includes a task progress status of a query request of the host device for the memory device, a current progress stage, a progress status for each memory device of the plurality of memory devices, and a delay time.
However, Abdellatif [Fig. 2, 0014-0016] discloses at least a data structure stored on a device with query plan data, that includes status/stage of query plans; Kuno [0016] discloses progress indicator for each executing query that includes progress status of each query and time remaining of the query (time remaining is analogous to delay time based at least on para [0042] of the instant specification.] and Gupta [0042] discloses progress status of a query for each device.
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Kuno and Gupta. One would have been motivated to do so in order to keep track of queries and their progress.
Claim 18: Abdellatif as modified discloses the method of Claim 17, and Abdellatif further discloses wherein the host device selects any one of the plurality of memory devices and transmits the operation command to process a stage or a task having an output to be combined with outputs of a plurality of stages, on the basis of the delay time. [0023].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Abdellatif et al (US Patent Application Publication 2012/0130986) in view of Gupta et al (US Patent Application Publication 2017/0199911) further in view of Subrahmanyam et al (US Patent Application Publication 2024/0256459) and further in view of Das (US Patent Application Publication 2015/0074143).
Claim 19: Abdellatif as modified discloses the method of Claim 15 above, but Abdellatif alone does not explicitly disclose wherein a query plan table is stored in a device memory belonging to each of the plurality of memory devices according to a CXL.mem protocol.
However, Das [0035] discloses having a storage plan stored in different nodes (i.e. devices) and Subrahmanyam [0022] discloses the use of CXL.mem protocol.]
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Subrahmanyam. One would have been motivated to do so in order to use a particular protocol based on the environment used for execution of queries.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Abdellatif et al (US Patent Application Publication 2012/0130986) in view of Gupta et al (US Patent Application Publication 2017/0199911) further in view of Subrahmanyam et al (US Patent Application Publication 2024/0256459) further in view of Das (US Patent Application Publication 2015/0074143) and further in view of Nishizawa et al (US Patent Application Publication 2010/0106710).
Claim 20: Abdellatif as modified discloses the method of Claim 19 above, but Abdellatif alone does not explicitly disclose wherein the query plan table includes a stage for each query, a local stage process, an input address for the device memory, an output address for a host memory, and a computation level.
However, Abdellatif [Fig. 2, 0014-0016] discloses at least a data structure stored on a device with query plan data for devices; Nishizawa [0043] further discloses a data structure that includes a format address for each query; And Subrahmanyam [0018] discloses translating between logical and physical addresses (i.e. input and output addresses).
As such, it would have been obvious for one of ordinary skill in the art before the effective filing date to modify Abdellatif with Nishizawa and Subrahmanyam. One would have been motivated to do so in order to keep track of where a query is executed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEX GOFMAN whose telephone number is (571)270-1072. The examiner can normally be reached Monday-Friday 8-5.
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/ALEX GOFMAN/Primary Examiner, Art Unit 2163