DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 & 13-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tani (US 2009/0310278).
In regards to claim 1, Tani ‘278 discloses
A multilayer electronic component, comprising:
a body (10 – fig. 1; [0047]) including a dielectric layer (50 – fig. 2; [0047]) and first and second internal electrodes (41-42 – fig. 2; [0051]) alternately disposed with the dielectric layer, and including first and second surfaces (11 & 12 – fig. 1-2; [0047]) opposing each other in a first direction, third and fourth surfaces (31 & 32– fig. 1; [0047]) connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces (21 & 22 – fig. 1; [0047]) connected to the first to fourth surfaces and opposing each other in a third direction;
a first external electrode (1 – fig. 1-2; [0049]) disposed on at least one surface among the first surface, the second surface, the fifth surface, and the sixth surface, and connected to the first internal electrodes;
a second external electrode (2 – fig. 1-2; [0049]) disposed on at least one surface among the first surface, the second surface, the third surface, and the fourth surface, and connected to the second internal electrodes; and
a first connection electrode (41d – fig. 4; [0053] & [0058]) penetrating the dielectric layer and connecting two first internal electrodes adjacent to each other in the first direction,
wherein, in the first connection electrode, a plurality of first via electrodes (41d) shifted from each other in a direction perpendicular to the first direction are laminated in the first direction (seen in fig. 4).
In regards to claim 2, Tani ‘278 discloses
The multilayer electronic component of claim 1, wherein a plurality of the first connection electrode penetrating the same dielectric layer are disposed (seen in fig. 4).
In regards to claim 3, Tani ‘278 discloses
The multilayer electronic component of claim 2, wherein the plurality of the first connection electrodes penetrating the same dielectric layer are arranged in the second and third directions (fig. 4; [0058] – as the connection electrodes are 3-D, said electrodes are arranged in the second and third directions. It can further be said that the array of connection electrodes is for example 2 x1).
In regards to claim 4, Tani ‘278 discloses
The multilayer electronic component of claim 1, further comprising: a second connection electrode penetrating the dielectric layer and connecting two second internal electrodes adjacent to each other in the first direction (fig. 4; [0053] & [0058]),
wherein, in the second connection electrode, a plurality of second via electrodes shifted from each other in the direction perpendicular to the first direction are laminated in the first direction (fig. 4; [0053]).
In regards to claim 5, Tani ‘278 discloses
The multilayer electronic component of claim 1, further comprising: a first auxiliary electrode (D1 – fig. 6-7; [0087]) spaced apart from one of the second internal electrodes in the third direction, and disposed between first via electrodes adjacent to each other among the plurality of first via electrodes (fig. 7).
In regards to claim 6, Tani ‘278 discloses
The multilayer electronic component of claim 4, further comprising: a second auxiliary electrode (D2 – fig. 6-7; [0087]) spaced apart from one of the first internal electrodes in the second direction, and disposed between second via electrodes adjacent to each other among the plurality of second via electrodes (fig. 7; [0087]).
In regards to claim 7, Tani ‘278 discloses
The multilayer electronic component of claim 1, wherein the first connection electrode includes a plurality of first connection electrodes (41d), and two first connection electrodes adjacent to each other in the first direction among the plurality of first connection electrodes are shifted from each other in the direction perpendicular to the first direction (fig. 4).
In regards to claim 13, Tani ‘278 discloses
A multilayer electronic component, comprising:
a body (10 – fig. 1; [0047]) including first and second surfaces (11 & 12 – fig. 1-2; [0047]) opposing each other in a first direction, third and fourth surfaces (31 & 32– fig. 1; [0047]) connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces (21 & 22 – fig. 1; [0047]) connected to the first to fourth surfaces and opposing each other in a third direction,
the body including a first internal electrode layer including a first dielectric layer (50 – fig. 6; [0047]) and a first internal electrode (41 – fig. 6; [0051]) disposed on the first dielectric layer and including a first main portion and a first lead portion extending from the first main portion to the fifth surface or sixth surface (seen in fig. 6),
the body including a second internal electrode layer including a second dielectric layer (50 – fig. 6; [0047]), a second internal electrode (42 – fig. 6; [0051]) disposed on the second dielectric layer and overlapping the first main portion in the first direction, and a first auxiliary electrode (D1 – fig. 6-7; [0087]) spaced apart from the second internal electrode in the third direction,
wherein the first and second internal electrodes layers are alternately disposed in the first direction (fig. 6);
a first external electrode (1 – fig. 6; [0049]) disposed on at least one surface among the first surface, the second surface, the fifth surface, and the sixth surface, and connected to the first internal electrode;
a second external electrode (2 – fig. 6; [0049]) disposed on at least one surface among the first surface, the second surface, the third surface, and the fourth surface, and connected to the second internal electrode;
a first via electrode (41d – fig. 7; [0053] & [0058]) penetrating the first dielectric layer and connecting the first lead portion to the first auxiliary electrode; and
a second via electrode (41d – fig. 7; [0053] & [0058]) penetrating the second dielectric layer and connecting the first lead portion to the first auxiliary electrode,
wherein the first via electrode and the second via electrode are shifted from each other in a direction perpendicular to the first direction (fig. 7).
In regards to claim 14, Tani ‘278 discloses
The multilayer electronic component of claim 13, wherein the first and second via electrodes do not overlap each other in the first direction (fig. 7).
In regards to claim 15, Tani ‘278 discloses
The multilayer electronic component of claim 13, wherein a plurality of the first via electrodes penetrating the same first dielectric layer are disposed, and a plurality of the second via electrodes penetrating the same second dielectric layer are disposed (fig. 7), and
wherein the first via electrodes penetrating the same first dielectric layer are arranged in the second and third directions, and the second via electrodes penetrating the same second dielectric layer are arranged in the second and third directions (fig. 7; [0058] – as the connection electrodes are 3-D, said electrodes are arranged in the second and third directions. It can further be said that the array of connection electrodes is for example 2 x1).
In regards to claim 16, Tani ‘278 discloses
The multilayer electronic component of claim 15, wherein the first dielectric layer includes a first region disposed between two first via electrodes adjacent to each other in the second or third direction among a plurality of the first via electrodes, and
wherein the plurality of the second via electrodes overlap the first region in the first direction (fig. 7).
In regards to claim 17, Tani ‘278 discloses
The multilayer electronic component of claim 13, wherein the second internal electrode includes a second main portion overlapping the first internal electrode in the first direction, and a second lead portion extending from the second main portion to the third surface or the fourth surface (fig. 6),
wherein the first internal electrode layer further includes a second auxiliary electrode (D2 – fig. 6-7; [0087]) disposed on the first dielectric layer and spaced apart from the first internal electrode in the second direction,
wherein the multilayer electronic component further includes a third via electrode penetrating the first dielectric layer and connecting the second lead portion to the second auxiliary electrode, and a fourth via electrode penetrating the second dielectric layer and connecting the second lead portion to the second auxiliary electrode (fig. 7; [0087]), and
wherein the third via electrode and the fourth via electrode are shifted from each other in the direction perpendicular to the first direction (fig. 7; [0087]).
In regards to claim 18, Tani ‘278 discloses
The multilayer electronic component of claim 17, wherein a plurality of the third via electrodes penetrating the same first dielectric layer are disposed, and a plurality of the fourth via electrodes penetrating the same second dielectric layer are disposed (fig. 7; [0087]), and
wherein the third via electrode penetrating the same first dielectric layer is arranged in the second and third directions, and the fourth via electrode penetrating the same second dielectric layer is arranged in the second and third directions (fig. 7; [0087]).
In regards to claim 19, Tani ‘278 discloses
The multilayer electronic component of claim 18, wherein the first dielectric layer includes a second region disposed between two third via electrodes adjacent to each other in the second direction or the third direction among a plurality of the third via electrodes, and
wherein a plurality of the fourth via electrodes overlap the second region in the first direction (fig. 7; [0087]).
Claim(s) 1-4, 7, & 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2013161983A hereafter referred to as Fujimura.
In regards to claim 1, Fujimura discloses
A multilayer electronic component, comprising:
a body (4 – fig. 1; [0020]) including a dielectric layer (10 – fig. 1; [0020]) and first and second internal electrodes (12-13 – fig. 1; [0020]) alternately disposed with the dielectric layer, and including first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction ([0022]), and fifth and sixth surfaces (5 & 7 – fig. 1; [0022]) connected to the first to fourth surfaces and opposing each other in a third direction;
a first external electrode (8 – fig. 1-2; [0021]) disposed on at least one surface among the first surface, the second surface, the fifth surface, and the sixth surface, and connected to the first internal electrodes;
a second external electrode (6 – fig. 1; [0021]) disposed on at least one surface among the first surface, the second surface, the third surface, and the fourth surface, and connected to the second internal electrodes; and
a first connection electrode (24 – fig. 2; [0030]) penetrating the dielectric layer and connecting two first internal electrodes adjacent to each other in the first direction,
wherein, in the first connection electrode, a plurality of first via electrodes shifted from each other in a direction perpendicular to the first direction are laminated in the first direction (fig. 2).
In regards to claim 2, Fujimura discloses
The multilayer electronic component of claim 1, wherein a plurality of the first connection electrode penetrating the same dielectric layer are disposed (fig. 2).
In regards to claim 3, Fujimura discloses
The multilayer electronic component of claim 2, wherein the plurality of the first connection electrodes penetrating the same dielectric layer are arranged in the second and third directions (fig. 2; [0030]).
In regards to claim 4, Fujimura discloses
The multilayer electronic component of claim 1, further comprising: a second connection electrode penetrating the dielectric layer and connecting two second internal electrodes adjacent to each other in the first direction (fig. 2; [0036]),
wherein, in the second connection electrode, a plurality of second via electrodes shifted from each other in the direction perpendicular to the first direction are laminated in the first direction (fig. 2; [0036]).
In regards to claim 7, Fujimura discloses
The multilayer electronic component of claim 1, wherein the first connection electrode includes a plurality of first connection electrodes, and two first connection electrodes adjacent to each other in the first direction among the plurality of first connection electrodes are shifted from each other in the direction perpendicular to the first direction (fig. 2).
In regards to claim 12, Fujimura discloses
The multilayer electronic component of claim 1, wherein a width of an upper surface of one of the plurality of first via electrodes is greater than a width of a lower surface of the one of the plurality of first via electrodes (fig. 2).
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2010041004A hereafter referred to as Sato.
In regards to claim 1, Sato discloses
A multilayer electronic component, comprising:
a body including a dielectric layer (VL – fig. 5-6; [0018]) and first and second internal electrodes (11 & 21 – fig. 5; [0019]) alternately disposed with the dielectric layer, and including first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction (seen in fig. 4-6);
a first external electrode (5 and/or 7 – fig. 4-5 & 9-10; [0016]) disposed on at least one surface among the first surface, the second surface, the fifth surface, and the sixth surface, and connected to the first internal electrodes;
a second external electrode (6 and/or 8 – fig. 4-5 & 9-10; [0016]) disposed on at least one surface among the first surface, the second surface, the third surface, and the fourth surface, and connected to the second internal electrodes; and
a first connection electrode (13 – fig. 5-6; [0019]) penetrating the dielectric layer and connecting two first internal electrodes adjacent to each other in the first direction (fig. 5-6),
wherein, in the first connection electrode, a plurality of first via electrodes shifted from each other in a direction perpendicular to the first direction are laminated in the first direction (seen in fig. 5-6).
In regards to claim 2, Sato discloses
The multilayer electronic component of claim 1, wherein a plurality of the first connection electrode penetrating the same dielectric layer are disposed (seen in fig. 5-6).
In regards to claim 3, Sato discloses
The multilayer electronic component of claim 2, wherein the plurality of the first connection electrodes penetrating the same dielectric layer are arranged in the second and third directions (seen in fig. 5-6).
In regards to claim 4, Sato discloses
The multilayer electronic component of claim 1, further comprising: a second connection electrode (23 – fig. 5-6; 0019]) penetrating the dielectric layer and connecting two second internal electrodes adjacent to each other in the first direction,
wherein, in the second connection electrode, a plurality of second via electrodes shifted from each other in the direction perpendicular to the first direction are laminated in the first direction (seen in fig. 5-6).
In regards to claim 5, Sato discloses
The multilayer electronic component of claim 1, further comprising: a first auxiliary electrode (31 – fig. 5; [0041]) spaced apart from one of the second internal electrodes in the third direction, and disposed between first via electrodes adjacent to each other among the plurality of first via electrodes (fig. 5).
In regards to claim 6, Sato discloses
The multilayer electronic component of claim 4, further comprising: a second auxiliary electrode (41 – fig. 5; [0044]) spaced apart from one of the first internal electrodes in the second direction, and disposed between second via electrodes adjacent to each other among the plurality of second via electrodes (fig. 5).
In regards to claim 7, Sato discloses
The multilayer electronic component of claim 1, wherein the first connection electrode includes a plurality of first connection electrodes, and two first connection electrodes adjacent to each other in the first direction among the plurality of first connection electrodes are shifted from each other in the direction perpendicular to the first direction (fig. 5-6).
In regards to claim 8, Sato discloses
The multilayer electronic component of claim 1, wherein the body includes a capacitance formation portion in which the first and second internal electrodes are alternately disposed in the first direction with the dielectric layer interposed therebetween (seen in fig. 5-6 – noting that instance when the VL layer is insulating; a capacitance will be formed), and a cover portion (topmost VL layer and/or bottommost VL layer) disposed on both surfaces of the capacitance formation portion opposing each other in the first direction (seen in fig. 5-6), wherein the first external electrode is disposed on at least one surface of the first and second surfaces (fig. 4-5 & 9-10), and wherein the multilayer electronic component includes a first contact electrode (15 and/or 25 – fig. 5 & 10; [0019]) penetrating the cover portion and connecting the first internal electrode disposed in an outermost region in the first direction to the first external electrode.
In regards to claim 9, Sato discloses
The multilayer electronic component of claim 8, wherein each of the first and second external electrodes is disposed on the second surface and is not disposed on the first surface (fig. 9-10).
In regards to claim 10, Sato discloses
The multilayer electronic component of claim 8, wherein the first external electrode is disposed on each of the first and second surfaces, and the second external electrode is disposed on each of the first and second surfaces (fig. 5-6), and
wherein the first and second external electrodes disposed on the first surface are spaced apart from the first and second external electrodes disposed on the second surface (fig. 5-6).
Claim(s) 25, 27, & 30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KR20180058034A hereafter referred to as Samsung.
In regards to claim 25, Samsung discloses
A multilayer electronic component, comprising:
a body (110 – fig. 1-3; [0038]) including a dielectric layer (111 – fig. 3; [0047]) and first and second internal electrodes (121-122 – fig. 3; [0047]) alternately disposed with the dielectric layer, and including first and second surfaces (1-2 – fig. 1-3; [0038]) opposing each other in a first direction, third and fourth surfaces (5-6 – fig. 1-3; [0038]) connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces (3-4 – fig. 1-3; [0038]) connected to the first to fourth surfaces and opposing each other in a third direction;
a first external electrode (131 – fig. 1-3; [0038]) disposed on at least one surface among the first surface, the second surface, the fifth surface, and the sixth surface, and connected to the first internal electrodes;
a second external electrode (132 – fig. 1-3; [0038]) disposed on at least one surface among the first surface, the second surface, the third surface, and the fourth surface, and connected to the second internal electrodes; and
a first connection electrode penetrating the dielectric layer and connecting two first internal electrodes adjacent to each other in the first direction,
wherein the first connection electrode (141 – fig. 3; [0047]) including one first via electrode (top portion of the hourglass shaped 141) extending directly from one of the two first internal electrodes and another first via electrode (bottom portion of the hourglass shaped 141) extending directly from another of the two first internal electrodes, and
the one first via electrode and the another first via electrode are both tapered in the first direction (seen in fig. 3-4).
In regards to claim 27, Samsung discloses
The multilayer electronic component of claim 25, further comprising:
a second connection electrode (142 – fig. 3; [0047]) penetrating the dielectric layer and connecting two second internal electrodes adjacent to each other in the first direction,
wherein the second connection electrode including one second via electrode (top portion of the hourglass shaped 142) extending directly from one of the two second internal electrodes and another second via electrode (bottom portion of the hourglass shaped 142) extending directly from another of the two second internal electrodes, and
the one second via electrode and the another second via electrode are both tapered in the first direction (fig. 3-4).
In regards to claim 30, Samsung discloses
The multilayer electronic component of claim 25, wherein the body includes a capacitance formation portion in which the first and second internal electrodes are alternately disposed in the first direction with the dielectric layer interposed therebetween, and a cover portion disposed on both surfaces of the capacitance formation portion opposing each other in the first direction (seen in fig. 3),
wherein the first external electrode is disposed on at least one surface of the first and second surfaces (seen in fig. 3), and
wherein the multilayer electronic component includes a first contact electrode (portion of 141 formed in cover layer) penetrating the cover portion and connecting the first internal electrode disposed in an outermost region in the first direction to the first external electrode.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11 & 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tani ‘278 in view of Ito et al. (US 2010/0008017).
In regards to claim 11,
Tani ‘278 discloses wherein the first internal electrode includes a first main portion overlapping the second internal electrode in the first direction, and a first lead portion extending from the first main portion toward the fifth surface or sixth surface (fig. 2-3). Tani ‘278 fails to disclose wherein a thickness of an end of the first lead portion exposed to the fifth surface or the sixth surface is greater than a thickness of a central portion of the first main portion in the third direction.
Ito ‘017 discloses wherein a thickness of an end of the first lead portion exposed to the fifth surface or the sixth surface is greater than a thickness of a central portion of the first main portion in the third direction (fig. 2 & 4; [0047-0049]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the lead portion of Tani ‘278 to be thicker as taught by Ito ‘017 to further improve the bonding strength of the plating layer.
In regards to claim 23,
Tani ‘278 fails to disclose wherein a thickness of an end exposed to the fifth surface or the sixth surface of the first lead portion is greater than a thickness of a central portion of the first main portion in the third direction.
Ito ‘017 discloses wherein a thickness of an end exposed to the fifth surface or the sixth surface of the first lead portion is greater than a thickness of a central portion of the first main portion in the third direction (fig. 2 & 4; [0047-0049]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the lead portion of Tani ‘278 to be thicker as taught by Ito ‘017 to further improve the bonding strength of the plating layer.
Claim(s) 13-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Ahn et al. (US 2014/0104750).
In regards to claim 13,
Sato discloses a multilayer electronic component, comprising:
a body including first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction (seen in fig. 4-6 & 9-11),
the body including a first internal electrode layer including a first dielectric layer (VL – fig. 5-6; [0018]) and a first internal electrode (11 – fig. 5; [0019]) disposed on the first dielectric layer and including a first main portion (12 – fig. 5; [0020]) and a first lead portion (14 – fig. 5; [0020]) extending from the first main portion,
the body including a second internal electrode layer including a second dielectric layer (VL – fig. 5-6; [0018]), a second internal electrode (21 – fig. 5; [0019]) disposed on the second dielectric layer and overlapping the first main portion in the first direction, and a first auxiliary electrode (31 – fig. 5; [0041]) spaced apart from the second internal electrode in the third direction,
wherein the first and second internal electrodes layers are alternately disposed in the first direction (fig. 5 & 10);
a first external electrode (5 and/or 7 – fig. 4-5 & 9-10; [0016]) disposed on at least one surface among the first surface, the second surface, the fifth surface, and the sixth surface, and connected to the first internal electrode;
a second external electrode (6 and/or 8 – fig. 4-5 & 9-10; [0016]) disposed on at least one surface among the first surface, the second surface, the third surface, and the fourth surface, and connected to the second internal electrode;
a first via electrode (13a – fig. 5-6; [0019]) penetrating the first dielectric layer and connecting the first lead portion to the first auxiliary electrode; and
a second via electrode (13b – fig. 5-6; 0019]) penetrating the second dielectric layer and connecting the first lead portion to the first auxiliary electrode,
wherein the first via electrode and the second via electrode are shifted from each other in a direction perpendicular to the first direction wherein, in the first connection electrode, a plurality of first via electrodes shifted from each other in a direction perpendicular to the first direction are laminated in the first direction (seen in fig. 5-6 & 10-11). Sato fails to discloses the first lead portion extending from the first main portion to the fifth surface or sixth surface.
Ahn ‘750 discloses the first lead portion extending from the first main portion to the fifth surface or sixth surface (fig. 11A-11B).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the leads of Sato to extend to the side surfaces as taught by Ahn ‘750 to obtain a component wherein a size of the product may be significantly reduced by reducing a thickness in a range in which insulation of the first and second internal electrodes and where the body has increased durability.
In regards to claim 14,
Sato as modified by Ahn ‘750 further discloses wherein the first and second via electrodes do not overlap each other in the first direction (fig. 5 of Sato).
In regards to claim 15,
Sato as modified by Ahn ‘750 further discloses wherein a plurality of the first via electrodes penetrating the same first dielectric layer are disposed, and a plurality of the second via electrodes penetrating the same second dielectric layer are disposed, and
wherein the first via electrodes penetrating the same first dielectric layer are arranged in the second and third directions, and the second via electrodes penetrating the same second dielectric layer are arranged in the second and third directions (fig. 5-6 & 10-11 of Sato).
In regards to claim 16,
Sato as modified by Ahn ‘750 further discloses wherein the first dielectric layer includes a first region disposed between two first via electrodes adjacent to each other in the second or third direction among a plurality of the first via electrodes, and
wherein the plurality of the second via electrodes overlap the first region in the first direction (fig. 6 & 11 of Sato).
In regards to claim 17,
Sato as modified by Ahn ‘750 further discloses wherein the second internal electrode includes a second main portion (22 – fig. 5; [0021] of Sato) overlapping the first internal electrode in the first direction, and a second lead portion (24– fig. 5; [0021] of Sato) extending from the second main portion to the third surface or the fourth surface (fig. 11 of Ahn ‘750),
wherein the first internal electrode layer further includes a second auxiliary electrode (41 – fig. 5; [0044] of Sato) disposed on the first dielectric layer and spaced apart from the first internal electrode in the second direction,
wherein the multilayer electronic component further includes a third via electrode (53a – fig. 5; [0045] of Sato) penetrating the first dielectric layer and connecting the second lead portion to the second auxiliary electrode, and a fourth via electrode (53b – fig. 5; [0045] of Sato) penetrating the second dielectric layer and connecting the second lead portion to the second auxiliary electrode, and
wherein the third via electrode and the fourth via electrode are shifted from each other in the direction perpendicular to the first direction (fig. 5-6 & 10-11 of Sato).
In regards to claim 18,
Sato as modified by Ahn ‘750 further discloses wherein a plurality of the third via electrodes penetrating the same first dielectric layer are disposed, and a plurality of the fourth via electrodes penetrating the same second dielectric layer are disposed, and
wherein the third via electrode penetrating the same first dielectric layer is arranged in the second and third directions, and the fourth via electrode penetrating the same second dielectric layer is arranged in the second and third directions (fig. 5-6 of Sato).
In regards to claim 19,
Sato as modified by Ahn ‘750 further discloses wherein the first dielectric layer includes a second region disposed between two third via electrodes adjacent to each other in the second direction or the third direction among a plurality of the third via electrodes, and
wherein a plurality of the fourth via electrodes overlap the second region in the first direction (fig. 5-6 of Sato).
In regards to claim 20,
Sato as modified by Ahn ‘750 further discloses wherein the body includes a capacitance formation portion (seen in fig. 5-6 of Sato – noting that instance when the VL layer is insulating; a capacitance will be formed) in which first and second internal electrodes are alternately disposed with the first dielectric layer or the second dielectric layer therebetween, and a cover portion (topmost VL layer and/or bottommost VL layer of Sato) disposed on both surfaces of the capacitance formation portion opposing each other in the first direction (seen in fig. 5-6 of Sato),
wherein the first external electrode is disposed on at least one of the first and second surfaces (seen in fig. 4-5 & 9-10 of Sato), and
wherein the multilayer electronic component further includes a first contact structure (15 and/or 25 – fig. 5 & 10; [0019] of Sato) penetrating the cover portion and connecting the first internal electrode or the first auxiliary electrode disposed in an outermost region in the first direction to the first external electrode.
In regards to claim 21,
Sato as modified by Ahn ‘750 further discloses wherein each of the first and second external electrodes is disposed on the second surface and is not disposed on the first surface (fig. 9-10 of Sato).
In regards to claim 22,
Sato as modified by Ahn ‘750 further discloses wherein first external electrode is disposed on each of the first and second surfaces, and the second external electrode is disposed on each of the first and second surfaces (fig. 5-6 of Sato), and
wherein the first and second external electrodes disposed on the first surface are spaced apart from the first and second external electrodes disposed on the second surface (fig. 5-6 of Sato).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato as modified by Ahn ‘750 13 as applied to claim 17 above, and further in view of JP2009177054A hereafter referred to as Sakaguchi.
In regards to claim 24,
Sato as modified by Ahn ‘750 fails to disclose wherein a width of an upper surface of the first via electrode is greater than a width of a lower surface of the first via electrode, and a width of an upper surface of the second via electrode is greater than a width of a lower surface of the second via electrode.
Sakaguchi discloses a width of an upper surface of the via electrode is greater than a width of a lower surface of the via electrode (fig. 1).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the vias of Sato to be tapered as taught by Sakaguchi to obtain a component wherein degradation of connection reliability is prevented and that has good electric characteristic.
Claim(s) 25-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Sakaguchi.
In regards to claim 25,
Sato discloses a multilayer electronic component, comprising:
a body including a dielectric layer (VL – fig. 5-6; [0018]) and first and second internal electrodes (11 & 21 – fig. 5; [0019]) alternately disposed with the dielectric layer, and including first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction (seen in fig. 4-6);
a first external electrode (5 and/or 7 – fig. 4-5 & 9-10; [0016]) disposed on at least one surface among the first surface, the second surface, the fifth surface, and the sixth surface, and connected to the first internal electrodes;
a second external electrode (6 and/or 8 – fig. 4-5 & 9-10; [0016]) disposed on at least one surface among the first surface, the second surface, the third surface, and the fourth surface, and connected to the second internal electrodes; and
a first connection electrode (13 – fig. 5-6; [0019]) penetrating the dielectric layer and connecting two first internal electrodes adjacent to each other in the first direction (fig. 5-6),
wherein the first connection electrode including one first via electrode extending directly from one of the two first internal electrodes and another first via electrode extending directly from another of the two first internal electrodes (seen in fig. 5-6).
Sato fails to disclose the one first via electrode and the another first via electrode are both tapered in the first direction.
Sakaguchi discloses the one first via electrode and the another first via electrode are both tapered in the first direction (fig. 1).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the vias of Sato to be tapered as taught by Sakaguchi to obtain a component wherein degradation of connection reliability is prevented and that has good electric characteristic.
In regards to claim 26,
Sato as modified by Sakaguchi further discloses wherein a plurality of the first connection electrode penetrating the same dielectric layer are disposed (fig. 5-6 of Sato).
In regards to claim 27,
Sato as modified by Sakaguchi further discloses further comprising:
a second connection electrode (23 – fig. 5-6; 0019]) penetrating the dielectric layer and connecting two second internal electrodes adjacent to each other in the first direction,
wherein the second connection electrode including one second via electrode extending directly from one of the two second internal electrodes and another second via electrode extending directly from another of the two second internal electrodes (fig. 5-6 of Sato)., and
the one second via electrode and the another second via electrode are both tapered in the first direction (fig. 1 of Sakaguchi).
In regards to claim 28,
Sato as modified by Sakaguchi further discloses further comprising: a second auxiliary electrode (41 – fig. 5; [0044] of Sato) spaced apart from one of the first internal electrodes in the second direction, and disposed between the one second via electrode and the another second via electrode (fig. 5 of Sato).
In regards to claim 29,
Sato as modified by Sakaguchi further discloses further comprising: a first auxiliary electrode (31 – fig. 5; [0041] of Sato) spaced apart from one of the second internal electrodes in the third direction, and disposed between the one first via electrode and the another first via electrode (fig. 5 of Sato).
In regards to claim 30,
Sato as modified by Sakaguchi further discloses wherein the body includes a capacitance formation portion (seen in fig. 5-6 of Sato – noting that instance when the VL layer is insulating; a capacitance will be formed) in which the first and second internal electrodes are alternately disposed in the first direction with the dielectric layer interposed therebetween, and a cover portion (topmost VL layer and/or bottommost VL layer of Sato) disposed on both surfaces of the capacitance formation portion opposing each other in the first direction,
wherein the first external electrode is disposed on at least one surface of the first and second surfaces (fig. 4-5 & 9-10 of Sato), and
wherein the multilayer electronic component includes a first contact electrode (15 and/or 25 – fig. 5 & 10; [0019] of Sato) penetrating the cover portion and connecting the first internal electrode disposed in an outermost region in the first direction to the first external electrode.
Claim(s) 31-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Ahn ‘750 and Sakaguchi.
In regards to claim 31,
Sato discloses a multilayer electronic component, comprising:
a body including first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction (seen in fig. 4-6 & 9-11),
the body including a first internal electrode layer including a first dielectric layer (VL – fig. 5-6; [0018]) and a first internal electrode (11 – fig. 5; [0019]) disposed on the first dielectric layer and including a first main portion (12 – fig. 5; [0020]) and a first lead portion (14 – fig. 5; [0020]) extending from the first main portion,
the body including a second internal electrode layer including a second dielectric layer (VL – fig. 5-6; [0018]), a second internal electrode (21 – fig. 5; [0019]) disposed on the second dielectric layer and overlapping the first main portion in the first direction, and a first auxiliary electrode (31 – fig. 5; [0041]) spaced apart from the second internal electrode in the third direction,
wherein the first and second internal electrodes layers are alternately disposed in the first direction (fig. 5 & 10);
a first external electrode (5 and/or 7 – fig. 4-5 & 9-10; [0016]) disposed on at least one surface among the first surface, the second surface, the fifth surface, and the sixth surface, and connected to the first internal electrode;
a second external electrode (6 and/or 8 – fig. 4-5 & 9-10; [0016]) disposed on at least one surface among the first surface, the second surface, the third surface, and the fourth surface, and connected to the second internal electrode;
a first via electrode (13a – fig. 5-6; [0019]) penetrating the first dielectric layer and directly connecting the first lead portion to the first auxiliary electrode; and
a second via electrode (13b – fig. 5-6; 0019]) penetrating the second dielectric layer and directly connecting the first lead portion to the first auxiliary electrode. Sato fails to discloses the first lead portion extending from the first main portion to the fifth surface or sixth surface & wherein the first via electrode and the second via electrode are both tapered in the first direction.
Ahn ‘750 discloses the first lead portion extending from the first main portion to the fifth surface or sixth surface (fig. 11A-11B).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the leads of Sato to extend to the side surfaces as taught by Ahn ‘750 to obtain a component wherein a size of the product may be significantly reduced by reducing a thickness in a range in which insulation of the first and second internal electrodes and where the body has increased durability.
Sakaguchi discloses wherein the first via electrode and the second via electrode are both tapered in the first direction (fig. 1).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the vias of Sato to be tapered as taught by Sakaguchi to obtain a component wherein degradation of connection reliability is prevented and that has good electric characteristic.
In regards to claim 32,
Sato as modified by Ahn ‘750 and Sakaguchi further discloses wherein the first and second via electrodes do not overlap each other in the first direction (fig. 5 & 10 of Sato).
In regards to claim 33,
Sato as modified by Ahn ‘750 and Sakaguchi further discloses wherein a plurality of the first via electrodes penetrating the same first dielectric layer are disposed, and a plurality of the second via electrodes penetrating the same second dielectric layer are disposed (fig. 5-6 & 10-11 of Sato), and
wherein the first via electrodes penetrating the same first dielectric layer are arranged in the second and third directions, and the second via electrodes penetrating the same second dielectric layer are arranged in the second and third directions (fig. 5-6 & 10-11 of Sato).
In regards to claim 34,
Sato as modified by Ahn ‘750 and Sakaguchi further discloses wherein the second internal electrode includes a second main portion (22 – fig. 5; [0021] of Sato) overlapping the first internal electrode in the first direction, and a second lead portion (24– fig. 5; [0021] of Sato) extending from the second main portion to the third surface or the fourth surface (fig. 11 of Ahn ‘750)
wherein the first internal electrode layer further includes a second auxiliary electrode (41 – fig. 5; [0044] of Sato) disposed on the first dielectric layer and spaced apart from the first internal electrode in the second direction,
wherein the multilayer electronic component further includes a third via electrode (53a – fig. 5; [0045] of Sato) penetrating the first dielectric layer and connecting the second lead portion to the second auxiliary electrode, and a fourth via electrode (53b – fig. 5; [0045] of Sato) penetrating the second dielectric layer and connecting the second lead portion to the second auxiliary electrode, and
wherein the third via electrode and the fourth via electrode are both tapered in the first direction (fig. 1 of Sakaguchi).
In regards to claim 35,
Sato as modified by Ahn ‘750 and Sakaguchi further discloses wherein a plurality of the third via electrodes penetrating the same first dielectric layer are disposed, and a plurality of the fourth via electrodes penetrating the same second dielectric layer are disposed, and
wherein the third via electrode penetrating the same first dielectric layer is arranged in the second and third directions, and the fourth via electrode penetrating the same second dielectric layer is arranged in the second and third directions (fig. 5-6 of Sato).
In regards to claim 36,
Sato as modified by Ahn ‘750 and Sakaguchi further discloses wherein the body includes a capacitance formation portion (seen in fig. 5-6 of Sato – noting that instance when the VL layer is insulating; a capacitance will be formed) in which first and second internal electrodes are alternately disposed with the first dielectric layer or the second dielectric layer therebetween, and a cover portion (topmost VL layer and/or bottommost VL layer of Sato) disposed on both surfaces of the capacitance formation portion opposing each other in the first direction,
wherein the first external electrode is disposed on at least one of the first and second surfaces (fig. 4-5 & 9-10 of Sato), and
wherein the multilayer electronic component further includes a first contact structure (15 and/or 25 – fig. 5 & 10; [0019] of Sato) penetrating the cover portion and connecting the first internal electrode or the first auxiliary electrode disposed in an outermost region in the first direction to the first external electrode.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2006/0180899 – [0028] US 10,026,558 – fig. 3
US 2020/0118497 – fig. 3 US 2007/0041146 – fig. 17
US 2025/0118497 – fig. 6 US 2019/0066922 – fig. 7
US 2012/0120546 – fig. 7 JP02251120A – fig. 1
Communication
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/David M Sinclair/Primary Examiner, Art Unit 2847
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