DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/12/2026 has been entered.
Response to Amendment
The amendment filed on 05/12/2026 has been considered by Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa et al (US 2020/0105176 A1) in view of Chung (US 2011/0187691 A1) and Na et al (US 2016/0171938 A1).
Claim 1, Kurokawa (Fig. 1-16C) discloses a display device (Fig. 16A-16C), comprising:
a display panel (20; Fig. 1) including an active area (21; Fig. 2) in which a plurality of pixels (51; Fig. 2) is disposed and a non-active area (22-24; Fig. 2; wherein figure shows an area that surrounds the display area 21 with the driving elements 22-23) which encloses the active area (21; Fig. 1); and
a gate driver (23; Fig. 1, 2, 3A, and 4A) configured to be driven in a first mode (Fig. 6; wherein figure shows a first mode of driving in which the switches GSL_SW (Fig. 3A and 4A) selects the input portion r to output a sequential driving method) or a second mode (Fig. 6; wherein figure shows a first mode of driving in which the switches GSL_SW (Fig. 3A and 4A) selects the input portion s to output a double scanning driving method) to supply a gate signal (Fig. 6) to the plurality of pixels (51; Fig. 3A and 2),
wherein the gate driver (23; Fig. 1, 2, 3A and 4A) includes:
a plurality of stages (65; Fig. 4A); and
a mode controller (GSL_SW; Fig. 3A and 4A) connected between the plurality of stages (65; Fig. 4A) to control an operation (Fig. 6) of the gate driver (65; Fig. 4A) according to a mode control signal (Fig. 3C; Paragraph [0104-0106]),
wherein in the first mode (Fig. 5 and 6; wherein both figures show the operation of “Switch GSL_SW selects input portion r” as the first mode), the mode controller connects (GSL_SW in both figures 3A and 4A; Paragraph [0112]; wherein states “Note that all the switches GSL_SW included in the logic circuit portion 63 (Fig. 4A) are in conjunction with the switches GSL_SW included in the selectors GSL[1] to GSL[l] (Fig. 3A)”) ) the plurality of stages (65; Fig. 4A; wherein figure shows at least five stages) to one another (Fig. 4A and 5; Paragraph [0113-0014]; wherein states “Furthermore, as for the signals G0′[1] to G0′[8] output from the logic circuit portion 63, three states are shown: a state in which the switch GSL_SW selects the input portion r, a state in which the switch GSL_SW selects the input portion s, and a state in which the switch GSL_SW selects the input portion t” and “In the state where the switch GSL_SW selects the input portion r, at the timing of a fall of the clock signal CLK when the start pulse SP is High, the signals G0′[1] to G0′[8] are sequentially output as pulse-like signals. When the potentials and the like of the signals G0′[1] to G0′[8] are adjusted by the output adjustment portion 64, the signals can be used as signals for sequentially selecting the gate lines G[1] to G[8]”) and connects output terminals (G0’[1]-G0’[5]; Fig. 4A) of the plurality of stages (65; Fig. 4A) to gate lines (G[1]-G[4]; Fig. 3A; Fig. 6; Paragraph [0119-0120]; wherein discloses “In the state where the switch GSL_SW selects (Fig. 3A) the input portion r, the timing chart of the gate lines G[1] to G[8] (Fig. 6) is the same as that of the signals G0′[1] to G0′[8] (Fig. 5)”), and
wherein in the second mode (Fig. 5 and 6; wherein both figures show the operation of “Switch GSL_SW selects input portion s” as the second mode), the mode controller (GSL_SW in both figures 3A and 4A; Paragraph [0112]; wherein states “Note that all the switches GSL_SW included in the logic circuit portion 63 (Fig. 4A) are in conjunction with the switches GSL_SW included in the selectors GSL[1] to GSL[l] (Fig. 3A)”) ) connects an output terminal (G0’[1]; Fig. 4A) of a (2n- 1)th stage (Fig. 4A; wherein figure shows a first stage 65 which is connected to the output terminal G0’[1]) among the plurality of stages (65; Fig. 4A; wherein figure shows at least five stages) to an input terminal (Fig. 4A; wherein figure shows the input terminal of the third stage is connected through GSL_SW during mode S to the output terminal G0’[1] of the first stage; wherein said mode S then provides the driving signals as shown in figure 5) of a (2n+1)th stage (Fig. 4A; wherein figure shows during mode S in figure 5 the third stage is connected to the output G0’[1] through the switch GSL_SW in mode S) , and connects (Figure 6 and 3A; Paragraph [0121]; wherein discloses “In the state where the switch GSL_SW selects the input portion s, the same signal as that of the gate line G[1] is output to the gate line G[2]”) a (2n-1)th gate line (G[1]; Fig. 6 during mode S; G[1]; Fig. 3A) to a (2n)th gate line (G[2]; Fig. 6 during mode S; G[2]; Fig. 3A).
Kurokawa does not expressly disclose the mode controller including:
a first control transistor connected between an output terminal of a (2n-1)th stage and an input terminal of a (2n)th stage, among the plurality of stages; and
a fourth control transistor connected between the output terminal of the (2n-1)th stage and an input terminal of a (2n+1)th stage.
Chung (Fig. 1-13) discloses the mode controller (1-5; Fig. 1) including:
a first control transistor (Tr1-1; Fig. 1) connected between an output terminal (out; Fig. 1) of a (2n-1)th stage (STG1; Fig. 1) and an input terminal (in; Fig. 1) of a (2n)th stage (STG2; Fig. 1), among the plurality of stages (STG1-STG5; Fig. 1); and
a fourth control transistor (Tr2-2; Fig. 1) connected between the output terminal (out; Fig. 1) of the (2n-1)th stage (STG1; Fig. 1) and an input terminal (in; Fig. 1) of a (2n+1)th stage (STG3; Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kurokawa’s display device by applying input selected circuits, as taught by Chung, so to use a display device with input selected circuits for providing a scan driver capable of performing progressive scanning and interlaced scanning, and a flat panel display apparatus including the scan driver (Paragraph [0010]).
Kurokawa in view of Chung does not expressly disclose the mode controller including:
a second control transistor connected to an output terminal of the (2n)th stage;
a third control transistor connected between the output terminal of the (2n-1)th stage and an output terminal of a (2n)th stage.
Na (Fig. 1-7) discloses the mode controller (TR7 and TR8; Fig. 3) including:
a second control transistor (TR8; Fig. 3) connected to an output terminal of the (2n)th stage (410a2; Fig. 3);
a third control transistor (TR7; Fig. 3) connected between the output terminal of the (2n-1)th stage (410a1; Fig. 3) and an output terminal of a (2n)th stage (410a2; Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kurokawa in view of Chung’s display device by applying a mode controlling circuit, as taught by Na, so to use a display device with a mode controlling circuit for providing a liquid crystal display (LCD) device capable of allowing a user to switch the LCD device from one driving mode to another driving mode and to adjust resolution (Paragraph [0007]).
Claim 2, Kurokawa (Fig. 1-16C) discloses wherein the gate driver (23; Fig. 1, 2, 3A, and 4A) is configured to output the gate signal output (G0’[1]-G0’[5]; Fig. 4A) from the plurality of stages (65; Fig. 4A) to gate lines (G[1]-G[4]; Fig. 3A) connected to each of the plurality of stages (65; Fig. 4A) in the first mode (Paragraph [0105]) and to output the gate signal output ((G0’[1]; Fig. 4A) from a (2n-1)th stage (Fig. 4A; wherein a first stage outputs G0’[1]), among the plurality of stages (65; Fig. 4A), to a gate line (G[1}; Fig. 3A) connected to the (2n-1)th stage (G0[1]; Fig. 3A) and a gate line (G[2]; Fig. 3A) connected to a (2n)th stage (G0[2]; Fig. 3A and 4A), among the plurality of stages (65; Fig. 4A), in the second mode (Paragraph [0106]; wherein discloses “When the switch GSL_SW selects the input portion “s”, from the selector GSL[1], the signal G0[1] is output to the gate line G[1] and the gate line G[2], and the signal G0[3] is output to the gate line G[3] and the gate line G[4]”).
Claim 3, Kurokawa (Fig. 1-16C) discloses further comprising:
a timing controller (24; Fig. 1) configured to supply the mode control signal (Paragraph [0113] and [0120-0122]; wherein discloses the control of the switching circuit GSL_SW in figure 3C to be controlled with three different modes) to the mode controller (GSL_SW; Fig. 3A, 3C, and 4A).
Claim 4, Kurokawa (Fig. 1-16C) discloses further comprising:
a plurality of data lines (S[1]-S[m]; Fig. 2) connected to the plurality of pixels (51; Fig. 2) to supply a data voltage (Paragraph [0071]); and
a plurality of gate lines (G[1]-G[n]; Fig. 2) connected to the plurality of stages (65; Fig. 4A) one to one to supply the gate signal (G0’[1]-G0Fig. 5).
Claim 6, Kurokawa (Fig. 1-16C) discloses wherein the mode control signal (Paragraph [0113] and [0120-0122]) includes a first mode control signal (Paragraph [0114] and [0120]; wherein switches GSL_SW are controlled to select r terminal) and a second mode control signal (Paragraph [0115] and [0121] wherein switches GSL_SW are controlled to select s terminal) wherein:
the first control transistor (GSL_SW wherein connected between terminal r and p; Fig. 4A and 3C; wherein figure shows the switching circuit as a multiplexer 3:1 which is known to be comprised of three transistors circuits, a first transistor connected between r and p, a second transistor connected between s and p, and a third transistor connected between t and p; therefore as shown in figures 4A and 3C; figure shows a first control transistor part of GSL_SW connected between r and p and arranged between output of first unit 65 and input of second unit 65) is configured to be turned on according to the first mode control signal (Paragraph [0114]; Fig. 5);
the second control transistor (GSL_SW wherein connected between terminal r and p; Fig. 3A and 3C; wherein figure shows the switching circuit as a multiplexer 3:1 which is known to be comprised of three transistors circuits, a first transistor connected between r and p, a second transistor connected between s and p, and a third transistor connected between t and p; therefore as shown in figures 3A and 3C; figure shows a first control transistor part of GSL_SW connected between r and p and arranged between output of G0[2] and gate line of G[2])) is configured to be turned on according to the first mode control signal (Paragraph [0020]; Fig. 6);
the third control transistor (GSL_SW wherein connected between terminal s and p; Fig. 3A and 3C; wherein figure shows the switching circuit as a multiplexer 3:1 which is known to be comprised of three transistors circuits, a first transistor connected between r and p, a second transistor connected between s and p, and a third transistor connected between t and p; therefore as shown in figures 3A and 3C; figure shows a second control transistor part of GSL_SW connected between s and p and arranged between output of G0[1] and gate line of G[2]) is configured to be turned on according to the second mode control signal (Paragraph [0121]; Fig. 6);
the fourth control transistor (GSL_SW wherein connected between terminal s and p; Fig. 4A and 3C; wherein figure shows the switching circuit as a multiplexer 3:1 which is known to be comprised of three transistors circuits, a first transistor connected between r and p, a second transistor connected between s and p, and a third transistor connected between t and p; therefore as shown in figures 4A and 3C; figure shows a second control transistor part of GSL_SW connected between s and p and arranged between output of first unit 65 and input of third unit 65) is configured to be turned on according to the second mode control signal (Paragraph [0115]; Fig. 5); and
the mode controller (GSL_SW; Fig. 3A and 4A) further includes a fifth control transistor (GSL_SW wherein connected between terminal r and p; Fig. 4A and 3C; wherein figure shows the switching circuit as a multiplexer 3:1 which is known to be comprised of three transistors circuits, a first transistor connected between r and p, a second transistor connected between s and p, and a third transistor connected between t and p; therefore as shown in figures 4A and 3C; figure shows a first control transistor part of GSL_SW connected between r and p and arranged between output of second unit 65 and input of third unit 65) connected between the output terminal of the (2n)th stage (second unit 65; Fig. 4A) and the input terminal of a (2n+1)th stage (third unit 65; Fig. 4A) and is configured to be turned on according to the first mode control signal (Paragraph [0114]; Fig. 5).
Claim 14, Kurokawa (Fig. 1-16C) discloses a display device (Fig. 16A-16C), comprising:
a display panel (20; Fig. 1); and
a gate driver (23; Fig. 1, 2, 3A, and 4A) which supplies a gate signal (Fig. 5 and 6) to the plurality of pixels (51; Fig. 2),
wherein the gate driver (23; Fig. 1, 2, 3A, and 4A) includes:
a plurality of stages (65; Fig. 4A); and
a mode controller (GSL_SW; Fig. 4A and 3A) connected with the plurality of stages (65; Fig. 4A) to control the gate driver (23; Fig. 1, 2, 3A, and 4A) to be driven in a first mode (Paragraph [0114] and [0120]) or a second mode (Paragraph [0115] and [0121]) according to a mode control signal (Fig. 5 and 6; wherein figure shows GSL_SW are selected in different mode when selecting r terminal or s terminal),
wherein, in the first mode (Paragraph [0114] and [0120]), the plurality of stages (65; Fig. 4A) are connected (GSL_SW) such that a gate signal output from one stage is input to an input terminal of a next stage (Paragraph [0114]; Fig. 5 for switch GSL_SW selects input portion r), and output terminals (65; Fig. 4A; wherein figure shows respective stages 65 having respective output terminals G0’[1]-G01[5])) of the plurality of stages (65; Fig. 4A) are respectively connected (Fig. 3A; wherein during R mode of 3A and 6; the figures shows the GSL_SW during R mode provide the input from signals (G0’[1]-G01[4]) to the gate lines (G1-G4); Paragraph [0120]) to the plurality of gate lines (G1-G4; Fig. 3A),
wherein, in the second mode (Paragraph [0115] and [0121]), only odd-numbered stages (Fig. 4A; wherein first and third units 65) or even-numbered stages among the plurality of stages are connected (GSL_SW; Fig. 4A) such that a gate signal output from one stage is input to an input terminal of a next stage (Paragraph [0115]; Fig. 5 for switch GSL_SW selects input portion s) and the odd-numbered gate lines (G[1], G[3], G[5] and G[7]; Fig. 3A and 6; wherein during mode S) are connected to (Paragraph [0121]; wherein discloses “In the state where the switch GSL_SW selects the input portion s, the same signal as that of the gate line G[1] is output to the gate line G[2], the same signal as that of the gate line G[3] is output to the gate line G[4], the same signal as that of the gate line G[5] is output to the gate line G[6], and the same signal as that of the gate line G[7] is output to the gate line G[8]. This is because the selectors GSL[1] and GSL[2] transmit one signal to two gate lines”) the even-number gate lines (G[2], G[4], G[6], and G[8]; Fig. 3A and 6; wherein during mode S).
Kurokawa in view of Chung does not expressly disclose the mode controller including:
a second control transistor connected to an output terminal of the (2n)th stage;
a third control transistor connected between the output terminal of the (2n-1)th stage and an output terminal of a (2n)th stage.
Na (Fig. 1-7) discloses the mode controller (TR7 and TR8; Fig. 3) including:
a second control transistor (TR8; Fig. 3) connected to an output terminal of the (2n)th stage (410a2; Fig. 3);
a third control transistor (TR7; Fig. 3) connected between the output terminal of the (2n-1)th stage (410a1; Fig. 3) and an output terminal of a (2n)th stage (410a2; Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kurokawa in view of Chung’s display device by applying a mode controlling circuit, as taught by Na, so to use a display device with a mode controlling circuit for providing a liquid crystal display (LCD) device capable of allowing a user to switch the LCD device from one driving mode to another driving mode and to adjust resolution (Paragraph [0007]).
Claim 15, Kurokawa (Fig. 1-16C) discloses wherein the mode controller (GSL_SW; Fig. 4A and 3A) includes a plurality of control transistors (GSL_SW; Fig. 4A and 3C; wherein figure shows the switching circuit as a multiplexer 3:1 which is known to be comprised of three transistors circuits, a first transistor connected between r and p, a second transistor connected between s and p, and a third transistor connected between t and p; therefore as shown in figures 4A and 3C) connected between the plurality of stages (65; Fig. 4A), and wherein the mode controller (GSL_SW; Fig. 4A) includes a first mode control signal (Paragraph [0114]) and a second mode control signal (Paragraph [0115]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa et al (US 2020/0105176 A1) in view of Chung (US 2011/0187691 A1) and Na et al (US 2016/0171938 A1) as applied to claim 1 above, and further in view of Lee et al (KR 2016-0081635 A).
Claim 5, Kurokawa in view of Chung and Na discloses the display device according to claim 1.
Kurokawa in view of Chung and Na does not expressly disclose further comprising:
a plurality of first data lines configured to supply a data voltage to pixels disposed in odd-numbered pixel lines, among the plurality of pixels;
a plurality of second data lines configured to supply a data voltage to pixels disposed in even-numbered pixel lines, among the plurality of pixels; and
a first gate line and a second gate line which are connected to the plurality of stages and supply the same gate signal to pixels disposed in two adjacent pixel lines.
Lee (Fig. 1-4) discloses further comprising:
a plurality of first data lines (DL_O1-DL_On; Fig. 3) configured to supply a data voltage (Data_odd; Fig. 4) to pixels disposed in odd-numbered pixel lines (H1, H3, …; Fig. 3), among the plurality of pixels (P; Fig. 3);
a plurality of second data lines (DL_E1-DL_En; Fig. 3) configured to supply a data voltage (Data_even; Fig. 4) to pixels disposed in even-numbered pixel lines H2, H4,…; Fig. 3), among the plurality of pixels (P; Fig. 3); and
a first gate line (GL1; Fig. 3) and a second gate line (GL2; Fig. 3) which are connected to the plurality of stages (400; Fig. 1) and supply the same gate signal (G1; Fig. 4; wherein discloses “During the first scan period TS1, the pixels P connected to the first odd gate line GL1 and the first even gate line GL2 are simultaneously scanned by the first gate pulse G1. The pixels P arranged in the first odd horizontal line HL1 charge the first odd data voltage DATA_O1 and the pixels P arranged in the first even horizontal line HL2 charge the first even data voltage DATA_E1)”) to pixels disposed in two adjacent pixel lines (H1 and H2; Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kurokawa in view of Chung and Na’s display device by applying a display circuit arrangement, as taught by Lee, so to use a display device with a display circuit arrangement for providing the horizontal dim phenomenon can be improved in the double-scan driving method, the present invention is advantageously applied to an ultra-high resolution display panel and a display device (Page 5 of translation).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa et al (US 2020/0105176 A1) in view of Chung (US 2011/0187691 A1) and Na et al (US 2016/0171938 A1) as applied to claim 1 above, and further in view of Lee et al (US 2006/0232591 A1).
Claim 7, Kurokawa in view of Chung and Na discloses the display device according to claim 1.
Kurokawa in view of Chung and Na does not expressly disclose wherein the active area of the display panel includes a first active area in which a first image is displayed and a second active area in which a second image is displayed and the first active area and the second active area have different resolutions.
Lee (Fig. 1a-9) discloses wherein the active area of the display panel (920; Fig. 9) includes a first active area (Fig. 5; wherein figure shows control only four gate lines as a first area) in which a first image is displayed (Fig. 5; wherein figure shows normal resolution driving mode) and a second active area (Fig. 5; wherein figure shows control only four gate lines as a second area) in which a second image is displayed (Fig. 5; wherein figure shows half resolution driving mode) and the first active area (Fig. 5; wherein figure shows normal resolution driving mode) and the second active area (Fig. 5; wherein figure shows half resolution driving mode) have different resolutions (Fig. 1a and 1b).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kurokawa in view of Chung and Na’s display device by applying different resolutions, as taught by Lee, so to use a display device with different resolutions for providing a circuit configuration for dual resolution modes in a display apparatus, which is low cost, small area and well performance (Paragraph [0010]).
Claim 8, Lee (Fig. 1a-9) discloses wherein the first active area (Fig. 5; wherein figure shows normal resolution driving mode) and the second active area (Fig. 5; wherein figure shows half resolution driving mode) have a same driving frequency (Fig. 5; wherein figure 5 shows driving pulse duration remains the same during both resolutions).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kurokawa in view of Chung and Na’s display device by applying different resolutions, as taught by Lee, so to use a display device with different resolutions for providing a circuit configuration for dual resolution modes in a display apparatus, which is low cost, small area and well performance (Paragraph [0010]).
Claims 9-11, 13, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa et al (US 2020/0105176 A1) in view of Chung (US 2011/0187691 A1) and Na et al (US 2016/0171938 A1) as applied to claim 1 above, and further in view of Lee et al (US 2018/0144688 A1).
Claim 9, Kurokawa in view of Chung and Na discloses the display device according to claim 1.
Kurokawa in view of Chung and Na does not expressly disclose wherein the gate driver is disposed in non-active areas on both sides of the active area.
Lee (Fig. 1-8B) discloses wherein the gate driver (130; Fig. 3) is disposed in non-active areas (ND; Fig. 3) on both sides (130; Fig. 3; Paragraph [0063]) of the active area (DA; Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kurokawa in view of Chung and Na’s display device by applying a gate driver arrangement, as taught by Lee, so to use a display device with a gate driver arrangement for providing a driving circuit for turning off pixels disposed at certain rows of the display panel (Paragraph [0014]).
Claims 10 and 16, Kurokawa in view of Chung and Na discloses the display device according to claims 1 and 14.
Kurokawa in view of Chung and Na does not expressly disclose wherein the gate driver includes a plurality of scan drivers and an emission driver.
Lee (Fig. 1-8B) discloses wherein the gate driver (Paragraph [0063]) includes a plurality of scan drivers (130; Fig. 3) and an emission driver (140; Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kurokawa in view of Chung and Na’s display device by applying a gate driver arrangement, as taught by Lee, so to use a display device with a gate driver arrangement for providing a driving circuit for turning off pixels disposed at certain rows of the display panel (Paragraph [0014]).
Claims 11 and 17, Lee (Fig. 1-8B) discloses wherein at least one of the plurality of scan drivers includes an edge trigger circuit (Fig. 6B) and the remaining scan drivers and the emission driver include shift register circuits (Fig. 6A).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kurokawa in view of Chung and Na’s display device by applying a gate driver arrangement, as taught by Lee, so to use a display device with a gate driver arrangement for providing a driving circuit for turning off pixels disposed at certain rows of the display panel (Paragraph [0014]).
Claim 13, Lee (Fig. 1-8B) discloses wherein the edge trigger circuit (Fig. 6B) includes:
a (2-1)th transistor (T1; Fig. 6B) having a source electrode connected to a line which supplies a start signal (EVST; Fig. 6B), a drain electrode connected to a Q′ node (Q; Fig. 6B), and a gate electrode connected to a line to which a clock signal of a nth stage is applied (ECLK(n); Fig. 6B);
a (2-2)th transistor (T3; Fig. 6B) having a source electrode connected to a line which supplies the gate high voltage (VEH; Fig. 6B), a drain electrode connected to a QC node (Fig. 6B; wherein figure shows electrode of transistor T3 connected to node which is connected to capacitor CQ’ and gate of transistor T2), and a gate electrode connected to a line which supplies the start signal (EVST; Fig. 6B);
a (2-3)th transistor (T2; Fig. 6B) having a source electrode connected to a line to which a clock signal of an n-th stage is applied (ECLK(n); Fig. 6B), a drain electrode connected to the QB node (QB; Fig. 6B), and a gate electrode connected to the QC node (Fig. 6B; wherein figure shows electrode of transistor T3 connected to node which is connected to capacitor CQ’ and gate of transistor T2);
a (2-4)th transistor (T4; Fig. 6B) having a source electrode connected to the line which supplies the gate high voltage (VEH; Fig. 6B), a drain electrode connected to the QB node (QB; Fig. 6B), and a gate electrode connected to the Q′ node (Q; Fig. 6B);
a (2-5)th transistor (T6; Fig. 6B) having a source electrode connected to the Q′ node (Q; Fig. 6B), a drain electrode connected to a Q node (QA; Fig. 6B), and a gate electrode connected to a line which supplies a gate low voltage (VEL; Fig. 6B);
a (2-6)th transistor (Tq; Fig. 6B) having a source electrode connected to the line which supplies the gate low voltage (VEL; Fig. 6B), a drain electrode connected to an output terminal (EM-out(n); Fig. 6B), and a gate electrode connected to the Q node (QA; Fig. 6B);
a (2-7)th transistor (Tqb_a and Tqb_b; Fig. 6B) having a source electrode connected to the line which supplies the gate high voltage (VEH; Fig. 6B), a drain electrode connected to the output terminal (EM-out(n); Fig. 6B), and a gate electrode connected to the QB node (QB; Fig. 6B);
a (2-1)th capacitor (CQ’; Fig. 6B) having a first electrode connected to a line to which a clock signal of the n-th stage is applied (ECLK(n); Fig. 6B) and a second electrode connected to the QC node (Fig. 6B; wherein figure shows electrode of transistor T3 connected to node which is connected to capacitor CQ’ and gate of transistor T2);
a (2-2)th capacitor (CB; Fig. 6B) having a first electrode connected to the Q node (QA; Fig. 6B) and a second electrode connected to the output terminal (EM-out(n); Fig. 6B); and
a (2-3)th capacitor (CQB; Fig. 6B) having a first electrode connected to the QB node (QB; Fig. 6B) and a second electrode connected to the line which supplies the gate high voltage (VEH; Fig. 6B).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kurokawa in view of Chung and Na’s display device by applying a gate driver arrangement, as taught by Lee, so to use a display device with a gate driver arrangement for providing a driving circuit for turning off pixels disposed at certain rows of the display panel (Paragraph [0014]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa et al (US 2020/0105176 A1) in view of Chung (US 2011/0187691 A1), Na et al (US 2016/0171938 A1), and Lee et al (US 2018/0144688 A1) as applied to claim 11 above, and further in view of Park et al (US 10,991,302 B1).
Claim 12, Lee (Fig. 1-8B) discloses wherein the shift register circuit (Fig. 6A) includes:
a (1-1)th transistor (T1; Fig. 6A) having a source electrode connected to a line which supplies a start signal (GVST; Fig. 6A), a drain electrode connected to a Q′ node (Q; Fig. 6A), and a gate electrode connected to a line to which a clock signal of a (n-1)th stage is applied (GCLK1; Fig. 6A; Fig. 4A; wherein both GCLK1 and GCLK2 are applied to all the stages);
a (1-2)th transistor (T3; Fig. 6A) having a source electrode connected to a line which supplies a gate high voltage (VGH; Fig. 6A), a drain electrode connected to the Q′ node (Q; Fig. 6A; wherein connected to node Q thought enabled transistor T2), and a gate electrode connected to a QB node (QB; Fig. 6A);
a (1-3)th transistor (T4; Fig. 6A) having a source electrode connected to the line which supplies the gate low voltage (see 112 1st rejection above; VGL; Fig. 6A), a drain electrode connected to the QB node (QB; Fig. 6A), and a gate electrode connected to a line to which a clock signal of a (n+2)th stage is applied (GCLK1; Fig. 6A; Fig. 4A; wherein both GCLK1 and GCLK2 are applied to all the stages);
a (1-6)th transistor (T6; Fig. 6A) having a source electrode connected to the Q′ node (Q; Fig. 6A), a drain electrode connected to a Q node (QA; Fig. 6A), and a gate electrode connected to a line which supplies a gate low voltage (VGL; Fig. 6A);
a (1-7)th transistor (Tq; Fig. 6A)having a source electrode connected to a line to which a clock signal of an n-th stage is applied (GCLK2; Fig. 6A), a drain electrode connected to an output terminal (Scan-out(n); Fig. 6A), and a gate electrode connected to the Q node (QA; Fig. 6A);
a (1-8)th transistor (Tqb; Fig. 6A) having a source electrode connected to the line which supplies the gate high voltage (VGH; Fig. 6A), a drain electrode connected to the output terminal (Scan-out(n); Fig. 6A), and a gate electrode connected to the QB node (QB; Fig. 6A);
a (1-1)th capacitor (CB; Fig. 6A) having a first electrode connected to the Q node (QA: Fig. 6A) and a second electrode connected to the output terminal (Scan-out(n); Fig. 6A); and
a (1-2)th capacitor (CQB; Fig. 6A) having a first electrode connected to the QB node (QB; Fig. 6A) and a second electrode connected to the line which supplies the gate high voltage (VGH; Fig. 6A).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kurokawa in view of Chung and Na’s display device by applying a gate driver arrangement, as taught by Lee, so to use a display device with a gate driver arrangement for providing a driving circuit for turning off pixels disposed at certain rows of the display panel (Paragraph [0014]).
Kurokawa in view of Chung, Na, and Lee does not expressly disclose a (1-4)th transistor having a source electrode connected to the line which supplies the gate high voltage, a drain electrode connected to the QB node, and a gate electrode connected to a line which supplies the start signal; and
a (1-5)th transistor having a source electrode connected to the line which supplies the gate high voltage, a drain electrode connected to the QB node, and a gate electrode connected to the Q′ node.
Park (Fig. 4) discloses a (1-4)th transistor (T11; Fig. 4) having a source electrode connected to the line which supplies the gate high voltage (VGH2; Fig. 4), a drain electrode connected to the QB node (QB-node; Fig. 4), and a gate electrode connected to a line which supplies the start signal (VST; Fig. 4); and
a (1-5)th transistor (T12; Fig. 4) having a source electrode connected to the line which supplies the gate high voltage (VGH2; Fig. 4), a drain electrode connected to the QB node (QB-node; Fig. 4), and a gate electrode connected to the Q′ node (Q’-node; Fig. 4).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kurokawa in view of Chung, Na, and Lee’s display device by applying a shift register circuit arrangement, as taught by Park, so to use a display device with a shift register circuit arrangement for providing a gate driving circuit and a display device using the same which can realize a narrow bezel (Col. 1, Lines 65-67).
Response to Arguments
Applicant's arguments with respect to claims 1-17 have been considered but are moot in view of the new ground(s) of rejection.
In view of arguments, the references of Kurokawa et al (US 2020/0105176 A1), Chung (US 2011/0187691 A1), Na et al (US 2016/0171938 A1), Lee et al (US 2018/0144688 A1), Lee et al (KR 2016-0081635 A), Lee et al (US 2006/0232591 A1), and Park et al (US 10,991,302 B1) have been used for new ground rejection.
Claims 1 and 14 are rejected in view of newly discovered reference(s) to Chung (US 2011/0187691 A1) and Na et al (US 2016/0171938 A1).
Conclusion
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/Adam J Snyder/Primary Examiner, Art Unit 2623 05/22/2026
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