DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 12/13/2023. It is noted, however, that applicant has not filed a certified copy of the Foreign Priority application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 13-15, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. Pub. No. 2020/0152123) in view of Okuno (U.S. Pub. No. 2015/0154910).
As to claim 1, Kim teaches a display apparatus (1001) comprising:
a display panel (100, Fig. 1) with a plurality of data lines (DL), a plurality of gate lines (SL), and a plurality of pixels disposed thereon (pixels P are disposed on the display),
the display panel (100) being configured to operate in a display mode or a sensing mode ([0042], lines 1-4);
a gate driver (gate driver comprising of circuits 200 and 300) configured to supply a scan signal (outputting scan signal SL1, [0060], lines 1-2 and [0075], lines 1-4),
a data driver (400) configured to supply a data signal to the plurality of data lines ([0055], lines 3-5);
a power supply (500) configured to apply an initialization voltage to the plurality of pixels in the sensing mode ([0058], lines 4-7); and
a sensing unit (sensing unit comprising of transistor T3, sensing signal SSLi, electrode RL, and compensator 500 functioning as a sensing unit, Fig. 1 and Fig. 2) configured to sense degradation of the plurality of pixels in the sensing mode ([0042], lines1-7 and [0070], lines 1-13, the third transistor connects the first transistor to the readout line. When a sensing signal is sent, T3 allows a small current to flow to the read out line. This small current is also sent to a compensator. By measuring this current and the voltage of T1, the system can figure out how T1 is changing over time, such as changes in its mobility or threshold voltage. In one example, the current is turned into a voltage, and that voltage is then used to make corrections.)
Kim does not mention an emission control signal,
Okuno teaches a gate driver (Fig. 1, 30) configured to supply an emission control signal to the plurality of gate lines (scan driver 30 applies emission control signals to emission control lines 31-33, [0057], lines 3-6).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the scan driver 30 of Okuno to the display apparatus of Kim because the scan driver 30 controls each of the plurality of pixels 100, [0051], lines 4-5).
As to claim 13, Kim teaches the display apparatus of claim 1,
Kim does not teach an emission control driver,
Okuno teaches the gate driver comprises one scan driver (20) and one emission control driver (30) respectively disposed at opposite sides of an active area (the gate driver has one scan driver 20 and one emission driver 30 that are arranged on both sides of the display opposite to one another).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the scan driver 30 of Okuno to the display apparatus of Kim because the scan driver 30 controls each of the plurality of pixels 100, [0051], lines 4-5).
As to claim 14, Kim teaches the display apparatus of claim 1,
Kim does not teach an emission control driver,
Okuno teaches the emission control driver (30) is disposed outside the scan driver (the emission driver 30 is outside of the scan driver 20 and located on the opposite side of the display).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the scan driver 30 of Okuno to the display apparatus of Kim because the scan driver 30 controls each of the plurality of pixels 100, [0051], lines 4-5).
As to claim 15, Kim teaches the gate driver (gate driver comprising of elements 200 and 300, Fig. 1) is connected to receive a gate control signal through a level shifter (the gate driver has a gate controller 300 that changes the level of the gate signals outputted by the scan driver 200, as can be seen in Fig. 3, the gate signals levels have been changes from Soi to the level signal of Si, thus gate controller 300 is a level shifter, and the gate controller 300 outputs the gate control signals to the pixels, [0052]).
As to claim 18, Kim teaches one frame of the display apparatus (Fig. 6 frame comprising of DP and BP) comprises an active period for display the image (DP period) and a blank period (BP period) except for the active period (BP period is after the active period, [0111], lines 1-3);
the display mode (DP period) operates in the active period ([0112], lines 1-4); and the sensing mode operates in the blank period (sensing signals are operating during the BP period, [0113], lines 1-5).
As to claim 19, Kim teaches the sensing unit (sensing unit comprising of transistor T3, read out line RL shown in Fig. 2 and compensator 500 shown in Fig. 1) is configured to sense pixel degradation through a sensing signal (the sensing unit senses a pixel degradation via sensing signal via read out lines, [0058], lines 1-7) output at a previously-set time (the sensing signals are repeated every P1-P4 period shown in Fig. 3 and therefore is considered as output at a previously set time once that period ends).
As to claim 20, Kim teaches a controller (timing controller 600) for counting a driving time of the display panel through accumulation of data ([0044], the timing controller generates a first driving control signal and drives all of the drivers such as 200, 300, 400, and 500, therefore the timing is checked and generated, for example for controller 300, the control signal VCS (generated by the timing controller) is used to output the sensing signals, therefore the timing controller controls the start and end of each period like P1, P2, P3, and etc. based on the timing controller signal, [0052] and [0053]), and outputting the sensing signal at the previously-set time (the sensing signals are repeated every P1-P4 period shown in Fig. 3 and therefore is considered as output at a previously set time once that period ends).
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. Pub. No. 2020/0152123) in view of Okuno (U.S. Pub. No. 2015/0154910), and further in view of Chun (U.S. Pub. No. 2024/0153459).
As to claim 16, Kim and Okuno teach the display apparatus,
Kim and Okuno do not teach wherein the sensing unit is disposed on a printed circuit board.
Chun teaches the sensing unit is disposed on a printed circuit board ([0135], lines 1-4).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the printed circuit board structure of Chun to the display apparatus of Kim as modified by Okuno because to connect the sensing driver to the display panel 100, [0135], lines 2-3.
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. Pub. No. 2020/0152123) in view of Okuno (U.S. Pub. No. 2015/0154910), and further in view of Jung (U.S. Pub. No. 2014/0176622).
As to claim 17, Kim and Okuno teach the display apparatus of claim 1,
Kim and Okuno do not teach a data driver integrated circuit.
Jung teaches the data driver (300, Fig. 3 and Fig. 5) comprises a plurality of driver-integrated circuits (302); and the sensing unit (320) is comprised in each of the plurality of driver-integrated circuits to sense the display panel on a block basis (each of the driver integrated circuits 300 shown in Fig. 5 are individually arranged and each comprises a sensing unit 320, [0074], lines 1-2 and [0085], lines 1-7).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the data driver and sensing unit structure of Jung to the display apparatus of Kim as modified by Okuno because the timing controller may correct the sensing data according to the input from the sensing unit 320, [0085], lines 1-12.
Allowable Subject Matter
Claims 21-28 are allowed.
Claims 2-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 21 is allowed because the prior art references do not teach the structure
Where a first capacitor connected between a first node and a second node;
a first transistor comprising a first electrode connected to a reference voltage line and a second electrode connected to the first node, the first transistor being configured to supply a reference voltage to the first node in response to an emission control signal of an n+1-th pixel row; a second transistor comprising a first electrode connected to the reference voltage line and a second electrode connected to the second node, the second transistor being configured to supply the reference voltage to the second node in response to a scan signal of an n−1-th pixel row; a driving transistor comprising a gate electrode connected to the second node, a first electrode configured to receive a high-level drive voltage and a second electrode connected to a third node; a third transistor comprising a first electrode connected to an initialization voltage line and a second electrode connected to a fourth node, the third transistor being configured to supply an initialization voltage to the fourth node in response to a scan signal of an n-th pixel row; and a fourth transistor comprising a first electrode connected to the initialization voltage line and a second electrode connected to the fourth node, the fourth transistor being configured to be turned on in response to a sensing signal.
Claim 25 is allowed because the prior art references do not teach the structure where supplying a reference voltage to a first node via the first transistor in response to an emission control signal of an n+1-th pixel row, the first transistor comprising a first electrode connected to a reference voltage line and a second electrode connected to the first node; supplying the reference voltage to a second node via the second transistor in response to a scan signal of an n−1-th pixel row, the second transistor comprising a first electrode connected to the reference voltage line and a second electrode connected to the second node; receiving a high-level drive voltage via the driving transistor, the driving transistor comprising a first electrode receiving the high-level drive voltage, and a second electrode connected to a third node, and a gate electrode connected to the second node; supplying an initialization voltage to a fourth node via the third transistor in response to a scan signal of an n-th pixel row, the third transistor comprising a first electrode connected to an initialization voltage line and a second electrode connected to the fourth node; and turning on the fourth transistor in response to a sensing signal, the fourth transistor comprising a first electrode connected to the initialization voltage line and a second electrode connected to the fourth node, wherein the first capacitor is connected between the first node and the second node.
Claim 2 is objected to because the prior art references do not teach the structure of the pixel specifically the underlined section of claim 2 when combined with other limitations of the structure wherein a light emitting element; a first capacitor connected between a first node and a second node; a first transistor comprising a first electrode connected to a reference voltage line and a second electrode connected to the first node, the first transistor being configured to supply a reference voltage to the first node in response to an emission control signal of an (n+1)th pixel row; a second transistor comprising a first electrode connected to the reference voltage line and a second electrode connected to the second node, the second transistor being configured to supply the reference voltage to the second node in response to a scan signal of an n−1-th pixel row; and a driving transistor comprising a gate electrode connected to the second node, a first electrode configured to receive a high-level drive voltage and a second electrode connected to a third node, wherein n is an integer greater than 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (U.S. Pub. No. 2023/0015213) teaches a pixel structure similar to the pixel structure shown in claims 2, 21, and 25. However, the structure does not read on all of the limitations of claims 2, 21, and 25.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGEMAN KARIMI whose telephone number is (571)270-1712. The examiner can normally be reached Monday-Friday; 9:00am-4:00pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 5712727772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PEGEMAN KARIMI/Primary Examiner, Art Unit 2623