DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 20 are presented for examination.
Information Disclosure Statement
The references listed in the information disclosure statement submitted on 5-6-2025 have been considered by the examiner (see attached PTO-1449).
Claim Objections
Claim 1 is objected to because of the following informalities: the phrase “with the of memory” recited in line 3 needs revising.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 to 2, 8, 10 to 11, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sheperek et al. (USPAP 2021/0191617) in view of Garcia Redondo et al. (USPAP 2022/0208265).
Claims 1, 10 and 16:
Sheperek substantially teaches the claimed invention. Sheperek teaches a computer system comprising a memory sub-system (110) that includes volatile and non-volatile memory devices (see par. 0027). Sheperek teaches that the memory subsystem is coupled to a host system and the host system can include a processor chip (see par. 0029 et seq.). Sheperek teaches that the memory sub-system comprises a memory sub-system controller (115) and memory devices (130 & 140) wherein each of the memory devices can include one or more arrays of memory cells that are grouped as pages and pages can be grouped as blocks (see par. 0034). Sheperek teaches that the memory sub-system controller can include a processor (117) configured to execute instructions stored in a local memory (119) (see par. 0037).
Sheperek teaches that the memory sub-system controller receives commands or operations from the host system and converts the operations into instructions to access the memory devices (see par. 0039). Sheperek teaches that the memory sub-system controller can be responsible for other operations such as wear leveling (“data retention”) (see par. 0039). Sheperek teaches that the memory subsystem includes a block family manager component (113) for implementing the block family-based error avoidance strategy (see par. 0043). Sheperek teaches that the block family manager component can manage block families associated with the memory devices (see par. 0043).
Sheperek teaches that the computer system tracks a temporal voltage shift caused by the slow charge loss for programmed blocks grouped by block families (see par. 0044). Sheperek teaches that the memory cell is programmed by applying a certain voltage that results in the electrical charge being stored in the memory cell thus establishing threshold voltage levels (see par. 0045). Sheperek teaches that the threshold voltage level is defined and any measured voltages falling below or above the threshold voltage level is associated with a distribution (see par. 0046). Sheperek teaches that an appropriate voltage offset that are based on block affiliation with certain block family are applied to the base on read levels in order to perform read operations (see par. 0047).
Sheperek fails to teach identifying a sacrificial block in a die of the plurality of dies of the memory device and responsive to performing a data retention test on the sacrificial block; however, Garcia Redondo in an analogous art teaches an apparatus and a method for predicting failure of a computer memory using on-chip memory cells, wherein a memory array of a memory device comprises a plurality of memory cells and a sacrificial memory cell used in a stress test to check for proper functionality of the memory cells (see par. 0058). Garcia Redondo teaches that a failure prediction circuitry includes sacrificial memory cells that are fabricated on the same die to be switchable between a first state and a second state and when the sacrificial cell fails to switch states, detection of failure of associated sacrificial memory cell is predictive of failure in at least one row of the memory array (see par. 0021).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the memory array of Sheperek to include the memory array of Garcia Redondo with a sacrificial memory cell used for predicting failures in the memory array because Garcia Redondo teaches that a method and an apparatus utilizes a sacrificial memory cell fabricated on the memory die to predict memory cells failures before the primary cells in the memory array fails. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method for using an on-chip sacrificial memory cell that is expected to fail in order to predict memory cell failures as taught by Garcia Redondo (see par. 0071).
As per claims 2, 8, 11 and 17, Sheperek teaches that the memory device grouped into block families (330a-330n) comprises one or more blocks having a specified temperature window and a block family manager (510) manages temperature values associated with the memory block (see par. 0048 and 0055 e5 seq.). Sheperek further teaches that the threshold voltage offset is measured against time after program i.e., the period of time elapsed since the block had been programmed (see par. 0048).
Sheperek fails to specifically teach a sacrificial block being exposed to a temperature above a threshold or comprise a first block, a middle block or a last block; however, Garcia Redondo teaches that sacrificial memory cells are fabricated such that they are expected to fail before cells in the primary memory array given the same amount of stress and variation of fabrication parameter values for the sacrificial memory cells are known to achieve desired operation points (see par. 0053 and 0071 et seq.). Garcia Redondo teaches that the sacrificial memory cells are exposed to temperature variations (see par. 0068).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify memory array of Sheperek to include the memory array of Garcia Redondo with a sacrificial memory cell used for predicting failures in the memory array because Garcia Redondo teaches that a method and an apparatus utilizes a sacrificial memory cell fabricated on the memory die to predict memory cells failures before the primary cells in the memory array fails. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method for using an on-chip sacrificial memory cell that is expected to fail in order to predict memory cell failures as taught by Garcia Redondo (see par. 0071).
Allowable Subject Matter
Claims 3 to 7, 9, 12 to 15 and 18 to 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Darragh et al. (USPAP 2017/0221573) discloses a memory system for measuring/predicts memory wear/endurance.
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/Shelly A Chase/Primary Examiner, Art Unit 2112