DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claims because the examined application claim is either anticipated by, or would have been obvious over, the reference claims.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-22 of U.S. Patent #11,500,791. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed invention simply claims a broader scope from the ‘791 patent.
For example,
‘215 Application
‘791 Patent
(Claim 1) a memory system, comprising:
(Claim 1) an apparatus, comprising:
circuitry coupled with a pin and to bias the pin to a first voltage in response to receiving an access command,
a first memory device comprising a first driver;
a second memory device comprising a second driver; and
the first voltage corresponding to a threshold voltage associated with the circuitry; and
a pin coupled with the first driver and the second driver, and to receive a chip enable signal for the first memory device and the second memory device,
a memory device coupled with the pin, wherein a first memory device of the memory device is to:
wherein the first driver is to:
bias the pin to a first voltage indicating that the first memory device is able to be accessed and a second voltage indicating that the first memory device is unable to be accessed;
bias the pin to a second voltage that is different from the first voltage based on the first memory device executing the access command; and
bias the pin to the first voltage based on a first status of the first memory device, the first status indicating that the first memory device is busy; and
release, by the first memory device, a first voltage source from the pin based on the first memory device finishing executing the access command.
bias the pin to the second voltage based on a second status of the first memory device, the second status indicating that the first memory device is available to receive a command.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent #12,169,461. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed invention simply claims a broader scope from the ‘791 patent.
For example,
‘215 Application
‘461 Patent
(Claim 1) a memory system, comprising:
(Claim 1) a memory system, comprising:
circuitry coupled with a pin and to bias the pin to a first voltage in response to receiving an access command,
a memory device comprising a driver;
the first voltage corresponding to a threshold voltage associated with the circuitry; and
a pin coupled with the memory device and to receive a chip enable signal for the memory device; and
a memory device coupled with the pin, wherein a first memory device of the memory device is to:
a controller coupled with the memory device and the pin,
wherein the controllers are to cause the memory system to:
bias the pin to a second voltage that is different from the first voltage based on the first memory device executing the access command; and
bias the pin to a first voltage, the first voltage corresponding to a first status of the memory device, the first status indicating that the memory device is accessible;
release, by the first memory device, a first voltage source from the pin based on the first memory device finishing executing the access command.
bias the pin to a second voltage, the second voltage corresponding to a second status of the memory device, the second status indicating that the memory device are inaccessible; and
determine the first status, the second status, or both of the memory device based on comparing the first voltage and the second voltage to a set of voltages associated with statuses of the memory devices.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o).
In claims 1, 8-9 and 16-17, the claim term “a first voltage source” and “the first voltage source” has no antecedent basis to specification.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “circuitry 205 coupled with a pin 215 to bias the pin to a first voltage in response to receiving an access command” must be shown or the features canceled from the claim(s).
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
“circuitry … configured to bias …” in claims 1 and 8,
“a first memory device … configured to: …” in claims 1 and 7,
“a received configured to …” in claims 4-6, and
“processor to …” in claims 17-20.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
In independent claim 1, the claim requires “circuitry 205 coupled with a pin 215 to bias the pin to a first voltage in response to receiving an access command”. The claim clearly requires the circuitry to receive an access command to bias a pin to a voltage. There is insufficient support for such a claim feature. The circuitry 205 does not appear to detect or initialize the pin to any voltage as a result of receiving any command.
For example, the circuit 205 may drive the pin 215 to low for enabling memory device 310 to receive access commands as described in para.0051.
For example, in fig. 3, step 335, it is the memory device 310 sets the pin 215 to a first voltage.
Independent claims 9 and 17 have the same issues; therefore, they are rejected for the same reason as above.
Dependent claims are rejected for the same reason as above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Woo (US 2008/0,052,639).
Referring to claims 1, 9 and 17, Woo discloses a memory system (fig. 1, system 100A), comprising:
circuitry (fig. 1, controller 120A) coupled with a pin (fig. 1, CE0 at memory controller 120A) and to bias the pin to a first voltage (fig. 2, CE0 voltage low during CMD) in response to receiving an access command (fig. 2, CMD during CE0 low),
the first voltage corresponding to a threshold voltage (fig. 2, voltage, e.g., low) associated with the circuitry; and
a memory device (fig. 1, NVM 110A-0/110A-7) coupled with the pin, wherein a first memory device (fig. 1, NVM 110-0) of the memory device is to:
bias the pin to a second voltage (fig. 1, CE0 voltage high) that is different from the first voltage based on the first memory device executing the access command (fig. 2, CE0 low during CMD, CE0 high after CMD); and
release, by the first memory device, a first voltage source (fig. 6, apparatus for outputting state signal 20) from the pin based on the first memory device finishing executing the access command (fig. 9, CMD).
As to claims 2-3 and 10-11, Woo discloses the system of claim 1, wherein the pin comprises an active high/low pin (fig. 2, CE0 output busy/output ready), and wherein the second voltage is greater/less than the first voltage (fig. 2, CE0 high during output, low during CMD).
As to claims 4, 12 and 18, Woo discloses the system of claim 1, wherein the circuit comprises a receiver (fig. 6, apparatus 20A) to determine a status (fig. 9, state signal 21A) of the first memory device based on a voltage (fig. 2, CE0) of the pin.
As to claims 5, 13 and 19, Woo discloses the system of claim 4, wherein, to determine the status of the first memory device, the receiver is to: determine that the first memory device is busy (fig. 2, output busy state) based on the pin being biased to the second voltage.
As to claims 6 and 14, Woo discloses the system of claim 4, wherein, to determine the status of the first memory device, the first memory device is available (fig. 2, output ready) to be accessed based on the pin being biased to the first voltage.
As to claims 7, 15 and 20, Woo discloses the system of claim 1, wherein the first memory device is to: bias the pin to a third voltage (fig. 2, CE0 low during CMD with way1-RnB), the third voltage indicating whether the first memory device has successfully finished executing the access command (fig. 2, CE1 for NVM 110A-1).
As to claims 8 and 16, Woo discloses the system of claim 1, wherein the circuitry is to: bias the pin to the first voltage based on the pin being released from the first voltage source (fig. 2, CE0 low during CMD with way1-RnB).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See M.P.E.P 707.05(c).
US2014/0,325,148 discloses storage device supplying data processing information to host in responsive to data access command.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
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