DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/21/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 – 3, 5 – 9, 11 – 16, 18 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno US Patent Application Publication No. 2022/0237114 (originally cited in IDS filed 6/19/2025, herein after referred to as Kanno) in view of Lee et al. US Patent Application Publication No. 2023/0205427 (herein after referred to as Lee).
Regarding claim 1, Kanno describes non-transitory computer readable media having instructions stored thereon, that when executed by at least one processor, cause the at least one processor to (Embodiments described herein relate generally to a memory system and a non-transitory computer readable recording medium (page 1, paragraph [0002]). The processor 11 includes a memory 12… The program 17 is, for example, a firmware. The processor 11 executes the program 17… (page 2, paragraphs [0030] – [0032])): identify, from incoming data, a plurality of namespace identifiers (IDs) corresponding to a plurality of namespaces (…the information processing device 2 sends a write command C2 together with namespace identification data (NSID) 6, LBA 7 which indicates a writing destination, data size 8 of the write data, and write data 9 to the memory system 3 (page 2, paragraph [0024]). In the present embodiment, a plurality of namespaces NS0 to NSM (M is an integer which is 1 or more) are each space which can be obtained from dividing a plurality of blocks B0 to BN (N is an integer which is M or more) included in the nonvolatile memory 5… (page 2, paragraph [0025]). When the reception unit 13 receives the write command C2, the address translation unit 15 executes associating to translate the LBA 7 with the write command C2 into the PBA for the address translation table T0 corresponding to the namespace NS0 which indicates the NSID 6 with the write command C2 (page 3, paragraph [0041])); segregate the incoming data according to the plurality of namespace IDs (In the present embodiment, the write unit 16 stores the write data 9 in the buffer memory F0 corresponding to the namespace NS0 indicated by the NSID 6 with the write command C2… (page 3, paragraph [0044]). The data is clearly being segregated into a memory buffer based on the identified namespace); and write the segregated incoming data to respective ones of a plurality of wordlines of a memory device (Then the write unit 16 writes the data of the buffer F0 to a position indicated by the PBA when the buffer memory F0 reaches a data amount suitable for the namespace NS0 (page 3, paragraph [0044]). The plurality of blocks include a plurality of memory cells arranged at crossing points of word lines and bit lines… (page 1, paragraph [0020])). While Kanno discloses the operation of an erase operation in the nonvolatile memory (page 1, paragraph [0020]), it does not specifically describe receive a namespace format command for a first namespace of the plurality of namespaces, said namespace format command including a user data erase request for the first namespace; identify a first wordline of the plurality of wordlines associated with the first namespace; and responsive to receiving the namespace format command, issue a single state program command to erase the first wordline by programming memory cells comprising the first wordline to a same state.
Lee describes performing management operations on a storage device. Specifically, Lee discloses that the storage device 20 may support a namespace function. Here, the “namespace” may be defined as a quantity of the memory devices 200 that may be formatted into logical blocks, and the namespace of size n is a collection of logical blocks having logical block addresses (LBA) from 0 to (n-1) (page 2, paragraph [0027]). The namespace manager 185 may dynamically generate or erase namespaces as shown in Fig. 9 in response to namespace generation requests or namespace erase requests received from the first to third hosts 31 to 33 (page 7, paragraph [0088]). In a NAND flash memory device having the structure as shown in Fig. 4, erasing may be performed block-by-block, and programming may be performed page-by-page, where pages correspond to word lines WL0 – WLn-1, respectively (page 4, paragraph [0049]). Accordingly, Lee presents that a namespace is comprised of blocks and those blocks are shown to be comprised of pages (see Fig. 6A), which Lee further describes correspond to word lines. Receiving a namespace erase request would identify all of the blocks->pages->word lines associated with that namespace as well as programming all of the word lines that are part of the identified namespace to an erased state.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Lee teachings in the Kanno system. Skilled artisan would have been motivated to incorporate the method of a namespace based erase operation as taught by Lee in the Kanno system for effectively executing an erase operation based on namespace identification. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as nonvolatile memory management. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 2, Kanno in view of Lee describe the non-transitory computer readable media of claim 1 (see above), the single state program command being issued for remaining ones of the plurality of wordlines (In the nonvolatile memory 5, data are erased at once block by block. That is, a block is an area of a unit of data erase. Data write and data read are performed page by page (word line by word line) in each block. That is, a page is an area of a unit of data write or an area of a unit of data read (Kanno, page 1, paragraph [0020]). The namespace manager 185 may dynamically generate or erase namespaces as shown in Fig. 9 in response to namespace generation requests or namespace erase requests received from the first to third hosts 31 to 33 (Lee, page 7, paragraph [0088]). In a NAND flash memory device having the structure as shown in Fig. 4, erasing may be performed block-by-block, and programming may be performed page-by-page, where pages correspond to word lines WL0 – WLn-1, respectively (Lee, page 4, paragraph [0049]). The namespace erase request of Lee would erase all of the corresponding word lines associated with the namespace).
Regarding claim 3, Kanno in view of Lee describe the non-transitory computer readable media of claim 2 (see above), wherein the same state is a highest state of a plurality of states (Kanno describes how data in NAND flash memory is erased (Kanno, page 1, paragraph [0020]). …voltage generator 360 may provide a high-level erase voltage to the bulk in which a selected memory cell array is formed during an erase operation (Lee, page 3, paragraph [0044])).
Regarding claim 5, Kanno in view of Lee describe the non-transitory computer readable media of claim 1 (see above), wherein the same state is a highest state of a plurality of states (Lee, page 3, paragraph [0044]).
Regarding claim 6, Kanno in view of Lee describe the non-transitory computer readable media of claim 1 (see above), said plurality of wordlines being organized into a plurality of virtual blocks (the namespace manager 185 may dynamically generate or erase namespaces as shown in Fig. 9 in response to namespace generation requests or namespace erase requests received from the first to third hosts 31 to 33 (Lee, page 7, paragraph [0088])), wherein the instructions, when executed by the at least one processor, cause the at least one processor to: maintain respective valid data frame (VDF) counts for each of the plurality of namespaces for respective ones of the plurality of virtual blocks (The management operation on the first storage region may be performed based on an erase count of the first storage region, a read count of the first storage region, the number of valid pages included in the first storage region, or correctability of the data read from the first storage region (Lee, page 3, paragraph [0037]). The memory controller 100 may control a garbage collection operation on the first storage region based on the number of valid pages included in the first storage region (Lee, page 7, paragraph [0093]). In order for operations to be based on the “number of valid pages” that number must be tracked and updated in order to operate as disclosed); and responsive to receiving the namespace format command, set the VDF count for the first namespace to zero (0) for one or more of the respective ones of the plurality of virtual blocks (The management operation on the first storage region may be performed based on an erase count of the first storage region, a read count of the first storage region, the number of valid pages included in the first storage region, or correctability of the data read from the first storage region (Lee, page 3, paragraph [0037]). The memory controller 100 may control a garbage collection operation on the first storage region based on the number of valid pages included in the first storage region (Lee, page 7, paragraph [0093]). In order for operations to be based on the “number of valid pages” that number must be tracked and updated in order to operate as disclosed).
Regarding claim 7, Kanno describes a data storage system comprising: a memory device including a plurality of wordlines (The plurality of blocks include a plurality of memory cells arranged at crossing points of word lines and bit lines… (page 1, paragraph [0020])); and a controller including at least one processor and a memory, said memory including instructions stored thereon, that when executed by the at least one processor, cause the at least one processor to (Embodiments described herein relate generally to a memory system and a non-transitory computer readable recording medium (page 1, paragraph [0002]). The processor 11 includes a memory 12… The program 17 is, for example, a firmware. The processor 11 executes the program 17… (page 2, paragraphs [0030] – [0032])): identify, from incoming data, a plurality of namespace identifiers (IDs) corresponding to a plurality of namespaces (…the information processing device 2 sends a write command C2 together with namespace identification data (NSID) 6, LBA 7 which indicates a writing destination, data size 8 of the write data, and write data 9 to the memory system 3 (page 2, paragraph [0024]). In the present embodiment, a plurality of namespaces NS0 to NSM (M is an integer which is 1 or more) are each space which can be obtained from dividing a plurality of blocks B0 to BN (N is an integer which is M or more) included in the nonvolatile memory 5… (page 2, paragraph [0025]). When the reception unit 13 receives the write command C2, the address translation unit 15 executes associating to translate the LBA 7 with the write command C2 into the PBA for the address translation table T0 corresponding to the namespace NS0 which indicates the NSID 6 with the write command C2 (page 3, paragraph [0041])); segregate the incoming data according to the plurality of namespace IDs (In the present embodiment, the write unit 16 stores the write data 9 in the buffer memory F0 corresponding to the namespace NS0 indicated by the NSID 6 with the write command C2… (page 3, paragraph [0044]). The data is clearly being segregated into a memory buffer based on the identified namespace); and write the segregated incoming data to respective ones of the plurality of wordlines (Then the write unit 16 writes the data of the buffer F0 to a position indicated by the PBA when the buffer memory F0 reaches a data amount suitable for the namespace NS0 (page 3, paragraph [0044]). The plurality of blocks include a plurality of memory cells arranged at crossing points of word lines and bit lines… (page 1, paragraph [0020])). While Kanno discloses the operation of an erase operation in the nonvolatile memory (page 1, paragraph [0020]), it does not specifically describe receive a namespace format command for a first namespace of the plurality of namespaces, said namespace format command including a user data erase request for the first namespace; identify a first wordline of the plurality of wordlines associated with the first namespace; and responsive to receiving the namespace format command, issue a single state program command to erase the first wordline by programming memory cells comprising the first wordline to a same state.
Lee describes performing management operations on a storage device. Specifically, Lee discloses that the storage device 20 may support a namespace function. Here, the “namespace” may be defined as a quantity of the memory devices 200 that may be formatted into logical blocks, and the namespace of size n is a collection of logical blocks having logical block addresses (LBA) from 0 to (n-1) (page 2, paragraph [0027]). The namespace manager 185 may dynamically generate or erase namespaces as shown in Fig. 9 in response to namespace generation requests or namespace erase requests received from the first to third hosts 31 to 33 (page 7, paragraph [0088]). In a NAND flash memory device having the structure as shown in Fig. 4, erasing may be performed block-by-block, and programming may be performed page-by-page, where pages correspond to word lines WL0 – WLn-1, respectively (page 4, paragraph [0049]). Accordingly, Lee presents that a namespace is comprised of blocks and those blocks are shown to be comprised of pages (see Fig. 6A), which Lee further describes correspond to word lines. Receiving a namespace erase request would identify all of the blocks->pages->word lines associated with that namespace as well as programming all of the word lines that are part of the identified namespace to an erased state.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Lee teachings in the Kanno system. Skilled artisan would have been motivated to incorporate the method of a namespace based erase operation as taught by Lee in the Kanno system for effectively executing an erase operation based on namespace identification. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as nonvolatile memory management. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 8, Kanno in view of Lee describe the data storage system of claim 7 (see above), the single state program command being issued for remaining ones of the plurality of wordlines (In the nonvolatile memory 5, data are erased at once block by block. That is, a block is an area of a unit of data erase. Data write and data read are performed page by page (word line by word line) in each block. That is, a page is an area of a unit of data write or an area of a unit of data read (Kanno, page 1, paragraph [0020]). The namespace manager 185 may dynamically generate or erase namespaces as shown in Fig. 9 in response to namespace generation requests or namespace erase requests received from the first to third hosts 31 to 33 (Lee, page 7, paragraph [0088]). In a NAND flash memory device having the structure as shown in Fig. 4, erasing may be performed block-by-block, and programming may be performed page-by-page, where pages correspond to word lines WL0 – WLn-1, respectively (Lee, page 4, paragraph [0049]). The namespace erase request of Lee would erase all of the corresponding word lines associated with the namespace).
Regarding claim 9, Kanno in view of Lee describe the data storage system of claim 8 (see above), wherein the same state is a highest state of a plurality of states (Kanno describes how data in NAND flash memory is erased (Kanno, page 1, paragraph [0020]). …voltage generator 360 may provide a high-level erase voltage to the bulk in which a selected memory cell array is formed during an erase operation (Lee, page 3, paragraph [0044])).
Regarding claim 11, Kanno in view of Lee describe the data storage system of claim 7 (see above), wherein the same state is a highest state of a plurality of states (Lee, page 3, paragraph [0044]).
Regarding claim 12, Kanno in view of Lee describe the data storage system of claim 7 (see above), said plurality of wordlines being organized into a plurality of virtual blocks (the namespace manager 185 may dynamically generate or erase namespaces as shown in Fig. 9 in response to namespace generation requests or namespace erase requests received from the first to third hosts 31 to 33 (Lee, page 7, paragraph [0088])), wherein the instructions, when executed by the at least one processor, cause the at least one processor to: maintain respective valid data frame (VDF) counts for each of the plurality of namespaces for respective ones of the plurality of virtual blocks (The management operation on the first storage region may be performed based on an erase count of the first storage region, a read count of the first storage region, the number of valid pages included in the first storage region, or correctability of the data read from the first storage region (Lee, page 3, paragraph [0037]). The memory controller 100 may control a garbage collection operation on the first storage region based on the number of valid pages included in the first storage region (Lee, page 7, paragraph [0093]). In order for operations to be based on the “number of valid pages” that number must be tracked and updated in order to operate as disclosed).
Regarding claim 13, Kanno in view of Lee describe the data storage system of claim 12 (see above), wherein the instructions, when executed by the at least one processor, cause the at least one processor to: in response to receiving the namespace format command, set the VDF count for the first namespace to zero (0) for one or more of the respective ones of the plurality of virtual blocks (Lee, page 7, paragraph [0088]. Lee, page 4, paragraph [0049]. Lee, page 3, paragraph [0037]. Lee, page 7, paragraph [0093]. In order for operations to be based on the “number of valid pages” that number must be tracked and updated in order to operate as disclosed).
Regarding claim 14, Kanno describes a computer-implemented method, comprising: identifying, from incoming data, a plurality of namespace identifiers (IDs) corresponding to a plurality of namespaces (…the information processing device 2 sends a write command C2 together with namespace identification data (NSID) 6, LBA 7 which indicates a writing destination, data size 8 of the write data, and write data 9 to the memory system 3 (page 2, paragraph [0024]). In the present embodiment, a plurality of namespaces NS0 to NSM (M is an integer which is 1 or more) are each space which can be obtained from dividing a plurality of blocks B0 to BN (N is an integer which is M or more) included in the nonvolatile memory 5… (page 2, paragraph [0025]). When the reception unit 13 receives the write command C2, the address translation unit 15 executes associating to translate the LBA 7 with the write command C2 into the PBA for the address translation table T0 corresponding to the namespace NS0 which indicates the NSID 6 with the write command C2 (page 3, paragraph [0041])); segregating the incoming data according to the plurality of namespace IDs (In the present embodiment, the write unit 16 stores the write data 9 in the buffer memory F0 corresponding to the namespace NS0 indicated by the NSID 6 with the write command C2… (page 3, paragraph [0044]). The data is clearly being segregated into a memory buffer based on the identified namespace); and writing the segregated incoming data to respective ones of a plurality of wordlines of a memory device (Then the write unit 16 writes the data of the buffer F0 to a position indicated by the PBA when the buffer memory F0 reaches a data amount suitable for the namespace NS0 (page 3, paragraph [0044]). The plurality of blocks include a plurality of memory cells arranged at crossing points of word lines and bit lines… (page 1, paragraph [0020])). While Kanno discloses the operation of an erase operation in the nonvolatile memory (page 1, paragraph [0020]), it does not specifically describe receiving a data erase request associated with a first namespace of the plurality of namespaces; identifying a first wordline of the plurality of wordlines associated with the first namespace; and issuing a single state program command to erase the first wordline by programming memory cells comprising the first wordline to a same state.
Lee describes performing management operations on a storage device. Specifically, Lee discloses that the storage device 20 may support a namespace function. Here, the “namespace” may be defined as a quantity of the memory devices 200 that may be formatted into logical blocks, and the namespace of size n is a collection of logical blocks having logical block addresses (LBA) from 0 to (n-1) (page 2, paragraph [0027]). The namespace manager 185 may dynamically generate or erase namespaces as shown in Fig. 9 in response to namespace generation requests or namespace erase requests received from the first to third hosts 31 to 33 (page 7, paragraph [0088]). In a NAND flash memory device having the structure as shown in Fig. 4, erasing may be performed block-by-block, and programming may be performed page-by-page, where pages correspond to word lines WL0 – WLn-1, respectively (page 4, paragraph [0049]). Accordingly, Lee presents that a namespace is comprised of blocks and those blocks are shown to be comprised of pages (see Fig. 6A), which Lee further describes correspond to word lines. Receiving a namespace erase request would identify all of the blocks->pages->word lines associated with that namespace as well as programming all of the word lines that are part of the identified namespace to an erased state.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Lee teachings in the Kanno system. Skilled artisan would have been motivated to incorporate the method of a namespace based erase operation as taught by Lee in the Kanno system for effectively executing an erase operation based on namespace identification. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as nonvolatile memory management. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 15, Kanno in view of Lee describe the computer-implemented method of claim 14 (see above), the single state program command being issued for remaining ones of the plurality of wordlines (In the nonvolatile memory 5, data are erased at once block by block. That is, a block is an area of a unit of data erase. Data write and data read are performed page by page (word line by word line) in each block. That is, a page is an area of a unit of data write or an area of a unit of data read (Kanno, page 1, paragraph [0020]). The namespace manager 185 may dynamically generate or erase namespaces as shown in Fig. 9 in response to namespace generation requests or namespace erase requests received from the first to third hosts 31 to 33 (Lee, page 7, paragraph [0088]). In a NAND flash memory device having the structure as shown in Fig. 4, erasing may be performed block-by-block, and programming may be performed page-by-page, where pages correspond to word lines WL0 – WLn-1, respectively (Lee, page 4, paragraph [0049]). The namespace erase request of Lee would erase all of the corresponding word lines associated with the namespace).
Regarding claim 16, Kanno in view of Lee describe the computer-implemented method of claim 15 (see above), wherein the same state is a highest state of a plurality of states (Kanno describes how data in NAND flash memory is erased (Kanno, page 1, paragraph [0020]). …voltage generator 360 may provide a high-level erase voltage to the bulk in which a selected memory cell array is formed during an erase operation (Lee, page 3, paragraph [0044])).
Regarding claim 18, Kanno in view of Lee describe the computer-implemented method of claim 14 (see above), wherein the same state is a highest state of a plurality of states (Lee, page 3, paragraph [0044]).
Regarding claim 19, Kanno in view of Lee describe the computer-implemented method of claim 14 (see above), said plurality of wordlines being organized into a plurality of virtual blocks (the namespace manager 185 may dynamically generate or erase namespaces as shown in Fig. 9 in response to namespace generation requests or namespace erase requests received from the first to third hosts 31 to 33 (Lee, page 7, paragraph [0088])), the method comprising: maintaining respective valid data frame (VDF) counts for each of the plurality of namespaces for respective ones of the plurality of virtual blocks (The management operation on the first storage region may be performed based on an erase count of the first storage region, a read count of the first storage region, the number of valid pages included in the first storage region, or correctability of the data read from the first storage region (Lee, page 3, paragraph [0037]). The memory controller 100 may control a garbage collection operation on the first storage region based on the number of valid pages included in the first storage region (Lee, page 7, paragraph [0093]). In order for operations to be based on the “number of valid pages” that number must be tracked and updated in order to operate as disclosed).
Regarding claim 20, Kanno in view of Lee describe the computer-implemented method of claim 19 (see above), the user data erase request being included in a namespace format command, comprising: receiving a namespace format command for a first namespace of the plurality of namespaces, said namespace format command including a user data erase request for the first namespace; issuing a namespace format command for a first namespace of the plurality of namespaces; and responsive to receiving the namespace format command, setting the VDF count for the first namespace to zero (0) for one or more of the respective ones of the plurality of virtual blocks (Lee, page 7, paragraph [0088]. Lee, page 4, paragraph [0049]. Lee, page 3, paragraph [0037]. Lee, page 7, paragraph [0093]. In order for operations to be based on the “number of valid pages” that number must be tracked and updated in order to operate as disclosed).
Claims 21 – 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno in view of Lee, further in view of Choi et al. US Patent Application Publication No. 2025/0054554 (herein after referred to as Choi).
Regarding claim 21, Kanno in view of Lee describe the non-transitory computer readable media of claim 1 (see above). They do not specifically disclose wherein programming the memory cells of the first wordline to the same state increases a threshold voltage of respective ones of the memory cells of the first wordline.
Choi describes a memory device. Specifically, in an embodiment, the memory cells on which the program operation is performed may have a threshold voltage corresponding to any one program state, among the erase state E and the first to seventh program states PV1 to PV7. The threshold voltage of the memory cells in the initial state may increase to a threshold voltage corresponding to any one program state, among the erase state E and the first to seventh program states PV1 to PV7, through the program operation (page 4, paragraph [0059]). Choi therefore discloses an operation in which the initial state may increase the threshold voltage to an erase state E.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Choi teachings in the Kanno in view of Lee system. Skilled artisan would have been motivated to incorporate the method of an erase operation involving increasing the threshold voltage of an initial state to an erase state as taught by Choi in the Kanno in view of Lee system for effectively executing an erase operation. Choi is believed to suggest variation on an erase operation that would be reasonably expected to succeed. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as nonvolatile memory management. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 22, Kanno in view of Lee describe the data storage system of claim 7 (see above). They do not explicitly disclose wherein programming the memory cells of the first wordline to the same state increases a threshold voltage of respective ones of the memory cells of the first wordline.
Choi describes a memory device. Specifically, in an embodiment, the memory cells on which the program operation is performed may have a threshold voltage corresponding to any one program state, among the erase state E and the first to seventh program states PV1 to PV7. The threshold voltage of the memory cells in the initial state may increase to a threshold voltage corresponding to any one program state, among the erase state E and the first to seventh program states PV1 to PV7, through the program operation (page 4, paragraph [0059]). Choi therefore discloses an operation in which the initial state may increase the threshold voltage to an erase state E.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Choi teachings in the Kanno in view of Lee system. Skilled artisan would have been motivated to incorporate the method of an erase operation involving increasing the threshold voltage of an initial state to an erase state as taught by Choi in the Kanno in view of Lee system for effectively executing an erase operation. Choi is believed to suggest variation on an erase operation that would be reasonably expected to succeed. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as nonvolatile memory management. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 23, Kanno in view of Lee describe the computer-implemented method of claim 14 (see above). They do not explicitly disclose wherein programming the memory cells of the first wordline to the same state increases a threshold voltage of respective ones of the memory cells of the first wordline.
Choi describes a memory device. Specifically, in an embodiment, the memory cells on which the program operation is performed may have a threshold voltage corresponding to any one program state, among the erase state E and the first to seventh program states PV1 to PV7. The threshold voltage of the memory cells in the initial state may increase to a threshold voltage corresponding to any one program state, among the erase state E and the first to seventh program states PV1 to PV7, through the program operation (page 4, paragraph [0059]). Choi therefore discloses an operation in which the initial state may increase the threshold voltage to an erase state E.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Choi teachings in the Kanno in view of Lee system. Skilled artisan would have been motivated to incorporate the method of an erase operation involving increasing the threshold voltage of an initial state to an erase state as taught by Choi in the Kanno in view of Lee system for effectively executing an erase operation. Choi is believed to suggest variation on an erase operation that would be reasonably expected to succeed. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as nonvolatile memory management. This close relation between both of the references highly suggests an expectation of success.
Response to Arguments
Applicant argues, with respect to the independent claims 1, 7, and 14, that the prior art of record do not teach or suggest the amended limitations. Specifically, that the “single state program command” and “by programming memory cells comprising the first wordline to a same state” is not taught or suggested by Kanno or Lee. Applicant relies on examples from their own originally filed specification, the amended claim language, as well as arguing that Kanno and Lee describe conventional block erasing. Examiner responds that firstly, the claims are not limited by examples presented in the specification. While Examiner acknowledges the further attempt to distinguish the invention, it is not believed to be specific enough to use “programming” in the claim. Applicant should further explain how this inventive wordline erase is accomplished in the claims to distinguish it from the prior art. Secondly, Examiner notes that, as explained in the rejection above, Lee discloses a namespace erase as well as pages being having corresponding wordlines. Applicant argues that the prior art doesn’t suggest wordline-level granularity. While the erasing may be conventional, it will erase the wordline present in the namespace identified by the erase operation. Examiner suggests that more explicit language is required to distinguish the inventive operation from the prior art if the invention intends to claim wordline-level granularity erasure operations, potentially that only the selected wordline is erased while other wordlines in the same erase block are not.
Applicant argues, with respect to the remaining claims, that they depend from the claims argued above and are therefore allowable for the same reasons. Examiner refers to rejections and responses above as to why these claims are not currently allowable.
Conclusion
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/RALPH A VERDERAMO III/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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September 30, 2026
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