Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cayton et al., (2018/0188974, hereafter Cayton) and Chou et al. (US 2005/0251609) and in further view of Yoshida et al., (US 2017/0262380), all currently sited in the IDS on 12/03/2024.
As per claims 1 and 11, Cayton teaches a device (300(1), Fig. 1) comprising: a connector (first interface configured to connect the storage device controller to the storage device, 110(n+1) to 110 (n+m), Fig. 1) configured to receive signal (Cayton is configured to operate in a first or second mode based on a status signal wherein Cayton teaches the use of different fabric protocols to communicate on different fabric networks [0021,0050-0055], further the system could be in a chassis – claim 19);
first circuitry (part of different fabric protocols to communicate on different fabric networks), wherein based on the signal, data is selected to configure the first circuitry to operate according to a communication protocol ([0021, 0050, 0055]); and
second circuitry coupled to the connector and the first circuitry, wherein based on the signal, a portion (Cayton is configured to operate in a first or second mode based on a status signal wherein Cayton teaches the use of different fabric protocols to communicate on different fabric networks [0021,0050-0055], further including the system method), of the
Cayton teaches that the storage devices could be one of a new form factor 1 (NFI) solid state drive (25D), an Ethernet SSD (eSSD), or an embedded SSD ([0021]) and “the computing device is a field programmable gate array (FPGA); or an application specific integrated circuit (ASIC) ([0079]), the first interlace is a PCIe interlace or a L2 connector (where the hast communicates over a PCle bus or port; Paragraphs 0021, 0023, and GG8G)."
In another analogous art, Chou el al discloses a host configured to receiving a signal (multi-mode device system 600, through an ExpressCard plug, is capable of PCle and USB (FIG. 6A) The host system may send an enable PCI Express Mode command to ascertain presence of the PCl Express mode ([0077]; FIG. 14). Note that this occurs after determining the presence of a first mode (e.g. USB) (step 1430 in FIG. 14) that for hot plug functionality (particularly with PCI) a PCI RST# signal can be asserted or deasserted; [0065])”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Cayton with the teachings of Chou for the flexibility in system configurations (Chou [0013]).
Cayton with Chou does not expressly disclose does not expressly teach a first or second portion of the second circuity is selected from a PCI endpoint that adheres to the communication protocol.
Nonetheless, Yoshida discloses a switch module (Figs. 1, 2 PCIe switch, 12) wherein a first port portion and a second port portion (part of a plurality of physical devices, 13-0-13-3, Fig. 1, [0038-0042]) can adaptively operate with PCIe or NVMe standard ([0029-0033]) when connected to a host/server (Fig. 1, 11). The switch modules includes a rear storage interface (via ports 15-0 – 15-3, Fig. 2) and a front storage interface connector (via first port, 14, Fig. 2, [0033]) Therein, in the first state, to present a device side storage interface according to a first storage protocol (PCIe standard) at the front storage interface connector (first/second portion of the circuitry), and in the second state, to present a device side storage interface according to a second storage protocol (NVMe standard), different from the first storage protocol, at the front storage interface connector (the other first/second portion of the circuitry),. (Yoshida, [0029-0042, 0070-0077])
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Cayton-Chou with the teachings of Yoshida for the flexibility in system configurations. Specifically, it would have been obvious to one of ordinary skill at the time the invention was made to incorporate the teachings of NVMe over Fabric overview the teachings of Yoshida for the purpose of providing a type of adaptive interface whereby when the switch is in one state a device storage interface is present in a first protocol and when the switch is in another state a device storage interface is presented in a second protocol. Using NVMe would improve the efficiency of the transmission functionality and further reduce latency to accommodate a system needs. ( NVMe over Fabric overview, pgs. 1-7)
As per claim 2 and 12, Crayton teaches wherein the connector includes a connector for a solid state drive. (Crayton teaches that the storage devices could be one of a new form factor 1 (NFI) solid stale drive (25D), an Ethernet SSD (eSSD), or an embedded SSD ([0021])
As per claim 3 and 13, Crayton teaches wherein the first circuitry includes a field programmable gate array. ( Crayton teaches “the computing device is a field programmable gate array (FPGA), [0021, 0023])
As per claim 4 and 14, Crayton teaches wherein the communication protocol is for receiving storage commands over a data communications bus. (Crayton teaches the first interlace is a PCIe interlace or a L2 connector (where the hast communicates over a PCle bus or port; Paragraphs [0021, 0023], and GG8G)
As per claim 5 and 15, Cayton-Chou with Yoshida wherein the second circuitry includes routing or switching circuitry. Yoshida discloses a switch module (Figs. 1, 2 PCIe switch, 12) wherein a first port portion and a second port portion (part of a plurality of physical devices, 13-0-13-3, Fig. 1, [0038-0042]) can adaptively operate with PCIe or NVMe standard ([0029-0033]) when connected to a host/server (Fig. 1, 11).
As per claim 6 and 16, Cayton-Chou with Yoshida teaches wherein the first portion of the second circuitry includes one or more first interfaces of the routing or switching circuitry, and the second portion of the second circuitry includes one or more second interfaces of the routing or switching circuitry. Yoshida discloses a switch module (Figs. 1, 2 PCIe switch, 12) wherein a first port portion and a second port portion (part of a plurality of physical devices, 13-0-13-3, Fig. 1, [0038-0042]) can adaptively operate with PCIe or NVMe standard ([0029-0033]) when connected to a host/server (Fig. 1, 11). The switch modules includes a rear storage interface (via ports 15-0 – 15-3, Fig. 2) and a front storage interface connector (via first port, 14, Fig. 2, [0033]).
As per claim 7 and 17, Yoshida discloses wherein the portion of the first circuitry includes one or more communication channels. Specifically, Yoshida teaches a switch module therein, in the first state, to present a device side storage interface according to a first storage protocol (PCIe standard) at the front storage interface connector (first/second portion of the circuitry), and in the second state, to present a device side storage interface according to a second storage protocol (NVMe standard), different from the first storage protocol, at the front storage interface connector (the other first/second portion of the circuitry). (Yoshida, [0029-0042, 0070-0077])
As per claim 8 and 18, Cayton-Chou with Yoshida teaches wherein the first portion of the first circuitry includes one or more first communication channels, and the second portion of the first circuitry includes one or more second communication channels. (Yoshida, [0029-0042, 0070-0077])
As per claims 9, 10, 19, and 20, Cayton-Chou with Yoshida teaches wherein the first circuitry includes an interface, wherein the third circuitry is configured to connect the interface to the memory based on the signal for retrieving the data from the memory. Yoshida discloses a switch module (Figs. 1, 2 PCIe switch, 12) wherein a first port portion and a second port portion (part of a plurality of physical devices, 13-0-13-3, Fig. 1, [0038-0042]) can adaptively operate with PCIe or NVMe standard ([0029-0033]) when connected to a host/server (Fig. 1, 11). The switch modules includes a rear storage interface (via ports 15-0 – 15-3, Fig. 2) and a front storage interface connector (via first port, 14, Fig. 2, [0033]) Therein, in the first state, to present a device side storage interface according to a first storage protocol (PCIe standard) at the front storage interface connector (first/second portion of one or more circuitry), and in the second state, to present a device side storage interface according to a second storage protocol (NVMe standard), different from the first storage protocol, at the front storage interface connector (the other first/second portion of the circuitry,. (Yoshida, [0029-0042, 0070-0077])
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c). Fischer et al., (US 12,189,554) is sited as prior art that teaches a multiplexer having a protocol selector that dynamically selects between multiple protocols between connected devices.
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to
this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMARA R PEYTON whose telephone number is (571)272-4157. The examiner can normally be reached on 9am-5pm, EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAMMARA R PEYTON/
Primary Examiner, Art Unit 2184
February 7, 2026