Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bassman et al., (US 6,295,567) and Sakalley et al., (US 9,934,173).
As per claims 1 and 11, Bassman teaches a device comprising: a connector first interface a connector (note connection to chassis, 203, Fig. 2, col. 4, lines 44-col.5, lines 1-7) configured to receive a signal (the chassis detection circuity provides a signal indicative of the presence of a structure, col.9, lines 13-16) first circuitry (note chassis type circuitry , col. 3 lines 55-57), wherein based on the signal, a memory device is identified to retrieve data from the memory device, (Bassman teaches that by detecting structural differences among the various planar plate types and providing a signal indicative of the differences, the present invention provides a system for allowing a computer system implementing a standardized system circuit board with standardized computer components and computer code to determine the chassis type and/or computer system type and execute operations accordingly, col. 3. lines 46-53; Circuit board 101 may be secured or attached to at least two types of planar plates with each planar plate type capable of being mounted and attached to at least one different chassis type col. 4, lines 9-43) wherein the data is selected to configure the first circuitry to operate according to a communication protocol; and second circuitry (note type of mode configuration circuitry, col.4,lines 9-43); coupled to the connector and the first circuity, wherein based on the signal..
Bassman does not expressly teach wherein a portion of the second circuitry is selected for connecting to a portion of the first circuitry to provide an interface that adheres to the communication protocol.
Sakalley discloses a device according to claim 1, wherein, a connector supports a first communication mode or a second communication mode being determined based on a received signal at the connector. Sakalley teaches determining a type of chassis in which a device is installed; a memory device (col. 4, lines 15-20) is identified to retrieve data from the memory device, and configuring the device to enable a first communication protocol or a second communication protocol the device according to the type of the chassis. Whereas the determining a type of chassis in which a device is installed includes accessing a signal from a pin on a connector coupled to the device. Sakalley teaches that the connector supports a plurality of Peripheral Component Interconnect Express (PCIe) lanes (a Peripheral Component Interconnect (PCI) Express® (PCIe) fabric; col. 4, lines 13-14) and Serial Attached Small Computer System Interface (SCSI) (SAS) pins (FIG. 4). Sakalley teaches wherein a portion of second circuitry is selected for connecting to a portion of the first circuitry to provide an interface that adheres to the communication protocol. Specifically, if the type of the chassis is NVMe, the mode configuration circuitry is operative to use a first two lanes of the PCIe lanes as both a first data plane and a first control plane for a first host and to disable use of an Ethernet port via the SAS pins (col. 5, lines 45-57 and FIG. 4)
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Bassman with the teachings of Sakalley for the flexibility in system configurations (Sakalley , col.3, lines 63-col.5,lines 1-57, Figs.1 and 4).
As per claim 2 and 12, Bassman in view of Sakalley teaches wherein the connector includes a connector for a solid state drive. (Sakalley, (col. 4, lines 15-20)
As per claim 3 and 13, Bassman in view of Sakalley teaches teaches wherein the first circuitry includes a field programmable gate array. ( Sakalley teaches “the computing device is a field programmable gate array (FPGA), Fig.5)
As per claim 4 and 14, Bassman in view of Sakalley teaches wherein the communication protocol is for receiving storage commands over a data communications bus. (Sakalley , col.3, lines 63-col.5,lines 1-57, Figs.1 and 4, Bassman connection to chassis, 203, Fig. 2, col. 4, lines 44-col.5, lines 1-7)
As per claim 5 and 15, Bassman in view of Sakalley teaches wherein the second circuitry includes routing or switching circuitry. Sakalley teaches that the connector supports a plurality of Peripheral Component Interconnect Express (PCIe) lanes (a Peripheral Component Interconnect (PCI) Express® (PCIe) fabric; col. 4, lines 13-14) and Serial Attached Small Computer System Interface (SCSI) (SAS) pins (FIG. 4). Sakalley teaches wherein a portion of second circuitry is selected for connecting to a portion of the first circuitry to provide an interface that adheres to the communication protocol. Specifically, if the type of the chassis is NVMe, the mode configuration circuitry is operative to use a first two lanes of the PCIe lanes as both a first data plane and a first control plane for a first host and to disable use of an Ethernet port via the SAS pins (col. 5, lines 45-57 and FIG. 4)
As per claim 6 and 16, Bassman in view of Sakalley teaches wherein the first portion of the second circuitry includes one or more first interfaces of the routing or switching circuitry, and the second portion of the second circuitry includes one or more second interfaces of the routing or switching circuitry. Sakalley teaches that the connector supports a plurality of Peripheral Component Interconnect Express (PCIe) lanes (a Peripheral Component Interconnect (PCI) Express® (PCIe) fabric; col. 4, lines 13-14) and Serial Attached Small Computer System Interface (SCSI) (SAS) pins (FIG. 4). Sakalley teaches wherein a portion of second circuitry is selected for connecting to a portion of the first circuitry to provide an interface that adheres to the communication protocol. Specifically, if the type of the chassis is NVMe, the mode configuration circuitry is operative to use a first two lanes of the PCIe lanes as both a first data plane and a first control plane for a first host and to disable use of an Ethernet port via the SAS pins (col. 5, lines 45-57 and FIG. 4)
As per claim 7 and 17, Bassman in view of Sakalley teaches wherein the portion of the first circuitry includes one or more communication channels. (Sakalley , col.3, lines 63-col.5,lines 1-57, Figs.1-5)
As per claim 8 and 18, Bassman in view of Sakalley teaches wherein the first portion of the first circuitry includes one or more first communication channels, and the second portion of the first circuitry includes one or more second communication channels. (Sakalley , col.3, lines 63-col.5,lines 1-57, Figs.1-5)
As per claims 9, 10, 19, and 20, Bassman in view of Sakalley teaches wherein the first circuitry includes an interface, wherein the third circuitry (Figs. 1-4) is configured to connect the interface to the memory based on the signal for retrieving the data from the memory. (Sakalley , col.3, lines 63-col.5,lines 1-57, Figs.1-5)
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c). Olarig (US 12,556,417) is sited as prior art that teaches a multiplexer having a protocol selector that dynamically selects between multiple protocols between connected devices.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMARA R PEYTON whose telephone number is (571)272-4157. The examiner can normally be reached on 9am-5pm, EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAMMARA R PEYTON/
Primary Examiner, Art Unit 2184
August 12, 2026
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