Prosecution Insights
Last updated: October 26, 2026
Application No. 18/967,275

EMBEDDED HARDWARE SECURITY MODULE (HSM)

Non-Final OA §103§DOUBLEPATENT
Filed
Dec 03, 2024
Priority
Jul 30, 2021 — continuation of 12/166,876
Examiner
OKEKE, IZUNNA
Art Unit
2497
Tech Center
2400 — Computer Networks
Assignee
Micron Technology Inc.
OA Round
2 (Non-Final)
82%
Grant Probability
Favorable
2-3
OA Rounds
1y 0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
618 granted / 756 resolved
+23.7% vs TC avg
Strong +15% interview lift
Without
With
+15.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
14 currently pending
Career history
770
Total Applications
across all art units

Statute-Specific Performance

§101
5.3%
-34.7% vs TC avg
§103
34.4%
-5.6% vs TC avg
§102
42.4%
+2.4% vs TC avg
§112
9.0%
-31.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 756 resolved cases

Office Action

§103 §DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,166,876. Although the claims at issue are not identical, they are not patentably distinct from each other because the patented claims in USPAT 12,166,876 is directed generating a cryptographic key using a seed value obtained from a PUF and processing a cryptographic operation using the cryptographic key. The claims in the instant invention are directed to selecting a cryptographic key generated using a seed from a PUF and performing a key management operation on the cryptographic key. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 7-10, 14-16, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Buer (US-20060072748), and further in view of Van Der Sluis et al. (US-20150234751). a. Referring to claims 1, 8 and 15: Regarding claims 1, 8 and 15, Buer teaches a device comprising: a volatile storage area storing a plurality of cryptographic keys (Para 105 and 109…. volatile key cache location); and a processor configured to: receive a key management request from an external device via an interface, select a cryptographic key from the plurality of cryptographic keys based on the key management request, perform a key management operation on the selected cryptographic key, and provide a response to the external device indicating a result of the key management operation (Para 91, 92, 97, 110, 111, …. external data interface for receiving command such as key management operations (Para 21), referencing appropriate key stored in the key cache, performing key management operation and indicating completion by returning the key value together with non-secure configuration value). Buer is silent with respect to a PUF, and a seed value derived from the PUF. However, a PUF and a seed value derived from the PUF for key generation are well known in the art and disclosed by Van der Sluis in Para 15, 19 and 37 (derived key (from memory used as PUF) used as seed for finding asymmetric keypair). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Buer by deriving the seed value from a PUF as taught by Van Der Sluis for the purpose of removing the root secret from the NV memory, where t can be recovered from a physical attack that opens and probes the memory. a. Referring to claim 2: Regarding claim 2, the combination of Buer and Van Der Sluis teaches the device of claim 1, wherein the key management operation comprises generating a new cryptographic key (See Buer, Para 68…. generating new key). a. Referring to claims 3, 9, 10 and 16: Regarding claims 3, 9, 10 and 16, the combination of Buer and Van Der Sluis teaches the device of claim 1, wherein the key management operation comprises exporting a public portion of the selected cryptographic key (See Buer, Para 131… exporting the public key effectively deletes/erases it from the storage area). a. Referring to claims 7, 14 and 20: Regarding claims 7, 14 and 20, the combination of Buer and Van Der Sluis teaches the device of claim 1, wherein the cryptographic keys comprise asymmetric key pairs (See Buer, Para 23 and 69…. asymmetric keypair). a. Referring to claim 18: Regarding claim 18, the combination of Buer and Van Der Sluis teaches the non-transitory computer-readable storage medium of claim 15, wherein the PUF comprises an uninitialized portion of the volatile storage arca (See Van Der Sluis, Para 23…. un-initialized SRAM blocks that may be used as the memory used as a PUF). Claims 4, 13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Buer (US-20060072748) and Van Der Sluis et al. (US-20150234751), and further in view of Taylor et al. (US-9,363,078). a. Referring to claims 4, 13 and 19: Regarding claims 4, 13 and 19, the combination of Buer and Van Der Sluis teaches a PCI interface (See Buer, Paea 72-73) but is silent with respect to the interface comprising a PCIe interface. However, PCIe interfaces are well known in the art and taught by Taylor in Col 10, lines 45-61 (PCI Express interface). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Buer and Van Der Sluis by using a PCIe interface in place of the PCI interface as taught by Taylor, for the purpose of improving the interface throughput to match the cryptographic processing. Claim(s) 5, 6, 11, 12, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Buer (US-20060072748) and Van Der Sluis et al. (US-20150234751), and further in view of Bell et al. (US-20130142329). a. Referring to claims 5, 11 and 17: Regarding claims 5, 11 and 17, the combination of Buer and Van Der Sluis teaches the storage of claim 1 but fails to teach that the storage area comprises a static random-access memory. However, storage areas comprising static random-access memory is well known in the art and described by Bell in Para 15 and 23…. (SRAM memory). Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the combination of Buer and Van Der Sluis and implement the storage as a static random-access memory as taught by Bell for the purpose of fast temporary data storage and access. a. Referring to claims 6 and 12: Regarding claims 6 and 12, the combination of Buer, Van Der Sluis and Bell teach the device of claim 1, wherein the PUF comprises a designated portion of the volatile storage area. (See Bell, Para 15…. PUF SRAM) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to IZUNNA OKEKE whose telephone number is (571)270-3854. The examiner can normally be reached Mon - Fri 8 - 4 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELENI SHIFERAW can be reached at (571) 272-3867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IZUNNA OKEKE/Primary Examiner, Art Unit 2497
Read full office action

Prosecution Timeline

Dec 03, 2024
Application Filed
Jun 09, 2026
Non-Final Rejection mailed — §103, §DOUBLEPATENT
Sep 09, 2026
Response Filed
Oct 16, 2026
Non-Final Rejection mailed — §103, §DOUBLEPATENT (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
82%
Grant Probability
97%
With Interview (+15.2%)
2y 11m (~1y 0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 756 resolved cases by this examiner. Grant probability derived from career allowance rate.

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