Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
As per the instant application having Application No. 18/967,497, the amendment filed on 3/6/2026 is herein acknowledged. Claims 4, 9 and 15 have been canceled and claims 1, 6 and 11 have been amended. Claims 1-3, 5-8, 10-14 and 16-19 are pending.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
TERMINAL DISCLAIMER
The terminal disclaimer filed on 3/6/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US 12,197,787 has been reviewed and is accepted. The terminal disclaimer has been recorded.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-7, 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0011642) in view of Khakifirooz et al. (US 2019/0227751) and Yoon et al. (2012/0324178).
1. A storage device comprising: a memory including a plurality of first type memory blocks and a plurality of second type memory blocks; and [Lee teaches memory comprising SCL data blocks in first region 252 and data blocks (MCL, TLC, QLC data blocks) in second region 254 (fig. 4 and related text) “[0107] Referring to FIG. 4, a nonvolatile memory die 250 may include a first region 252 and a second region 254. The first region 252 includes a plurality of first memory blocks 40_1 each including one or more single-level cells (SLCs). The second region 254 may include a plurality of second memory blocks 40_2 each including one or more multi-level cells (MLCs)”]
a controller configured to: determine write throughput, which is an indicator of a performance of the storage device to write data, based on a plurality of write commands received from outside of the storage device, [Lee teaches “[0058] The controller 130 in the memory system 110 may determine whether SLC buffering operation is performed for inputted data based on data input/output (I/O) speed (I/O throughput) required by the external device or the host 102 “ “[0061] … The I/O speed check circuitry 194 may determine the data input/output speed (e.g., I/O throughput) based on the amount of data transferred between the transitions of the real time clock signal RTC or during a period of the real time clock signal RTC… ” “[0127]…The controller 130 in the memory system 110 may recognize an amount of data transferred with one or more write requests from the external device in a preset reference time period (for example, a period of a real time clock), and the controller 130 may thereby determine a data input/output speed (e.g., I/O throughput) required by the external device.”] but Lee refers to the throughput being determined based on input/output; thus, not expressly disclosing the throughput based on a plurality of write commands… , which is an indicator of a performance of the storage device to write data
write target data requested from the outside into a first memory area including one or more of the first type memory blocks when the write throughput is greater than or equal to a threshold throughput, and [Lee teaches “[0128]… the controller 130 may program a piece of input data in a SLC buffer (S1006) when the data input/output speed (e.g., I/O throughput) is more than a first reference value (CASE1). The controller 130 may temporarily store all inputted data (that is, data to be programmed) in the SLC buffer…”]
write target data requested from the outside into a second memory area including one or more of the second type memory blocks when the write throughput is less than the threshold throughput, [Lee teaches “[0129] When the data input/output speed (e.g., I/O throughput) of the memory system 110 is less than a second reference value (CASE2), the controller 130 may not use an SLC buffer to buffer the inputted data, but may store the inputted data in the MLC block (e.g., the second memory block 40_2) (S1010)… the controller 130 may program the inputted data in a MLC memory block without temporarily storing the inputted data in the SLC buffer, so that subsequent data migration from the SLC buffer to the MLC memory block can be avoided.”]
wherein the first type memory blocks operate at a higher speed than the second type memory blocks, [Lee teaches “[0055] Read and program operations in the multi-level cell (MLC) may be slower than those in the single-level cell (SLC) even when the structure of the two cells is the same.”]
Lee does not expressly disclose wherein the controller is configured to determine the write throughput, which is an indicator of a performance of the storage device to write data based on write performance values for respective N target write commands selected from among the plurality of write commands, wherein the controller is configured to determine an average write performance value for M target write commands from among the N target write commands and to determine the average write performance value as the write throughput when the average write performance value is less than or equal to a maximum write performance value, and wherein the N is a natural number greater than or equal to 2 and the M is a natural number less than or equal to the N… and wherein the controller is configured to determine an average of write performance values for an M number of las recently received, from the present, write commands from among the N target write commands as the average write performance value.
Regarding the limitations “the throughput based on a plurality of write commands,” Khakifirooz teaches [“[0034]… the controller determines if a higher write throughput is needed to service incoming write requests. In one example, if the controller determines that the write throughput is higher than can be handled by writing to the slower higher density memory units or cells, the controller reconfigures the memory units to operate in a smaller number of bits-per-cell configuration.” “[0041]… consider that host 110 generates a sequence of writes to SSD 120 that will result in a higher write throughput than controller 130 can store to array 140 in a given time window… controller 130 configures portion 142 of array 140 as a less dense storage area, while portion 144 remains unaffected. In such an example, reconfiguring can refer to allocation by controller 130 of portion 142 to store data at a lower density than portion 144. When data is stored to portion 142, the data is stored in accordance with a different program sequence to result in storage at a different density or bits per cell than the density of portion 144.” “[0035]… the controller can determine to use the first density when there is sufficient write bandwidth to program the storage cells at the first density. When the write throughput increases, the controller can program the same MLC storage cells at the second density instead of the first density, using the same program process and voltage. When the write throughput decreases, the controller can program the same MLC storage cells at the first density again.”].
Lee and Khakifirooz are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Lee to have the throughput to decide whether to write to SLC or MLC be determined on a plurality of write operations as taught by Khakifirooz since doing so would provide higher burst write throughput (par 0034).
The combination of Lee and Khakifirooz does not expressly disclose wherein the controller is configured to determine the write throughput which is an indicator of a performance of the storage device to write data, based on write performance values for respective N target write commands selected from among the plurality of write commands, wherein the controller is configured to determine an average write performance value for M target write commands from among the N target write commands and to determine the average write performance value as the write throughput when the average write performance value is less than or equal to a maximum write performance value, and wherein the N is a natural number greater than or equal to 2 and the M is a natural number less than or equal to the N, and wherein the controller is configured to determine an average of write performance values for an M number of las recently received, from the present, write commands from among the N target write commands as the average write performance value
With respect to the limitations wherein the controller is configured to determine the write throughput ,which is an indicator of a performance of the storage device to write data based on write performance values for respective N target write commands selected from among the plurality of write commands, [Yoon teaches “the performance of the data storage device 1100 may be determined in real time according to a data throughput/bandwidth” (par. 0068) “[0110] As illustrated in FIG. 8, the performance (or, bandwidth) of the data storage device 1100 may vary as time goes by.” “An average value of data throughputs on write requests made during a predetermined period of time may be used to judge whether the data throughput satisfies the target performance.” (par. 0111) where, as performance is monitored over different periods of time and varies from one time period to another and is thus determined over the number of write requests occurring over the different time periods or N write requests. Yoon further teaches Yoon teaches [“measuring a throughput performance of the data storage device; and based on the measured throughput performance, selecting a scheduling order for performing the first programming stage operations and the second programming stage operations.” (par. 0022) “ For example, the performance of the data storage device 1100 may be determined in real time according to a data throughput/bandwidth.” (par. 0068) and “[0104] Referring to FIG. 7, in step S110, the performance of a data storage device 1100 may be measured. Measuring of the performance may be made, for example, based upon the amount of data processed during a given time. The amount of data processed during a given time may be referred to as `data throughput`. In operation S120, whether the data throughput satisfies the target performance may be judged.
[0105] If the data throughput is judged to satisfy the target performance, in operation S130, a static scheduling manner may be selected as a scheduling manner. When the static scheduling manner is selected, a buffer program operation may be performed as soon as data of the minimum program unit of the first region 101 for a particular word line is stored in a buffer memory 201, and a main program operation may be carried out as soon as data of the minimum program unit of the second region 102 for a particular word line is gathered in the first region 101.
[0106] If the data throughput is judged not to satisfy the target performance, in operation S140, a dynamic scheduling manner may be selected as the scheduling manner. When the dynamic scheduling manner is selected, the buffer program operation may be carried out for a continuous period of time. In this case, the main program operation on data stored in the first region 101 via the buffer program operation may be delayed. The buffer program operation may be performed alone, without being interrupted by execution of the main program operation. The delayed main program operations may be made by a memory controller 200 considering various limitations.
[0109] The performance of a data storage device 1100 may be measured using a bandwidth (or, data throughput), for example….
[0111] An average value of data throughputs on write requests made during a predetermined period of time may be used to judge whether the data throughput satisfies the target performance.”] Which clearly corresponds to a write throughput for write requests indicating a performance of the data storage device to write data as claime]
wherein the controller is configured to determine an average write performance value for M target write commands from among the N target write commands and to determine the average write performance value as the write throughput when the average write performance value is less than or equal to a maximum write performance value, and wherein the N is a natural number greater than or equal to 2 and the M is a natural number less than or equal to the N [Yoon teaches “[0110] As illustrated in FIG. 8, the performance (or, bandwidth) of the data storage device 1100 may vary as time goes by.” “An average value of data throughputs on write requests made during a predetermined period of time may be used to judge whether the data throughput satisfies the target performance.” (par. 0111)” where the number of write requests occurring during a given time period is interpreted to correspond to the M write requests. “[0109] The performance of a data storage device 1100 may be measured using a bandwidth (or, data throughput), for example. The data storage device 1100 may have a maximum bandwidth. In one embodiment, the target performance of the data storage device 1100 may be set to a target bandwidth that is a certain bandwidth margin higher than a minimum desired bandwidth allowable… the target performance (i.e., target threshold bandwidth) of the data storage device 1100 can be set close to or at a maximum bandwidth of the device 1100.” Thus, the average write performance for M write commands during a given time period is determined while keeping the target performance (measured in terms of throughput or bandwidth) close or at the maximum or when below or equal to the maximum]
and wherein the controller is configured to determine an average of write performance values for an M number of las recently received, from the present, write commands from among the N target write commands as the average write performance value [Yoon teaches “[0111] In an exemplary embodiment, the data throughput may indicate an average amount of data processed during a predetermined period of time. For example, after data input at a write request of a host 300 is stored in a multi-bit memory device 100, the data storage device 1100 may send a response to the write request to the host 300. At this time, it is possible to calculate a single data point of data throughput based upon a time between the write request and the response and the amount of write-requested data. An average value of data throughputs on write requests made during a predetermined period of time may be used to judge whether the data throughput satisfies the target performance.”], where the average value of data throughputs as taught by Yoon may be measured over different time intervals, include a most recent time period or interval. The write throughput for these write commands representing the average throughput over this interval includes an M number of recently received, from the present or any interval write commands from a total number of writes made during different time intervals.
Lee, Khakifirooz and Yoon are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Lee and Khakifirooz to include wherein the controller is configured to determine the write throughput which is an indicator of a performance of the storage device to write data, based on write performance values for respective N target write commands selected from among the plurality of write commands, wherein the controller is configured to determine an average write performance value for M target write commands from among the N target write commands and to determine the average write performance value as the write throughput when the average write performance value is less than or equal to a maximum write performance value, and wherein the N is a natural number greater than or equal to 2 and the M is a natural number less than or equal to the, and wherein the controller is configured to determine an average of write performance values for an M number of las recently received, from the present, write commands from among the N target write commands as the average write performance value, as taught by Yoon since doing so would provide the benefits of allowing for efficient access operations and computations of average throughput.
Therefore, it would have been obvious to combine Lee, Khakifirooz and Yoon for the benefit of creating a storage system/method to obtain the invention as specified in claim 1.
2. The storage device according to claim 1, wherein a total size of data requested by the N target write commands is less than a size of a write buffer that stores data to be written in the memory [Lee teaches “[0128]… the controller 130 may program a piece of input data in a SLC buffer (S1006) when the data input/output speed (e.g., I/O throughput) is more than a first reference value (CASE1). The controller 130 may temporarily store all inputted data (that is, data to be programmed) in the SLC buffer.” Thus, the total size of the data must be less than the size of the buffer. Yoon teaches “[0070]… if data of the minimum program unit of the first region 101 is stored in the buffer memory 201, the memory controller 200 may control the multi-bit memory device 100 such that data of the minimum program unit is stored (or, programmed) in the first region 101. This may be called a buffer program operation (BP). If data of the minimum program unit of the second region 102 is gathered at the first region 101, the memory controller 200 may control the multi-bit memory device 100 such that data of the minimum program unit of the second region 102 is stored (or, programmed) in the second region 102. This may be called a main program operation (MP). The buffer program operation and the main program operation may form an on-chip buffer program (OBP) operation, which will be more fully described below.” “[0074]… it is possible to minimize a size of the buffer memory 201 of the memory controller 200 by storing data in the first region 101 through the buffer program operation and storing data in the second region 102 through the main program operation. For example, it may be unnecessary to retain data for a fine program operation in the buffer memory 201. Accordingly, a size of the buffer memory 201 of the memory controller 200 may be made smaller…”. Where a plurality of write requests are sent (par. 0111)].
6. A method for operating a storage device, comprising: determining write throughput, which is an indicator of a performance of the storage device to write data, based on a plurality of write commands received from outside of the storage device; in response to determining the write throughput is greater than or equal to a threshold throughput, writing, target data requested from the outside into a first memory area including one or more of a plurality of first type memory blocks; and in response to determining the write throughput is less than to the threshold throughput, writing target data requested from the outside into a second memory area including one or more of a plurality of second type memory blocks, wherein the first type memory blocks operate at a higher speed than the second type memory blocks, wherein determining the write throughput comprises: determining N target write commands from among the plurality of write commands; and determining the write throughput based on write performance values for the respective N target write commands, wherein determining the write throughput based on write performance values for the respective N target write commands comprises: determining an average write performance value for M target write commands from among the N target write commands; in response to determining the average write performance value is less than or equal to a maximum write performance value setting the average write performance value as the write throughput; wherein the N is a natural number greater than or equal to 2 and the M is a natural number less than or equal to the N, and wherein determining the average write performance determines an average of write performance values for an M number of last recently received, from the preset, write commands from among the N target write commands as the average write performance value [The rationale in the rejection of claim 1 is herein incorporated].
7. The method according to claim 6, wherein a total size of data requested by the N target write commands is less than a size of a write buffer that stores data to be written in the memory [The rationale in the rejection of claim 2 is herein incorporated].
11. A controller comprising: a memory interface configured to communicate with a memory including a plurality of single level cell (SLC) memory blocks and a plurality of memory blocks which include multi-level cell (MLC), triple level cell (TLC) or quad level cell (QLC); and a control circuit configured to: determine write throughput based on a plurality of write commands received from outside of the controller, write data requested by the outside of the controller to one or more of the SLC memory blocks when the write throughput is greater than or equal to a threshold throughput, and write data requested by the outside of the controller to one or more of the memory blocks which include MLC, TLC or QLC when the write throughput is less than the threshold throughput, wherein the control circuit is configured to determine the write throughput based on write performance values for respective N target write commands selected from among the plurality of write commands, wherein the control circuit is configured to determine an average write performance value for M target write commands from among the N target write commands and to determine the average write performance value as the write throughput when the average write performance value is less than or equal to a maximum write performance value, and wherein the N is a natural number greater than or equal to 2 and the M is a natural number less than or equal to the N, and wherein the control circuit is configured to determine an average of write performance values for an M number of last recently received, from the present, write commands form among the N target write commands as the average write performance value [The rationale in the rejection of claim 1 is herein incorporated. Note Lee teaches “[0052] The memory device 150 may include a first memory block 40_1 including a single-level cell (SLC) and a second memory block 40_2 including a multi-level cell (MLC). Here, the single-level cell (SLC) is a kind of memory cells that individually stores one bit of data. The multi-level cell (MLC) is a kind of memory cells that individually stores multiple bits of data. For example, the multi-level cell (MLC) may include at least one of a double-level cell (DLC) storing two-bit data, a triple-level cell (TLC) storing 3-bit data, or a quad-level cell (QLC) for storing 4-bit data.” Khakifirooz teaches “[0027] As described herein, a storage system is dynamically reconfigurable to use one density of multilevel bitcells or another density of multilevel bitcells. For example, the system could support QLC (quad level cells) and TLC (trilevel cells), or QLC and double level cells.” “[0043] SSD 120 is illustrated to include buffer 122. Buffer 122 represents a buffer for an access interface between array 140 and controller 114. Buffer 122 includes memory that has faster access time than array 140. For example, buffer 122 can include SLC (single level cell)”].
12. The controller according to claim 11, further comprising a write buffer that stores data requested by the outside of the controller to be written in the memory [The rationale in the rejection of claim 2 is herein incorporated].
13. The controller according to claim 12, wherein a total size of data requested by the N target write commands is less than a size of the write buffer [The rationale in the rejection of claim 2 is herein incorporated].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0011642) in view of Khakifirooz et al. (US 2019/0227751) and Yoon et al. (2012/0324178) as applied in the rejection of claim 11 above, and further in view of Tressler et al. (US 2014/0372684).
16. The controller according to claim 11, wherein the control circuit is configured to determine the write throughput based on a sum of sizes of data written to the memory according to the plurality of write commands for a reference time period [Yoon teaches “An average value of data throughputs on write requests made during a predetermined period of time may be used to judge whether the data throughput satisfies the target performance.” (par. 0111)” thus determining average throughput over a plurality of write requests during a reference period which would require the total or sum of the data written over the reference period] but the combination of Lee, Khakifirooz and Yoon does not expressly refer to the throughput based on the sum of sizes of data written over the reference period; however, regarding these limitations, Tressler teaches [“Controller 310 periodically determines average throughput… Controller 310 includes data written to solid state memory 320 in the average throughput determinations, including metadata” (par. 0034) where “the mechanism determines the average write throughput for the period P by taking the MB written and dividing by the number of seconds in P” (par. 0055) where a total of data written represents a sum of the sizes of the data written or the MB written as taught by Tressler].
Lee, Khakifirooz, Yoon and Tressler are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Lee, Khakifirooz and Yoon to include as taught by Tressler since doing so would provide the benefits of [facilitating computations of average throughput over a time period and enabling throttling on average write throughput (par. 0001)].
Therefore, it would have been obvious to combine Lee, Khakifirooz, Yoon and Tressler for the benefit of creating a storage system/method to obtain the invention as specified in claim 16.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c). Gill et al. (US 2008/0168234) teaches “[0049] The adjusted low and high thresholds 98 and 100 are used to throttle or determine the number of concurrent tasks assigned to destage write requests for one storage group. If the occupancy for a storage group 22 is relatively toward the high threshold 100, then the cache manager 14 may tend to increase the number of tasks assigned to that storage group 22 to avoid reaching the threshold. If the storage group 22 occupancy of the cache 10 is relatively toward the low threshold 98, then the cache manager 14 may tend to decrease the number of tasks assigned to that storage group 22 to avoid reaching the low threshold. In certain embodiments, the storage group low threshold is used to ensure that there are a sufficient number of write requests pending in the cache 10 such that writes may be written to spatially proximate storage locations in the storage group 22 to increase the write throughput. Write throughput increases as the number of pending write requests increases because the probability of writes at more proximate locations increases, which reduces the seek time and distance required by the storage device to position a write mechanism and/or the storage media (e.g., disk or tape) to the storage location to write the data… [0051] In certain embodiments, the adjustment factor 118 may comprise a value between zero and one. If the cache occupancy 116 is relatively toward the cache high threshold 114, then the cache manager 14 may tend to lower the adjustment factor toward zero, which when applied, e.g., multiplied, to the storage group 22 low 92 and high 94 thresholds lowers the thresholds, such as the high threshold. This ensures that a greater number of tasks are allocated to process destage requests for the storage groups, because more tasks are allocated to a storage group as the storage group cache occupancy 104 increases toward the downward adjusted storage group high threshold 100. If the cache occupancy 116 is relatively toward the cache low threshold 112, then the cache manager 14 may tend to increase the adjustment factor to one, which when applied, e.g., multiplied, to the storage group 22 low 92 and high 94 thresholds increases the adjusted thresholds 98 and 100, such as the high threshold 100. This ensures that relatively fewer tasks are allocated to process destage requests for the storage groups because fewer tasks are allocated to a storage group as the storage group cache occupancy 104 is further away from the storage group high threshold 94. By lowering the number of tasks assigned to destage requests, the rate at which destage requests are processed is lowered leading to a gradual increase in the number of pending write requests. As discussed, increasing the number of pending write requests may increase the likelihood that destaged write requests are closer in spatial proximity to improve write throughput at the storage device.”
ACKNOWLEDGEMENT OF ISSUES RAISED BY APPLICANT
Response to Amendment
The double patenting rejections in the non-final rejection mailed on 12/8/2025 have been overcome by the terminal disclaimer filed on 3/6/2026.
Applicant's arguments filed on March 6, 2026 with respect to the 35 USC 103 rejection have been fully considered but they are not deemed persuasive.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Claims must be given the broadest reasonable interpretation during examination and limitations appearing in the specification but not recited in the claim are not read into the claim (See M.P.E.P. 2111 [R-1]).
Applicant argues “Yoon does not define data throughput as an indicator of performance in writing the data… Yoon measures states in paragraph [0111] that “it is possible to calculate a single data point of data throughput based upon a time between the write request and the response and the amount of write-requested data.”… it is clear that Yoon only discloses measuring the time it takes to transfer data to be written, or bandwidth. Yoon does not however, teach or suggest measuring the time it takes to actually write the data, or “write throughput”… Yoon merely discloses changing the operational method to achieve a pre-determined target performance by considering the changing bandwidth. The technical concepts and control targets of Yoon retroactively pursue data transmission and data scheduling performance goals through simple task scheduling changes… The technical concepts are focused on actively determining write throughput itself and managing the writing operation to improve performance. There is no need, for example, to consider general data transmission bandwidth over a period of time as shown in Figure 8 of Yoon because the inventions are focused on determining the performance of writing data for target write commands.”
In response, these arguments have been fully considered but are not deemed persuasive.
First, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., write throughput being the time it takes to actually write the data) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Note the pending claims define the pending claims define the terms write throughput as “an indicator of a performance of the storage device to write data” and do not contain any limitation dictating that the performance be measured in terms of time as argued by Applicant.
Regarding write throughput, which is an indicator of a performance of the storage device to write data, Yoon teaches [“measuring a throughput performance of the data storage device; and based on the measured throughput performance, selecting a scheduling order for performing the first programming stage operations and the second programming stage operations.” (par. 0022) “ For example, the performance of the data storage device 1100 may be determined in real time according to a data throughput/bandwidth.” (par. 0068) and “[0104] Referring to FIG. 7, in step S110, the performance of a data storage device 1100 may be measured. Measuring of the performance may be made, for example, based upon the amount of data processed during a given time. The amount of data processed during a given time may be referred to as `data throughput`. In operation S120, whether the data throughput satisfies the target performance may be judged.
[0105] If the data throughput is judged to satisfy the target performance, in operation S130, a static scheduling manner may be selected as a scheduling manner. When the static scheduling manner is selected, a buffer program operation may be performed as soon as data of the minimum program unit of the first region 101 for a particular word line is stored in a buffer memory 201, and a main program operation may be carried out as soon as data of the minimum program unit of the second region 102 for a particular word line is gathered in the first region 101.
[0106] If the data throughput is judged not to satisfy the target performance, in operation S140, a dynamic scheduling manner may be selected as the scheduling manner. When the dynamic scheduling manner is selected, the buffer program operation may be carried out for a continuous period of time. In this case, the main program operation on data stored in the first region 101 via the buffer program operation may be delayed. The buffer program operation may be performed alone, without being interrupted by execution of the main program operation. The delayed main program operations may be made by a memory controller 200 considering various limitations.
[0109] The performance of a data storage device 1100 may be measured using a bandwidth (or, data throughput), for example….
[0111] An average value of data throughputs on write requests made during a predetermined period of time may be used to judge whether the data throughput satisfies the target performance.”] Which clearly corresponds to a write throughput for write requests indicating a performance of the data storage device to write data as claimed.
Regarding the limitations “an average of write performance values for an M number of last recently received, from the present, write commands from among the N target write commands as the average write performance value”, Applicant argues “the present inventions explicitly specify a temporal selection criterion of “the M number of last recently received” data… data from a subset of all write commands, that, an N number of target write commands… Selecting a specific number of data associated with a specific type of target write commands is an essential configuration in the inventions for most accurately reflecting the current load status and performance characteristics of the storage device… Paragraph [0111] of Yoon states that an “average value of data throughput on write requests made during a predetermined period of time may be used to judge whether data throughput satisfies the target performance… this language does not disclose… the measuring of writing of data. The only disclosure is for determining the data throughput (or transmission) for data of a write request over a “predetermined time period.”… Yoon fails to disclose or suggest the specific technical feature of using the “M most recently received items”, which is an event-based criterion and not a time based criterion, as the basis for measurement… the expression “predetermined period”… refers to a fixed temporal interval, while the “M most recent items” recited in the present invention… enables tracking relative to the current time… “predetermined period” is too broad to teach or suggest the specificity of measuring performance in writing the “M most recent items” for target write commands… Yoon tends to teach away from the inventions…”.
In response, these arguments have been fully considered but are not deemed persuasive.
First, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., Selecting a specific number of data associated with a specific type of target write commands… the measuring of writing of data) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding the argument that ““M most recently received items”, which is an event-based criterion and not a time based criterion,”, the examiner would like to respectfully point out that the pending claim recites “an average of write performance values for an M number of last recently received, from the present,” where last “recently received”, from the present, certainly include a time based criterion and not merely an event based criterion. But a number of most recently or temporal condition for a number of write commands. Further, the present or a present time period may be any time period in a timeline.
The pending claims recite “an average of write performance values for an M number of last recently received, from the present, write commands from among the N target write commands as the average write performance value” which is taught by the combination of Lee, Khakifirooz and Yoon as [Yoon teaches “[0111] In an exemplary embodiment, the data throughput may indicate an average amount of data processed during a predetermined period of time. For example, after data input at a write request of a host 300 is stored in a multi-bit memory device 100, the data storage device 1100 may send a response to the write request to the host 300. At this time, it is possible to calculate a single data point of data throughput based upon a time between the write request and the response and the amount of write-requested data. An average value of data throughputs on write requests made during a predetermined period of time may be used to judge whether the data throughput satisfies the target performance.”], where the average value of data throughputs as taught by Yoon may be measured over different time intervals, include a most recent time period or interval. The write throughput for these write commands representing the average throughput over this interval includes an M number of recently received, from the present or any interval write commands from a total number of writes made during different time intervals.
The arguments that “Yoon tends to teach away from the inventions…” are not deemed persuasive since Yoon does not criticize, discredit, or otherwise discourage the solution claimed In re Fulton, 391 F.3d 1195, 1201, 73 USPQ2d 1141, 1146 (Fed. Cir. 2004). See also MPEP 2123.
Regarding all other Claims not specifically traversed above and whose rejections were upheld, the Applicant contends that the listed claims are allowable by virtue of their dependence on other allowable claims. As this dependence is the sole rationale put forth for the allowability of said dependent claims, the Applicant is directed to the Examiner's remarks above. Additionally, any other arguments the Applicant made that were not specifically addressed in this Office Action appeared to directly rely on an argument presented elsewhere in the Applicant’s response that was traversed, rendered moot or found persuasive above.
All arguments by the applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 3/6/2026.
CLOSING COMMENTS
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-2, 6-7, 11-13 and 16 have received an action on the merits and are subject to a final rejection.
a(2) CLAIMS NO LONGER UNDER CONSIDERATION
Claims 4, 9 and 15 have been canceled.
a(3) ALLOWABLE SUBJECT MATTER
Per the instant office action, claims 3, 5, 8, 10, 14 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if the double patenting rejections above are overcome.
3. The storage device according to claim 1, wherein the controller is configured to determine a write performance value for a first target write command received K-th among the N target write commands as a value obtained by dividing a size of data requested by the first target write command by time from when a second target write command, which is received (K-1)-th among the N target write commands, is received to when the first target write command is received, and wherein the K is a natural number greater than or equal to 2 and less than or equal to the N.
5. The storage device according to claim 1, wherein the controller is configured to determine the write throughput based on a sum of sizes of data written to the memory according to the plurality of write commands for a reference time period, and wherein the reference time period is an update period of a mapping table indicating mapping information between logical address and physical address or an allocation period of a super memory block including one or more of a plurality of memory blocks included in the memory.
8. The method according to claim 6, wherein a write performance value for a first target write command received K-th among the N target write commands is determined as a value obtained by dividing a size of data requested by the first target write command by time from when a second target write command, which is received (K-1)-th among the N target write commands, is received to when the first target write command is received, and wherein K is a natural number greater than or equal to 2 and less than or equal to the N.
10. The method according to claim 6, wherein determining the write throughput determines the write throughput based on a sum of sizes of data written to the memory in response to the plurality of write commands for a reference time period, and wherein the reference time period is an update period of a mapping table indicating mapping information between logical address and physical address or an allocation period of a super memory block including one or more of a plurality of memory blocks included in the memory.
14. The controller according to claim 11, wherein the control circuit is configured to determine a write performance value for a first target write command received K-th among the N target write commands as a value obtained by dividing a size of data requested by the first target write command by time from when a second target write command, which is received (K-1)-th among the N target write commands, is received to when the first target write command is received, and wherein the K is a natural number greater than or equal to 2 and less than or equal to the N.
17. The controller according to claim 16, wherein the reference time period is an update period of a mapping table indicating mapping information between logical address and physical address of the memory.
18. The controller according to claim 16, wherein the reference time period is an allocation period of a super memory block including one or more of a plurality of SLC memory blocks.
19. The controller according to claim 16, wherein the reference time period is an allocation period of a super memory block including one or more of a plurality of memory blocks which includes MLC, TLC or QLC.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIMA RIGOL whose telephone number is (571)272-1232. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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March 27, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135