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The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-28 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-30 of U.S. Patent No. 12,166,581. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 1, U.S. Patent No. 12,166,581 recites an apparatus for wireless communication at a user equipment (UE) (Claim 1, An apparatus for wireless communication at a user equipment (UE)), comprising:
one or more memories (Claim 1, a memory); and
at least one processor coupled to the one or more memories (Claim 1, at least one processor coupled to the memory), the one or more memories storing instructions configurable to be executable by the at least one processor to cause the apparatus to (Claim 1, memory storing instructions executable by the at least one processor to configure the apparatus to):
calculate a slot length for each uplink (UL) slot of a plurality of UL slots, the slot length for each UL slot being associated with a plurality of rate matching output bits, each UL slot including a starting point for the plurality of rate matching output bits, the slot length for each UL slot being associated with a starting boundary, the plurality of UL slots being associated with at least one of a single transport block (TB) or a single rate matching (Claim 1, calculate a slot length for each uplink (UL) slot of a plurality of UL slots, the slot length for each UL slot being associated with a plurality of rate matching output bits, each UL slot including a starting point for the plurality of rate matching output bits, the slot length for each UL slot being associated with a starting boundary, the plurality of UL slots being associated with at least one of a single transport block (TB) or a single rate matching);
allocate one or more bits of the plurality of rate matching output bits for a modulation process (Claim 1, allocate one or more bits of the plurality of rate matching output bits for a modulation process);
write physical uplink shared channel (PUSCH) data in at least one bit of the plurality of rate matching output bits, the at least one bit corresponding to uplink control information (UCI) multiplexing (Claim 1, refrain from allocating at least one bit of the plurality of rate matching output bits for the modulation process; Claim 16, wherein the instructions are further executable by the at least one processor to configure the UE to refrain from allocating the at least one bit by: writing physical uplink shared channel (PUSCH) data in the at least one bit); and
overwrite the PUSCH data with UCI multiplexing data in the at least one bit (Claim 1, refrain from allocating at least one bit of the plurality of rate matching output bits for the modulation process; Claim 16, refrain from allocating the at least one bit by…and overwriting UCI multiplexing data in the at least one bit).
Regarding claim 2, U.S. Patent No. 12,166,581 recites wherein the plurality of rate matching output bits corresponds to a rate matching output size (Claim 2, wherein the plurality of rate matching output bits corresponds to a rate matching output size).
Regarding claim 3, U.S. Patent No. 12,166,581 recites wherein the single TB corresponds to a TB over multiple slots (TBoMS) (Claim 3, wherein the single TB corresponds to a TB over multiple slots (TBoMS)).
Regarding claim 4, U.S. Patent No. 12,166,581 recites wherein the instructions configurable to be executed are further executable by the at least one processor to cause the UE to: store the starting boundary associated with each UL slot; wherein the at least one bit of the plurality of rate matching output bits corresponds to an end of one or more slots of the plurality of UL slots (Claim 4, wherein the instructions are further executable by the at least one processor to configure the UE to: store the starting boundary associated with each UL slot; wherein the at least one bit of the plurality of rate matching output bits that is refrained from being allocated corresponds to an end of one or more slots of the plurality of UL slots).
Regarding claim 5, U.S. Patent No. 12,166,581 recites wherein the instructions configurable to be executed are further executable by the at least one processor to cause the UE to: determine one or more UCI bits to be multiplexed, the one or more UCI bits not corresponding with the UCI multiplexing; and calculate and store the starting boundary associated with each UL slot based on the one or more UCI bits; wherein the at least one bit of the plurality of rate matching output bits corresponds to an end of one or more slots of the plurality of UL slots (Claim 5, wherein the instructions are further executable by the at least one processor to configure the UE to: determine one or more UCI bits to be multiplexed, the one or more UCI bits not corresponding with the UCI multiplexing; and calculate and store the starting boundary associated with each UL slot based on the one or more UCI bits; wherein the at least one bit of the plurality of rate matching output bits that is refrained from being allocated corresponds to an end of one or more slots of the plurality of UL slots).
Regarding claim 6, U.S. Patent No. 12,166,581 recites wherein the instructions configurable to be executed are further executable by the at least one processor to cause the UE to: wherein the slot length is calculated without storing the starting boundary associated with each UL slot; wherein the at least one bit of the plurality of rate matching output bits corresponds to an end of the plurality of UL slots (Claim 6, wherein the instructions are further executable by the at least one processor to configure the UE to: wherein the slot length is calculated without storing the starting boundary associated with each UL slot; wherein the at least one bit of the plurality of rate matching output bits that is refrained from being allocated corresponds to an end of the plurality of UL slots).
Regarding claim 7, U.S. Patent No. 12,166,581 recites wherein the instructions configurable to be executed are further executable by the at least one processor to cause the UE to: determine one or more UCI bits to be multiplexed, the one or more UCI bits not corresponding with the UCI multiplexing; and wherein the slot length is calculated without storing the starting boundary associated with each UL slot based on the one or more UCI bits; wherein the at least one bit of the plurality of rate matching output bits corresponds to an end of the plurality of UL slots (Claim 7, herein the instructions are further executable by the at least one processor to configure the UE to: determine one or more UCI bits to be multiplexed, the one or more UCI bits not corresponding with the UCI multiplexing; and wherein the slot length is calculated without storing the starting boundary associated with each UL slot based on the one or more UCI bits; wherein the at least one bit of the plurality of rate matching output bits that is refrained from being allocated corresponds to an end of the plurality of UL slots).
Regarding claim 8, U.S. Patent No. 12,166,581 recites wherein the instructions configurable to be executed are further executable by the at least one processor to cause the UE to: receive, from a base station, an indication of a physical uplink shared channel (PUSCH) configuration, wherein the PUSCH configuration is associated with the allocation of the one or more bits and the at least one bit (Claim 8, wherein the instructions are further executable by the at least one processor to configure the UE to: receive, from a base station, an indication of a physical uplink shared channel (PUSCH) configuration, wherein the PUSCH configuration is associated with the allocation of the one or more bits and the refrained allocation of the at least one bit).
Regarding claim 9, U.S. Patent No. 12,166,581 recites wherein each of the one or more bits is allocated for the modulation process in one or more resource elements (REs) (Claim 9, wherein each of the one or more bits is allocated for the modulation process in one or more resource elements (REs)).
Regarding claim 10, U.S. Patent No. 12,166,581 recites wherein the instructions configurable to be executed are further executable by the at least one processor to cause the UE to: determine whether the at least one bit of the plurality of rate matching output bits corresponds to UCI multiplexing (Claim 10, wherein the instructions are further executable by the at least one processor to configure the UE to: determine whether the at least one bit of the plurality of rate matching output bits corresponds to UCI multiplexing).
Regarding claim 11, U.S. Patent No. 12,166,581 recites wherein the at least one bit of the plurality of rate matching output bits corresponds to at least one unused physical uplink shared channel (PUSCH) bit (Claim 11, wherein the at least one bit of the plurality of rate matching output bits that is refrained from being allocated for the modulation process corresponds to at least one unused physical uplink shared channel (PUSCH) bit).
Regarding claim 12, U.S. Patent No. 12,166,581 recites wherein the UCI multiplexing is associated with one or more physical uplink control channel (PUCCH) acknowledgment or non-acknowledgment bits (Claim 12, wherein the UCI multiplexing is associated one or more physical uplink control channel (PUCCH) acknowledgment or non-acknowledgment bits).
Regarding claim 13, U.S. Patent No. 12,166,581 recites wherein the instructions configurable to be executed are further executable by the at least one processor to cause the UE to: calculate a first starting boundary for at least one subsequent slot of the plurality of UL slots based on the at least one bit of the plurality of rate matching output bits (Claim 13, wherein the instructions are further executable by the at least one processor to configure the UE to: calculate a first starting boundary for at least one subsequent slot of the plurality of UL slots based on the at least one bit of the plurality of rate matching output bits that is refrained from being allocated for the modulation process).
Regarding claim 14, U.S. Patent No. 12,166,581 recites wherein the starting boundary for the at least one subsequent slot is calculated without accounting for UCI multiplexing (Claim 14, wherein the starting boundary for the at least one subsequent slot is calculated without accounting for UCI multiplexing).
Regarding claim 15, U.S. Patent No. 12,166,581 recites wherein the calculation of the starting boundary for the at least one subsequent slot is pre-calculated or predetermined (Claim 15, wherein the calculation of the starting boundary for the at least one subsequent slot is pre-calculated or predetermined).
Regarding claim 16, U.S. Patent No. 12,166,581 recites wherein the instructions configurable to be executed are further executable by the at least one processor to cause the UE to: transmit, to a base station, an UL transmission based on the allocated one or more bits and the at least one bit (Claim 17, wherein the instructions are further executable by the at least one processor to configure the UE to: transmit, to a base station, an UL transmission based on the allocated one or more bits and the at least one bit that is refrained from being allocated).
Regarding claim 17, U.S. Patent No. 12,166,581 recites a transceiver coupled to the at least one processor (Claim 18, a transceiver coupled to the at least one processor).
Regarding claim 18, U.S. Patent No. 12,166,581 recites an apparatus for wireless communication at a network entity, comprising (Claim 19, An apparatus for wireless communication at a network entity, comprising):
one or more memories (Claim 19, a memory); and
at least one processor coupled to the one or more memories, the one or more memories storing instructions configurable to be executable by the at least one processor to cause the apparatus to (Claim 19, at least one processor coupled to the memory, the memory storing instructions executable by the at least one processor to configure the apparatus to):
transmit an indication of a physical uplink shared channel (PUSCH) configuration for a user equipment (UE), the PUSCH configuration being associated with an allocation of a plurality of rate matching output bits for a modulation process, a slot length for each UL slot of a plurality of UL slots being associated with the plurality of rate matching output bits, each UL slot including a starting point for the plurality of rate matching output bits, the slot length for each UL slot being associated with a starting boundary, the plurality of UL slots being associated with at least one of a single transport block (TB) or a single rate matching (Claim 19, transmit an indication of a physical uplink shared channel (PUSCH) configuration for a user equipment (UE), the PUSCH configuration being associated with an allocation of a plurality of rate matching output bits for a modulation process, a slot length for each UL slot of a plurality of UL slots being associated with the plurality of rate matching output bits, each UL slot including a starting point for the plurality of rate matching output bits, the slot length for each UL slot being associated with a starting boundary, the plurality of UL slots being associated with at least one of a single transport block (TB) or a single rate matching); and
receive an UL transmission based on an allocation of one or more bits of the plurality of rate matching output bits and on at least one bit of the plurality of rate matching output bits that is associated with uplink control information (UCI) multiplexing wherein PUSCH data in the at least one bit is overwritten with UCI multiplexing data (Claim 19, receive an UL transmission based on a first allocation of one or more bits of the plurality of rate matching output bits and a refrained allocation of at least one bit of the plurality of rate matching output bits, the at least one bit associated with uplink control information (UCI) multiplexing; Claims 1 and 16, configure the UE to refrain from allocating the at least one bit by: writing physical uplink shared channel (PUSCH) data in the at least one bit; and overwriting UCI multiplexing data in the at least one bit; Claim 23, wherein the at least one bit that is skipped being allocated for the modulation process corresponds to at least one unused physical uplink shared channel (PUSCH) bit).
Regarding claim 19, U.S. Patent No. 12,166,581 wherein the plurality of rate matching output bits corresponds to a rate matching output size (Claim 20, wherein the plurality of rate matching output bits corresponds to a rate matching output size).
Regarding claim 20, U.S. Patent No. 12,166,581 recites wherein the single TB corresponds to a TB over multiple slots (TBoMS) (Claim 21, wherein the single TB corresponds to a TB over multiple slots (TBoMS)).
Regarding claim 21, U.S. Patent No. 12,166,581 recites wherein each of the one or more bits is allocated for the modulation process in one or more resource elements (REs) (Claim 22, wherein each of the one or more bits is allocated for the modulation process in one or more resource elements (REs)).
Regarding claim 22, U.S. Patent No. 12,166,581 recites wherein the UCI multiplexing is associated with one or more physical uplink control channel (PUCCH) acknowledgment or non-acknowledgment bits (Claim 24, wherein the UCI multiplexing is associated one or more physical uplink control channel (PUCCH) acknowledgment or non-acknowledgment bits).
Regarding claim 23, U.S. Patent No. 12,166,581 recites wherein the starting boundary for at least one subsequent slot of the plurality of UL slots is calculated without accounting for UCI multiplexing and based on the at least one bit that is skipped being allocated for the modulation process (Claim 25, wherein the starting boundary for at least one subsequent slot of the plurality of UL slots is calculated without accounting for UCI multiplexing and based on the at least one bit that is skipped being allocated for the modulation process).
Regarding claim 24, U.S. Patent No. 12,166,581 recites an antenna or a transceiver coupled to the at least one processor (Claim 26, an antenna or a transceiver coupled to the at least one processor).
Regarding claim 25, U.S. Patent No. 12,166,581 recites a method of wireless communication at a user equipment (UE), comprising (Claim 27, A method of wireless communication at a user equipment (UE), comprising):
calculating a slot length for each uplink (UL) slot of a plurality of UL slots, the slot length for each UL slot being associated with a plurality of rate matching output bits, each UL slot including a starting point for the plurality of rate matching output bits, the slot length for each UL slot being associated with a starting boundary, the plurality of UL slots being associated with at least one of a single transport block (TB) or a single rate matching (Claim 27, calculating a slot length for each uplink (UL) slot of a plurality of UL slots, the slot length for each UL slot being associated with a plurality of rate matching output bits, each UL slot including a starting point for the plurality of rate matching output bits, the slot length for each UL slot being associated with a starting boundary, the plurality of UL slots being associated with at least one of a single transport block (TB) or a single rate matching);
allocating one or more bits of the plurality of rate matching output bits for a modulation process (Claim 27, allocating one or more bits of the plurality of rate matching output bits for a modulation process);
writing physical uplink shared channel (PUSCH) data in at least one bit of the plurality of rate matching output bits, the at least one bit corresponding to uplink control information (UCI) multiplexing (Claim 27, refraining from allocating at least one bit of the plurality of rate matching output bits for the modulation process, the at least one bit corresponding to uplink control information (UCI) multiplexing; Claims 1 and 16, configure the UE to refrain from allocating the at least one bit by: writing physical uplink shared channel (PUSCH) data in the at least one bit; and overwriting UCI multiplexing data in the at least one bit); and
overwriting the PUSCH data with UCI multiplexing data in the at least one bit (Claim 27, refraining from allocating at least one bit of the plurality of rate matching output bits for the modulation process, the at least one bit corresponding to uplink control information (UCI) multiplexing; Claims 1 and 16, refrain from allocating the at least one bit by…and overwriting UCI multiplexing data in the at least one bit).
Regarding claim 26, U.S. Patent No. 12,166,581 recites storing the starting boundary associated with each UL slot; wherein the at least one bit of the plurality of rate matching output bits corresponds to an end of one or more slots of the plurality of UL slots (Claim 28, storing the starting boundary associated with each UL slot; wherein the at least one bit of the plurality of rate matching output bits that is refrained from being allocated corresponds to an end of one or more slots of the plurality of UL slots).
Regarding claim 27, U.S. Patent No. 12,166,581 recites wherein the single TB corresponds to a TB over multiple slots (TBoMS) (Claim 29, wherein the single TB corresponds to a TB over multiple slots (TBoMS)).
Regarding claim 28, U.S. Patent No. 12,166,581 recites a method for wireless communication at a network entity, comprising (Claim 30, A method for wireless communication at a network entity, comprising):
transmitting an indication of a physical uplink shared channel (PUSCH) configuration for a user equipment (UE), the PUSCH configuration being associated with an allocation of a plurality of rate matching output bits for a modulation process, a slot length for each UL slot of a plurality of UL slots being associated with the plurality of rate matching output bits, each UL slot including a starting point for the plurality of rate matching output bits, the slot length for each UL slot being associated with a starting boundary, the plurality of UL slots being associated with at least one of a single transport block (TB) or a single rate matching (Claim 30, transmitting an indication of a physical uplink shared channel (PUSCH) configuration for a user equipment (UE), the PUSCH configuration being associated with an allocation of a plurality of rate matching output bits for a modulation process, a slot length for each UL slot of a plurality of UL slots being associated with the plurality of rate matching output bits, each UL slot including a starting point for the plurality of rate matching output bits, the slot length for each UL slot being associated with a starting boundary, the plurality of UL slots being associated with at least one of a single transport block (TB) or a single rate matching); and
receive an UL transmission based on an allocation of one or more bits of the plurality of rate matching output bits and on at least one bit of the plurality of rate matching output bits that is associated with uplink control information (UCI) multiplexing wherein PUSCH data in the at least one bit is overwritten with UCI multiplexing data (Claim 30, receiving an UL transmission based on a first allocation of one or more bits of the plurality of rate matching output bits and a refrained allocation of at least one bit of the plurality of rate matching output bits, the at least one bit associated with uplink control information (UCI) multiplexing; Claims 1 and 16, configure the UE to refrain from allocating the at least one bit by: writing physical uplink shared channel (PUSCH) data in the at least one bit; and overwriting UCI multiplexing data in the at least one bit).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yang et al. (US 2015/0341923) disclose PUSCH skipping/omitting with only UCI PUCCH being transmitted at paragraph 258 with rate-matching applied to PUSCH (Paragraph 80).
Park et al. (US 2019/0037586) disclose PUSCH scheduling without considering PUCCH transmission, prioritizing PUCCH over PUSCH transmission, and when performing UCI piggyback on the PUSCH without UCI transmission processing time guarantee, transmitting only the UCI on the PUCCH and omitting the PUSCH transmission (Paragraph 679) with rate-matching/puncturing applied on the PUSCH (Paragraphs 436-444).
Talarico et al. (US 2021/0007129) disclose PUSCH dropping with slot puncturing at paragraph 38.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OTIS L THOMPSON, JR whose telephone number is (571)270-1953. The examiner can normally be reached Monday - Friday, 6:30am - 7:00pm.
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/OTIS L THOMPSON, JR/Primary Examiner, Art Unit 2477
September 28, 2026
