DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kearney (US 9,160,356 B1 hereinafter “Kearney”) in view of van Engelen (US 7,042,375 B1 hereinafter “van Engelen”).
As to claim 1, Kearney discloses in Figs. 2, 3, and 6: a measuring circuit for measuring a characteristic of a resonator-based loop filter included in a delta-sigma (DS) analog-to-digital converter (ADC) (receiver 10 of Fig. 2; CT-ΔΣ ADC of Fig. 3; resonator-based loop filter formed by first integrator 24, second integrator 26, and extra feedback path 34; “the NTF zeros are shifted from their default position at DC by inserting an extra feedback path 34 with a programmable gain feedback component (gain) ‘−g’ from the output of the second integrator 26 to the input of the first integrator 24”, col. 3, lines 1-30), comprising:
a tone generator circuit, configured to generate a tone, and inject the tone to the DS ADC that is offline (controller 22 of Fig. 2 generating Tune_wav<2:0>; injection at active summer 28 of Fig. 3 at the input of ADC quantizer 30; offline by Sel_i of Fig. 3; “Tune_wav<lt;2:0>; is an 8-level (3 bit) synthesized quasi-sinusoidal calibration signal injected via the active summer 28 at the input to the ADC quantizer 30”; “Sel_i disconnects the ADC inputs in_i — 0 and in_i — 1 from the IF front end of the receiver, so decoupling the ADC from any RF signal input during calibration”; col. 3, lines 35-55); and
a digital signal processing circuit, configured to process a digital output of the DS ADC with the tone injected, to generate a measurement result of the resonator-based loop filter (controller 22 of Fig. 2 processing output out_i of Fig. 3; Fig. 6; “the controller 22 performs a Discrete Fourier Transform (DFT) of the output signal for the ADC being calibrated”; “The tune<3:0>; value (code) which provides the minimal IF DFT power (signal strength) can then be chosen”; col. 4, lines 45-60).
Kearney does not disclose a dither tone or a Q-factor measurement result.
However, van Engelen discloses a dither tone and processing the digital output with the dither injected to generate a Q-factor measurement result:
“A known dither signal is used, for example a digital dither signal.”
“Through adding of the dither to the modulator loop, the digital output of the sigma delta modulator ADC contains a filtered version of the digital dither. This signal can be used to reveal characteristics of the modulator-loop, including characteristics of a continuous-time filter in the modulator.”
“tune it to an application specific correct frequency, gain or bandwidth, etc.”
(analog dither 122 of Fig. 1; digital dither 128 of Fig. 1; dither device 238 and digital dither 242 of Fig. 2; digital output 216/216′ of Fig. 2; signal processing device 350 of Fig. 3; adaptive filter 452 of Fig. 4).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Kearney and implement the missing element exactly as recited, as taught by van Engelen, for generating and injecting a dither tone, and for generating a Q-factor measurement result, because van Engelen teaches that a known dither appearing in the digital output reveals the continuous-time loop-filter response, including bandwidth, and bandwidth of resonator 24/26/34 is the Q-factor.
As to claim 2, Kearney discloses in Figs. 2 and 3: the DS ADC is a continuous-time DS ADC (“an continuous time-delta sigma (CT-ΔΣ) analog-to-digital converter (ADC)”; Fig. 3 “2 nd -order low-pass CT-AZ ADC” comprising integrators 24, 26, active summer 28, ADC quantizer 30, and IDAC 32).
As to claim 3, Kearney discloses in Fig. 2 an IF receiver with bandpass analog filter FILT and an NTF notch at IF (“real bandpass analog filter (FILT)”; “Placing the NTF notch at f IF”).
Kearney does not disclose the DS ADC is a band-pass ADC.
However, van Engelen discloses the DS ADC is a band-pass ADC:
“A sigma delta (ΣΔ) modulator ADC (e.g., a band pass sigma delta modulator) is particularly suited for converting narrow-band signals (e.g., narrow-band frequency signals) from analog to digital.”
“In the case of a bandpass modulator ADC, this means that the “tuning frequency” in which the bandpass filter G has a high gain can vary significantly.”
(modulator 102 and analog filter 104 of Fig. 1; analog filter 204 of Fig. 2).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Kearney and implement the missing element exactly as recited, as taught by van Engelen, for making the DS ADC a band-pass ADC, because van Engelen teaches that a band pass sigma delta modulator is used for narrow-band conversion and that its analog loop filter is the filter identified from the digital output after dither injection.
As to claim 4, Kearney discloses in Fig. 2: digital processing of the ADC output including down sampling and conversion to baseband (block 20; “further digital filtering, down sampling and conversion to baseband within block 20”).
Kearney does not disclose that the digital signal processing circuit comprises a digital down-conversion (DDC) circuit and a decimation filter.
However, van Engelen discloses digital processing of the modulator output by filters operating on digital output 216 (first bandpass filter 564 and second bandpass filter 566 of Fig. 5; signal processing device 350 of Fig. 3).
Kearney’s block 20 already performs “digital filtering, down sampling and conversion to baseband.”
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Kearney and implement the missing element exactly as recited, as taught by the combination, for providing a digital down-conversion (DDC) circuit and a decimation filter, because Kearney already converts the digital output to baseband after down sampling in block 20, which is a DDC and a decimation filter.
As to claim 5, Kearney discloses in Fig. 3: the DS ADC is a low-pass ADC (“FIG. 3 shows in more detail an example 2 nd -order low-pass CT-AZ ADC”, col3, line 7-30).
As to claim 6, Kearney discloses in Fig. 2: the digital signal processing circuit comprises a decimation filter (block 20; “further digital filtering, down sampling and conversion to baseband within block 20”, col. 3, lines 1-7)).
As to claim 7, Kearney discloses in controller 22 of Fig. 2:
the digital signal processing circuit comprises a fast Fourier transform (FFT) circuit (“the controller 22 performs a Discrete Fourier Transform (DFT) of the output signal for the ADC being calibrated”; “measure the DFT bin at IF frequency”).
As to claim 8, Kearney discloses Tune_wav<;2:0>; generated by controller 22 of Fig. 2.
Kearney does not disclose the dither tone is a digital tone.
However, van Engelen discloses the dither tone is a digital tone:
“A known dither signal is used, for example a digital dither signal.”
“a digital dither signal 128 may be added to an output signal 130 of ADC 106 to result in a digital output 116 of modulator 102.”
(digital dither 128 of Fig. 1; digital dither 242 of Fig. 2).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Kearney and implement the missing element exactly as recited, as taught by van Engelen, for making the dither tone a digital tone, because van Engelen teaches a digital dither signal added in the modulator so that the digital output contains a filtered version of the digital dither.
As to claim 9, Kearney injects Tune_wav<2:0>; at analog active summer 28 of Fig. 3.
Kearney does not disclose the dither tone is an analog tone.
However, van Engelen discloses the dither tone is an analog tone:
“an analog dither 122 is added to filtered error signal 120 resulting in an input signal 124 that is input to ADC 106.” (analog dither 122 of Fig. 1).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Kearney and implement the missing element exactly as recited, as taught by van Engelen, for making the dither tone an analog tone, because van Engelen teaches analog dither 122 added before ADC 106.
As to claim 10, Kearney discloses in Fig. 3: the dither tone is injected to an input node of a quantizer included in the DS ADC (active summer 28 at the input of ADC quantizer 30; “Tune_wav<2:0>; is an 8-level (3 bit) synthesized quasi-sinusoidal calibration signal injected via the active summer 28 at the input to the ADC quantizer 30”; “By injecting this calibration signal at the input to the ADC quantizer 30, it can experience approximately the same transfer function as the ADC quantization noise—i.e. the NTF”).
As to claim 11, Kearney discloses injection at the input of ADC quantizer 30 via active summer 28 of Fig. 3.
Kearney does not disclose the dither tone is injected to an internal node of a quantizer included in the DS ADC.
However, van Engelen discloses injection immediately before the quantizer and immediately after the quantizer:
“an analog dither 122 is added to filtered error signal 120 resulting in an input signal 124 that is input to ADC 106.”
“a digital dither signal 128 may be added to an output signal 130 of ADC 106 to result in a digital output 116 of modulator 102.”
“signal 128 must conform to a signal that is inserted into modulator 102 and has an effect on modulator output 116, such that sufficient information about the modulator noise transfer function or loopfilter can be obtained.” (analog dither 122, ADC 106, output signal 130, and digital dither 128 of Fig. 1).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Kearney and implement the missing element exactly as recited, as taught by van Engelen, for injecting the dither tone to an internal node of a quantizer, because van Engelen teaches insertion of dither at the input of ADC 106 and at output signal 130 of ADC 106, and an internal node of the quantizer is between those two disclosed nodes while still affecting modulator output 116.
As to claim 12, Kearney discloses injection at the input of ADC quantizer 30 of Fig. 3.
Kearney does not disclose the dither tone is injected to an output node of a quantizer included in the DS ADC.
However, van Engelen discloses the dither tone is injected to an output node of a quantizer included in the DS ADC:
“a digital dither signal 128 may be added to an output signal 130 of ADC 106 to result in a digital output 116 of modulator 102.” (ADC 106, output signal 130, digital dither 128, and digital output 116 of Fig. 1).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Kearney and implement the missing element exactly as recited, as taught by van Engelen, for injecting the dither tone to an output node of a quantizer, because van Engelen teaches digital dither 128 added to output signal 130 of ADC 106.
As to claim 13, Kearney discloses in Figs. 3 and 6 measuring output power of injected Tune_wav versus frequency (“FIG. 6 shows the ADC output power when a calibration tone, Tune_wav, is injected”; “exhaustive, linear, binary or successive approximation search algorithm”).
Kearney does not disclose the dither tone generator circuit is configured to inject the dither tone from a start tone frequency to a stop tone frequency for a frequency sweep test; and the Q-factor measurement result comprises a plurality of measurement results obtained for a plurality of different tone frequencies of the dither tone, respectively.
However, van Engelen discloses measurements of the digital output at a plurality of different frequencies:
“FIG. 5 shows a system using two passband filters to filter modulator output 216 (or 216 ′) at frequencies above and below the frequency band of interest”
“First bandpass filter 564 filters modulator signal 216 (or processed signal 216 ′) using a passband defined by fc+ΔF.”
“second bandpass filter 566 filters modulator signal 216 (or processed signal 216 ′) using a passband centered at fc-ΔF.”
“an energy value of dither signal 242 within these two signals 554-1 and 554-2 is determined.”
(first bandpass filter 564, second bandpass filter 566, filter signals 554-1 and 554-2, dither signal 242, and controller 352 of Fig. 5).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Kearney and implement the missing element exactly as recited, as taught by van Engelen, for injecting the dither tone from a start tone frequency to a stop tone frequency for a frequency sweep test and obtaining a plurality of measurement results for a plurality of different tone frequencies, because van Engelen measures dither energy in digital output 216 at a plurality of frequencies fc+ΔF and fc−ΔF, and Kearney already plots injected-tone power versus frequency in Fig. 6.
As to claim 14, Kearney discloses in Figs. 2, 3, 4, 5, and 6: a tuning system for tuning a characteristic of a resonator-based loop filter included in a delta-sigma (DS) analog-to-digital converter (ADC) (receiver 10 of Fig. 2; CT-ΔΣ ADC of Fig. 3; resonator-based loop filter formed by integrators 24, 26 and extra feedback path 34), comprising:
a measuring circuit, comprising:
a tone generator circuit, configured to generate a tone, and inject the tone to the DS ADC that is offline (controller 22 of Fig. 2; Tune_wav<2:0>; at active summer 28 / ADC quantizer 30 of Fig. 3; Sel_i of Fig. 3; “Tune_wav<2:0> is an 8-level (3 bit) synthesized quasi-sinusoidal calibration signal injected via the active summer 28 at the input to the ADC quantizer 30”; “Sel_i disconnects the ADC inputs in_i — 0 and in_i — 1 from the IF front end of the receiver, so decoupling the ADC from any RF signal input during calibration”); and
a digital signal processing circuit, configured to process a digital output of the DS ADC with the tone injected, to generate a measurement result of the resonator-based loop filter (controller 22 of Fig. 2; output out_i of Fig. 3; Fig. 6; “the controller 22 performs a Discrete Fourier Transform (DFT) of the output signal for the ADC being calibrated”); and
a control circuit, configured to adjust compensation of the resonator-based loop filter according to the measurement result (controller 22 of Fig. 2; tune<;3:0>; of Fig. 3 setting gain “−g” of extra feedback path 34; Figs. 4 and 5; “The position of the notch in the NTF of each ADC quantizer 30 is adjusted using a programmable value of a feedback parameter that sets the gain −g”; “Finding the particular value from 0 . . . 15 of tune<3:0>; which produces this minimum”).
Kearney does not disclose a dither tone, a Q-factor measurement result, or adjust Q-factor compensation.
However, van Engelen discloses those missing limitations:
“A known dither signal is used, for example a digital dither signal.”
“the digital output of the sigma delta modulator ADC contains a filtered version of the digital dither. This signal can be used to reveal characteristics of the modulator-loop, including characteristics of a continuous-time filter in the modulator.”
“tune it to an application specific correct frequency, gain or bandwidth, etc.”
“control signal 244 is used to adjust parameters of function G of analog filter 204 in modulator 202.” (analog dither 122 and digital dither 128 of Fig. 1; dither device 238 and digital dither 242 of Fig. 2; signal processing device 350 and controller 352 of Fig. 3; control signal 244 of Figs. 2–5; analog filter 204 of Fig. 2).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Kearney and implement the missing element exactly as recited, as taught by van Engelen, for using a dither tone, generating a Q-factor measurement result, and configuring the control circuit to adjust Q-factor compensation, because van Engelen teaches that controller 352 uses control signal 244 to adjust analog filter 204 from a dither-based measurement of frequency, gain, or bandwidth, and bandwidth adjustment of resonator 24/26/34 is Q-factor compensation.
As to claim 15, Kearney discloses in Fig. 6 ADC output power versus frequency for injected Tune_wav.
Kearney does not disclose the dither tone generator circuit is configured to inject the dither tone from a start tone frequency to a stop tone frequency for a frequency sweep test; and the Q measurement result comprises a plurality of measurement results obtained for a plurality of different tone frequencies of the dither tone, respectively.
However, van Engelen discloses a plurality of measurement results at a plurality of different frequencies:
“First bandpass filter 564 filters modulator signal 216 (or processed signal 216 ′) using a passband defined by fc+ΔF.”
“second bandpass filter 566 filters modulator signal 216 (or processed signal 216 ′) using a passband centered at fc-ΔF.”
“an energy value of dither signal 242 within these two signals 554-1 and 554-2 is determined.”
(first bandpass filter 564, second bandpass filter 566, and filter signals 554-1, 554-2 of Fig. 5).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Kearney and implement the missing element exactly as recited, as taught by van Engelen, for the same reasons set forth for claim 13.
As to claim 16, Kearney discloses adjusting tune<3:0> of Fig. 3 according to a minimized power measurement (“detect the value of said programmable gain feedback component when a signal strength is minimized”; “The tune<3:0>; value (code) which provides the minimal IF DFT power (signal strength) can then be chosen”).
Kearney does not disclose the control circuit is configured to adjust the Q-factor compensation of the resonator-based loop filter by comparing a local minimum among the plurality of measurement results and a measurement result obtained for a reference frequency, where the reference frequency is included in the plurality of different tone frequencies.
However, van Engelen discloses comparing measurement results at a reference frequency and at other frequencies:
“Here, fc is the desired center frequency of analog filter 204 in modulator 202 and the desired tuning frequency of the noise transfer function of modulator 202, and ΔF is the (positive) offset frequency of bandpass filter 564 with respect to fc.”
“an energy value of dither signal 242 within these two signals 554-1 and 554-2 is determined. If the energy value is substantially identical in both signals, then known analog filter 204 is tuned to the correct value fc. If the energy values are not substantially identical, then one value is higher than the other value, and control signal 244 is used to adjust the tuning frequency of analog filter 204 higher or lower towards the desired frequency fc.” (first bandpass filter 564, second bandpass filter 566, filter signals 554-1 and 554-2, controller 352, control signal 244, and analog filter 204 of Fig. 5).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Kearney and implement the missing element exactly as recited, as taught by van Engelen, for comparing a local minimum among the plurality of measurement results with a measurement result at a reference frequency, because van Engelen compares dither energy at offset frequencies with desired center frequency fc to generate control signal 244.
As to claim 19, Kearney discloses in Figs. 2 and 3 a continuous-time DS ADC (integrators 24, 26 of Fig. 3; “an continuous time-delta sigma (CT-ΔΣ) analog-to-digital converter (ADC)”).
Kearney does not disclose the DS ADC is a band-pass continuous-time DS ADC.
However, van Engelen discloses a band-pass continuous-time DS ADC:
“A sigma delta (ΣΔ) modulator ADC (e.g., a band pass sigma delta modulator) is particularly suited for converting narrow-band signals (e.g., narrow-band frequency signals) from analog to digital.”
“including characteristics of a continuous-time filter in the modulator.”
(modulator 102 and analog filter 104 of Fig. 1; analog filter 204 of Fig. 2).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Kearney and implement the missing element exactly as recited, as taught by van Engelen, for making the DS ADC a band-pass continuous-time DS ADC, for the same reasons set forth for claims 2 and 3.
As to claim 20, Kearney discloses in Figs. 2, 3, and 6: a method for measuring a characteristic of a resonator-based loop filter included in a delta-sigma (DS) analog-to-digital converter (ADC) (CT-ΔΣ ADC of Fig. 3; resonator-based loop filter formed by integrators 24, 26 and extra feedback path 34), comprising:
generating a tone and injecting the tone to the DS ADC that is offline (controller 22 of Fig. 2; Tune_wav<2:0> injected at active summer 28 / ADC quantizer 30 of Fig. 3; Sel_i of Fig. 3; “Tune_wav<2:0> is an 8-level (3 bit) synthesized quasi-sinusoidal calibration signal injected via the active summer 28 at the input to the ADC quantizer 30”; “Sel_i disconnects the ADC inputs in_i — 0 and in_i — 1 from the IF front end of the receiver, so decoupling the ADC from any RF signal input during calibration”); and
processing a digital output of the DS ADC with the tone injected, to generate a measurement result of the resonator-based loop filter (controller 22 of Fig. 2; output out_i of Fig. 3; Fig. 6; “the controller 22 performs a Discrete Fourier Transform (DFT) of the output signal for the ADC being calibrated”).
Kearney does not disclose generating a dither tone or generate a Q-factor measurement result.
However, van Engelen discloses those missing limitations:
“(a) producing a modulator digital output signal based on a received input analog signal and a dither signal;
(b) filtering the modulator digital output signal, such that a portion of the modulated digital output signal related to the dither signal is measurable;”
“the digital output of the sigma delta modulator ADC contains a filtered version of the digital dither. This signal can be used to reveal characteristics of the modulator-loop, including characteristics of a continuous-time filter in the modulator.”
“tune it to an application specific correct frequency, gain or bandwidth, etc.”
(analog dither 122 and digital dither 128 of Fig. 1; dither device 238 and digital dither 242 of Fig. 2; digital output 216/216′ of Fig. 2; method 600 of Fig. 6).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the method of Kearney and implement the missing element exactly as recited, as taught by van Engelen, for generating a dither tone and generating a Q-factor measurement result, because van Engelen teaches that the dither-related portion of digital output 216 measures the continuous-time loop-filter response, including bandwidth, which is the Q-factor of resonator 24/26/34.
Allowable Subject Matter
Claims 17-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 17-18, the prior art in record alone and/or in combination does not disclose the features of “ when a difference between the measurement result and the local minimum does not exceed a pre-defined threshold, the control circuit is configured to increase strength of the Q-factor compensation of the resonator-based loop filter, and the digital signal processing circuit is configured to process the digital output of the DS ADC with the dither tone injected, to generate another Q-factor measurement result of the resonator-based loop filter, as recited in claim 17; and the control circuit does not stop adjusting the Q-factor compensation of the resonator-based loop filter until a difference between the measurement result and the local minimum exceeds a pre-defined threshold”, as recited in the claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUNG X NGUYEN whose telephone number is (571)272-1967. The examiner can normally be reached 10:30am-6:30pm M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUNG X NGUYEN/Primary Examiner, Art Unit 2858 9/19/2026
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