DETAILED ACTION
Claims 1-20 are pending in this application.
Claims 8, 10, 18 and 20 are objected to.
Claims 1-7, 9, 11-17 and 19 are rejected.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/4/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 11-13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Greiner et al. (U.S. PGPub No. 2013/0339657) in view of Hashimoto et al. (U.S. PGPub No. 2015/0370726).
Claim 1
Greiner (2013/0339657) teaches:
A memory system, comprising:
[…] a controller configured to: P. 0253 and FIG. 1 Controller 120
manage validity of data written in the non-volatile memory, using a data map that includes at least a plurality of first tables and at least one second table, P. 0271 one or more of the translation tables (e.g., region tables, segment tables and/or page tables) are accessed
each of the plurality of first tables P. 0270 segment tables associated with segments including a first number of first entries, each of the first entries having information indicating the validity of data having a first size written in the non-volatile memory, P. 0126 invalid bit in the segment-table entry (STE); P. 0140 the STE contains a segment-frame absolute address (rather than a page-table origin) specifying the absolute storage location of the 1 M-byte block
the second table including a second number of second entries, each of the second entries having information indicating an address where each of the plurality of first tables is stored; and P. 0147-0149 a region-third-table entry (RTTE) has a segment-table origin when RTTE-format control is zero (see also P. 0085); P. 0073-75 a table origin field indicates an attached table entry of a next higher level
when all of first data written in the non-volatile memory are invalidated, the first data being data of which validity is managed in one of the plurality of first tables, set information indicating invalidity of the first data in one of the second entries of the second table that corresponds to the one of the plurality of first tables. P. 0131 setting the invalid bit in the region-third-table entry (RTTE) to zero (regions are 2G-byte blocks 0149, a region includes a plurality of segments 0153); P. 0152 INVALIDATE DAT TABLE ENTRY (IDTE) selectively clears TLB combined region and segment table entries when a segment-table entry is invalidated
Greiner does not explicitly teach a non-volatile memory device storing the data managed by the data map.
Hashimoto (2015/0370726) teaches:
[…] a non-volatile memory; and […] P. 0033 and FIG. 1 external memory 7 may be a nonvolatile memory device
[…] each of the plurality of first tables including a first number of first entries, […] P. 0489 page table T401-0 of level 2; FIG. 4 and P. 0188 tables T101-1 to T101-n of level 2 has entries E101-1-0 through E101-1-511
[…] the second table including a second number of second entries, P. 0186 and FIG. 4 highest-level page table T101 includes table entries E101-0 to E101-3 each of the second entries having information indicating an address where each of the plurality of first tables is stored; and P. 0186 Each table entry has an index for a page table of a subsequent level
when all of first data written in the non-volatile memory are invalidated, the first data being data of which validity is managed in one of the plurality of first tables, set information indicating invalidity of the first data in one of the second entries of the second table that corresponds to the one of the plurality of first tables. P. 0186 and FIG. 4 Each entry of highest-level page table T101 has a valid/invalid bit designating whether the page table of the subsequent level is valid/invalid
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Greiner with the non-volatile memory device storing the data managed by the data map taught by Hashimoto
The motivation being it is a well-known implementation of a memory device.
The systems of Greiner and Hashimoto are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Greiner with Hashimoto to obtain the invention as recited in claim 1.
Claim 2
Hashimoto (2015/0370726) teaches:
The memory system according to claim 1, wherein the at least one second table is one of a plurality of second tables, the data map includes the plurality of second tables and further at least one third table, FIG. 4 and P. 0187 page tables T101, T101-1 and T101-0; P. 0489 page table T401-0-0 of level 3
the third table including a third number of third entries, FIG. 4 and P. 0188 Table entries E101-1-0 to E101-1-511 in page table T101-1-0 of level 3 each of the third entries having information indicating an address where each of the plurality of second tables is stored, and P. 0186 Each table entry has an index for a page table of a subsequent level
Greiner (2013/0339657) teaches:
the controller is further configured to: when all of second data written in the non-volatile memory are invalidated, the second data being data of which validity is managed in two or more of the plurality of first tables, addresses where the two or more of the plurality of first tables are stored are managed in one of the plurality of second tables, set information indicating invalidity of the second data in one of the third entries of the third table that corresponds to the one of the plurality of second tables. P. 0129 program should set the invalid bit to one in the page-table entry, and clear all entries in all TLBs; P. 0050 the page table is designated by an attached and valid segment-table entry; P. 0064 the term "current level" refers to the level of translation table (region first table, region second table, region third table, segment table, or page table)
Claim 3
Hashimoto (2015/0370726) teaches:
The memory system according to claim 1, further comprising: a volatile memory, P. 0143 internal memory 8; P. 0040 is a storage device in a processor package (it is well-known in the art to have integrated memory to be volatile)
wherein the controller is further configured to: store the plurality of first tables and the second table in the volatile memory to manage the validity of data written in the non-volatile memory; and P. 0042 internal memory 8 stores a secure page table tree 121
upon setting the information indicating the invalidity of the first data in the one of the second entries of the second table, discard the one of the plurality of first tables from the volatile memory. P. 0186 and FIG. 4 Each entry of highest-level page table T101 has a valid/invalid bit designating whether the page table of the subsequent level is valid/invalid; P. 0071 the update unit 6 sets the parent entry pe1 in the parent table 101 invalid when the secure page table tree 121 does not include the child table 201
Claim 5
Hashimoto (2015/0370726) teaches:
The memory system according to claim 1, further comprising: a volatile memory, wherein the controller is further configured to store at least one of the plurality of first tables in the volatile memory, and P. 0040 and FIG. 1 the internal memory 8 is a storage device in a processor package (it is well-known in the art that integrated memory is typically volatile memory); P. 0046 child table 201 is copied from the external memory 7 to the internal memory 8
each of the second entries has information that indicates whether each of the plurality of first tables is stored in the volatile memory or in the non-volatile memory. P. 0054-55 parent entry pe1 in the parent table 107 refers to the child table 201 included in the page table tree 9 in the external memory 7. The update unit 6 updates the parent entry pe1 to be updated in the parent table 101 in the secure page table tree 121 to cause it to refer to the child table 201 included in the secure page table tree 121 in the internal memory 8; P. 0065-66 all data and tables related to an address that are valid are arranged in internal memory; P. 0071 sets the parent entry pe1 in the parent table 101 invalid when the secure page table tree 121 does not include the child table 201 (See Also P. 0080)
Claim 11
Greiner (2013/0339657) teaches:
A method of controlling a […] memory, comprising: managing validity of data written in the non-volatile memory, using a data map that includes at least a plurality of first tables and at least one second table, P. 0271 one or more of the translation tables (e.g., region tables, segment tables and/or page tables) are accessed
each of the plurality of first tables P. 0270 segment tables associated with segments including a first number of first entries, each of the first entries having information indicating the validity of data having a first size written in the non-volatile memory, P. 0126 invalid bit in the segment-table entry (STE); P. 0140 the STE contains a segment-frame absolute address (rather than a page-table origin) specifying the absolute storage location of the 1 M-byte block
the second table including a second number of second entries, each of the second entries having information indicating an address where each of the plurality of first tables is stored; P. 0147-0149 a region-third-table entry (RTTE) has a segment-table origin when RTTE-format control is zero (see also P. 0085); P. 0073-75 a table origin field indicates an attached table entry of a next higher level
determining that all of first data written in the non-volatile memory are invalidated, the first data being data of which validity is managed in one of the plurality of first tables; and P. 0289 utilize the M4 field 0402 to determine whether to selectively clear the TLBs of all CPUs
in response to determining that all of the first data written in the non-volatile memory are invalidated, setting information indicating invalidity of the first data in one of the second entries of the second table that corresponds to the one of the plurality of first tables. P. 0131 setting the invalid bit in the region-third-table entry (RTTE) to zero (regions are 2G-byte blocks 0149, a region includes a plurality of segments 0153); P. 0152 INVALIDATE DAT TABLE ENTRY (IDTE) selectively clears TLB combined region and segment table entries when a segment-table entry is invalidated
Greiner does not explicitly teach a non-volatile memory device storing the data managed by the data map.
Hashimoto (2015/0370726) teaches:
A method of controlling a non-volatile memory, […] P. 0033 and FIG. 1 external memory 7 may be a nonvolatile memory device
[…] each of the plurality of first tables including a first number of first entries, […] P. 0489 page table T401-0 of level 2; FIG. 4 and P. 0188 tables T101-1 to T101-n of level 2 has entries E101-1-0 through E101-1-511
[…] the second table including a second number of second entries, P. 0186 and FIG. 4 highest-level page table T101 includes table entries E101-0 to E101-3 each of the second entries having information indicating an address where each of the plurality of first tables is stored; P. 0186 Each table entry has an index for a page table of a subsequent level
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Greiner with the non-volatile memory device storing the data managed by the data map taught by Hashimoto
The motivation being it is a well-known implementation of a memory device.
The systems of Greiner and Hashimoto are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Greiner with Hashimoto to obtain the invention as recited in claim 11.
Claim 12
Hashimoto (2015/0370726) teaches:
The method according to claim 11, wherein the at least one second table is one of a plurality of second tables, the data map includes the plurality of second tables and further at least one third table, FIG. 4 and P. 0187 page tables T101, T101-1 and T101-0; P. 0489 page table T401-0-0 of level 3
the third table including a third number of third entries, FIG. 4 and P. 0188 Table entries E101-1-0 to E101-1-511 in page table T101-1-0 of level 3 each of the third entries having information indicating an address where each of the plurality of second tables is stored, and P. 0186 Each table entry has an index for a page table of a subsequent level
Greiner (2013/0339657) teaches:
the method further comprises: determining that all of second data written in the non-volatile memory are invalidated, the second data being data of which validity is managed in two or more of the plurality of first tables, addresses where the two or more of the plurality of first tables are stored are managed in one of the plurality of second tables; P. 0289 utilize the M4 field 0402 to determine whether to selectively clear the TLBs of all CPUs
in response to determining that all of the second data written in the non-volatile memory are invalidated, setting information indicating invalidity of the second data in one of the third entries of the third table that corresponds to the one of the plurality of second tables. P. 0129 program should set the invalid bit to one in the page-table entry, and clear all entries in all TLBs; P. 0050 the page table is designated by an attached and valid segment-table entry; P. 0064 the term "current level" refers to the level of translation table (region first table, region second table, region third table, segment table, or page table)
Claim 13
Hashimoto (2015/0370726) teaches:
The method according to claim 11, further comprising: storing the plurality of first tables and the second table in a volatile memory to manage the validity of data written in the non-volatile memory; and P. 0143 internal memory 8; P. 0040 is a storage device in a processor package (it is well-known in the art to have integrated memory to be volatile); P. 0042 internal memory 8 stores a secure page table tree 121
upon setting the information indicating the invalidity of the first data in the one of the second entries of the second table, discarding the one of the plurality of first tables from the volatile memory. P. 0186 and FIG. 4 Each entry of highest-level page table T101 has a valid/invalid bit designating whether the page table of the subsequent level is valid/invalid; P. 0071 the update unit 6 sets the parent entry pe1 in the parent table 101 invalid when the secure page table tree 121 does not include the child table 201
Claim 15
Hashimoto (2015/0370726) teaches:
The method according to claim 11, further comprising: storing at least one of the plurality of first tables in a volatile memory, P. 0040 and FIG. 1 the internal memory 8 is a storage device in a processor package (it is well-known in the art that integrated memory is typically volatile memory)
wherein each of the second entries has information that indicates whether each of the plurality of first tables is stored in the volatile memory or in the non-volatile memory. P. 0054-55 parent entry pe1 in the parent table 107 refers to the child table 201 included in the page table tree 9 in the external memory 7. The update unit 6 updates the parent entry pe1 to be updated in the parent table 101 in the secure page table tree 121 to cause it to refer to the child table 201 included in the secure page table tree 121 in the internal memory 8; P. 0065-66 all data and tables related to an address that are valid are arranged in internal memory; P. 0071 sets the parent entry pe1 in the parent table 101 invalid when the secure page table tree 121 does not include the child table 201 (See Also P. 0080)
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Greiner et al. (U.S. PGPub No. 2013/0339657) in view of Hashimoto et al. (U.S. PGPub No. 2015/0370726) in view of Asbe et al. (U.S. PGPub No. 2019/0004883).
Claim 4
Hashimoto (2015/0370726) teaches:
The memory system according to claim 3, wherein the controller is further configured to: when all of third data written in the non-volatile memory are valid, the third data being data of which validity is managed in another one of the plurality of first tables, set information indicating validity of the third data in another one of the second entries of the second table that corresponds to said another one of the plurality of first tables; and P. 0186 and FIG. 4 Each entry of highest-level page table T101 has a valid/invalid bit designating whether the page table of the subsequent level is valid/invalid; P. 0071 sets the parent entry pe1 in the parent table 101 valid when the child table 201 is incorporated in the secure page table tree 121
The systems of Greiner and Hashimoto do not explicitly state the second fragment table
collectively managing validity for a range of physical addresses when the validity for the physical
addresses are common.
Asbe (2019/0004883) teaches:
upon setting the information indicating the validity of the third data in said another one of the second entries of the second table, discard said another one of the plurality of first tables from the volatile memory. P. 0027 Once all the page table entries of L3 page table are mapped [analogous to common validity] MMU 202 determines that the mappings represented by the L3 page table 206(2) [first fragment table] should be consolidated into the single page table entry 210(1) of the L2 page table 206(1) [second fragment table], which currently stores a pointer to the L3 page table 206(2)
It would have been obvious to a person with ordinary skill in the art at the effective filing
date of the application to include the invention of Greiner and Hashimoto with the second fragment table collectively managing validity for a range of physical addresses when the validity for the physical addresses are common taught by Asbe
The motivation being freeing memory for other uses by the processor-based system
(see Asbe P. 0003)
The systems of Greiner, Hashimoto and Asbe are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Greiner and Hashimoto with Asbe to obtain the invention as recited in claim 4.
Claim 14
Hashimoto (2015/0370726) teaches:
The method according to claim 13, further comprising: determining that all of third data written in the non-volatile memory are valid, the third data being data of which validity is managed in another one of the plurality of first tables; in response to determining that all of the third data written in the non-volatile memory are valid, setting information indicating validity of the third data in another one of the second entries of the second table that corresponds to said another one of the plurality of first tables; and P. 0186 and FIG. 4 Each entry of highest-level page table T101 has a valid/invalid bit designating whether the page table of the subsequent level is valid/invalid; P. 0071 sets the parent entry pe1 in the parent table 101 valid when the child table 201 is incorporated in the secure page table tree 121
The systems of Greiner and Hashimoto do not explicitly state the second fragment table
collectively managing validity for a range of physical addresses when the validity for the physical
addresses are common.
Asbe (2019/0004883) teaches:
upon setting the information indicating the validity of the third data in said another one of the second entries of the second table, discarding said another one of the plurality of first tables from the volatile memory. P. 0027 Once all the page table entries of L3 page table are mapped [analogous to common validity] MMU 202 determines that the mappings represented by the L3 page table 206(2) [first fragment table] should be consolidated into the single page table entry 210(1) of the L2 page table 206(1) [second fragment table], which currently stores a pointer to the L3 page table 206(2)
It would have been obvious to a person with ordinary skill in the art at the effective filing
date of the application to include the invention of Greiner and Hashimoto with the second fragment table collectively managing validity for a range of physical addresses when the validity for the physical addresses are common taught by Asbe
The motivation being freeing memory for other uses by the processor-based system
(see Asbe P. 0003)
The systems of Greiner, Hashimoto and Asbe are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Greiner and Hashimoto with Asbe to obtain the invention as recited in claim 14.
Claim(s) 6-7, 9, 16-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Greiner et al. (U.S. PGPub No. 2013/0339657) in view of Hashimoto et al. (U.S. PGPub No. 2015/0370726) in view of Cohen et al. (U.S. PGPub No. 2014/0047210).
Claim 6
Greiner (2013/0339657) teaches:
when the second range is larger than or equal to the first range, set the information indicating the invalidity of the first data in the one of the second entries of the second table. P. 0152 INVALIDATE DAT TABLE ENTRY (IDTE) selectively clears TLB combined region and segment table entries when a segment-table entry is invalidated; P. 0157 a range of entries beginning with the designated entry, is invalidated; P. 0153 During execution of an IDTE instruction, a specified portion of virtual storage is invalidated. As examples, a segment of storage, which includes a plurality of pages of storage, or a region of storage, which includes a plurality of segments of storage, is selected to be invalidated
The systems of Greiner and Hashimoto do not explicitly state determining the units of data corresponding to an invalidation request.
Cohen (2014/0047210) teaches:
The memory system according to claim 1, wherein each of the plurality of first tables corresponds to a first range of physical addresses of the non-volatile memory, and the controller is further configured to: P. 0030 “TRIM” command enables host device 180 to designate blocks of previously saved data as unneeded or invalid
receive a first invalidation request from a host; P. 0030 During a delete operation, the OS sends a TRIM command specifying one or more ranges of Logical Block Addresses (LBAs)
determine a second range of physical addresses of the non-volatile memory where fourth data is stored, the fourth data being data to be invalidated in response to the first invalidation request and including at least the first data; and P. 0048 when a TRIM command having a trim range is processed, determines whether there are partial SLM pages at the start or end of the TRIM range; P. 0044 the size values are subtracted from the BUS count of corresponding regions when SSD 101 performs a TRIM operation; P. 0051 SSD 101 might maintain one or more pointers that are updated as memory blocks are trimmed at step 816 (e.g., as their BUS count is updated)
It would have been obvious to a person with ordinary skill in the art at the effective filing
date of the application to include the invention of Greiner and Hashimoto with the determining the units of data corresponding to an invalidation request taught by Cohen
The motivation being to ensure the new TRIM range is remembered as blocks are processed (See Cohen P. 0051)
The systems of Greiner, Hashimoto and Cohen are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Greiner and Hashimoto with Cohen to obtain the invention as recited in claim 6-7.
Claim 7
Cohen (2014/0047210) teaches:
The memory system according to claim 6, wherein the controller is further configured to: receive a second invalidation request from the host; P. 0030 “TRIM” command enables host device 180 to designate blocks of previously saved data as unneeded or invalid
determine a third range of physical addresses of the non-volatile memory where fifth data is stored, the fifth data being data to be invalidated in response to the second invalidation request; and P. 0048 when a TRIM command having a trim range is processed, determines whether there are partial SLM pages at the start or end of the TRIM range; P. 0044 the size values are subtracted from the BUS count of corresponding regions when SSD 101 performs a TRIM operation; P. 0051 SSD 101 might maintain one or more pointers that are updated as memory blocks are trimmed at step 816 (e.g., as their BUS count is updated)
when the third range is smaller than the first range, set information indicating invalidity of the fifth data in at least one of the first entries of another one of the plurality of first tables. P. 0047 SSD 101 determines a range of the TRIM operation (starting and ending LBAs) and maintains a beginning and an ending TBP index indicating portions of the first level map (FLM) requiring trim operations
Claim 9
The systems of Greiner and Hashimoto do not explicitly state determining the units of data corresponding to an invalidation request according to an address conversion table.
Cohen (2014/0047210) teaches:
The memory system according to claim 6, wherein the first invalidation request specifies a fourth range of logical addresses, and the controller is further configured to: manage mapping information between each of logical addresses used by the host and each of the physical addresses of the non-volatile memory, by using an address conversion table; and determine the second range of physical addresses of the non-volatile memory, from the fourth range of logical addresses by referring to the address conversion table. P. 0047 SSD 101 determines a range of the TRIM operation (starting and ending LBAs) and maintains a beginning and an ending TBP index indicating portions of the first level map (FLM) requiring trim operations; P. 0048 when a TRIM command having a trim range is processed, determines whether there are partial SLM pages at the start or end of the TRIM range
It would have been obvious to a person with ordinary skill in the art at the effective filing
date of the application to include the invention of Greiner and Hashimoto with the determining the units of data corresponding to an invalidation request according to an address conversion table taught by Cohen
The motivation being to ensure the new TRIM range is remembered as blocks are processed (See Cohen P. 0051)
The systems of Greiner, Hashimoto and Cohen are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Greiner and Hashimoto with Cohen to obtain the invention as recited in claim 9.
Claim 16
Greiner (2013/0339657) teaches:
determining that the second range is larger than or equal to the first range; and in response to determining that the second range is larger than or equal to the first range, setting the information indicating the invalidity of the first data in the one of the second entries of the second table. P. 0152 INVALIDATE DAT TABLE ENTRY (IDTE) selectively clears TLB combined region and segment table entries when a segment-table entry is invalidated; P. 0157 a range of entries beginning with the designated entry, is invalidated; P. 0153 During execution of an IDTE instruction, a specified portion of virtual storage is invalidated. As examples, a segment of storage, which includes a plurality of pages of storage, or a region of storage, which includes a plurality of segments of storage, is selected to be invalidated
The systems of Greiner and Hashimoto do not explicitly state determining the units of data corresponding to an invalidation request.
Cohen (2014/0047210) teaches:
The method according to claim 11, wherein each of the plurality of first tables corresponds to a first range of physical addresses of the non-volatile memory, and the method further comprises: receiving a first invalidation request from a host; P. 0030 During a delete operation, the OS sends a TRIM command specifying one or more ranges of Logical Block Addresses (LBAs)
determining a second range of physical addresses of the non-volatile memory where fourth data is stored, the fourth data being data to be invalidated in response to the first invalidation request and including at least the first data; P. 0048 when a TRIM command having a trim range is processed, determines whether there are partial SLM pages at the start or end of the TRIM range; P. 0044 the size values are subtracted from the BUS count of corresponding regions when SSD 101 performs a TRIM operation; P. 0051 SSD 101 might maintain one or more pointers that are updated as memory blocks are trimmed at step 816 (e.g., as their BUS count is updated)
It would have been obvious to a person with ordinary skill in the art at the effective filing
date of the application to include the invention of Greiner and Hashimoto with the determining the units of data corresponding to an invalidation request taught by Cohen
The motivation being to ensure the new TRIM range is remembered as blocks are processed (See Cohen P. 0051)
The systems of Greiner, Hashimoto and Cohen are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Greiner and Hashimoto with Cohen to obtain the invention as recited in claims 16-17.
Claim 17
Cohen (2014/0047210) teaches:
The method according to claim 16, further comprising: receiving a second invalidation request from the host; P. 0030 “TRIM” command enables host device 180 to designate blocks of previously saved data as unneeded or invalid
determining a third range of physical addresses of the non-volatile memory where fifth data is stored, the fifth data being data to be invalidated in response to the second invalidation request; P. 0048 when a TRIM command having a trim range is processed, determines whether there are partial SLM pages at the start or end of the TRIM range; P. 0044 the size values are subtracted from the BUS count of corresponding regions when SSD 101 performs a TRIM operation; P. 0051 SSD 101 might maintain one or more pointers that are updated as memory blocks are trimmed at step 816 (e.g., as their BUS count is updated)
determining that the third range is smaller than the first range; and in response to determining that the third range is smaller than the first range, setting information indicating invalidity of the fifth data in at least one of the first entries of another one of the plurality of first tables. P. 0047 SSD 101 determines a range of the TRIM operation (starting and ending LBAs) and maintains a beginning and an ending TBP index indicating portions of the first level map (FLM) requiring trim operations
Claim 19
The systems of Greiner and Hashimoto do not explicitly state determining the units of data corresponding to an invalidation request according to an address conversion table.
Cohen (2014/0047210) teaches:
The method according to claim 16, wherein the first invalidation request specifies a fourth range of logical addresses, and the method further comprises: managing mapping information between each of logical addresses used by the host and each of the physical addresses of the non-volatile memory, by using an address conversion table; and determining the second range of physical addresses of the non-volatile memory, from the fourth range of logical addresses by referring to the address conversion table. P. 0047 SSD 101 determines a range of the TRIM operation (starting and ending LBAs) and maintains a beginning and an ending TBP index indicating portions of the first level map (FLM) requiring trim operations; P. 0048 when a TRIM command having a trim range is processed, determines whether there are partial SLM pages at the start or end of the TRIM range
It would have been obvious to a person with ordinary skill in the art at the effective filing
date of the application to include the invention of Greiner and Hashimoto with the determining the units of data corresponding to an invalidation request according to an address conversion table taught by Cohen
The motivation being to ensure the new TRIM range is remembered as blocks are processed (See Cohen P. 0051)
The systems of Greiner, Hashimoto and Cohen are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Greiner and Hashimoto with Cohen to obtain the invention as recited in claim 19.
Allowable Subject Matter
Claims 8, 10, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 8 recites the limitation “wherein the controller is further configured to: transmit a completion response for the first invalidation request to the host before setting the information indicating the invalidity of the first data in the one of the second entries of the second table”
Said limitation is taught by the specification of the instant application as originally filed at least at [P. 0261 and FIG. 18]. Said limitations, in combination with the other recited limitations of claim 8, are not taught or suggested by a reasonable combination of the prior art of record.
The closest prior art of record includes: Greiner (2013/0339657); Hashimoto (2015/0370726); Cohen (2014/0047210); and Kim (2011/0264884) which teaches de-allocation in stages, erasing a first region, notifying host of completion, then erasing second region. None of the references teach transmitting a completion response to the host for an invalidation request which invalidates a range of physical addresses determined to be greater or equal to the range of addresses covered by a child table, before setting an invalid indicator of an entry of a parent table which references the child table, where validity indicators are in both parent and child tables.
Claim 18 contains similar limitations to claim 8, and is considered allowable for at least the same reasons as claim 8.
Claim 10 recites the limitation “wherein the address conversion table includes at least a plurality of fourth tables and at least one fifth table,
each of the plurality of fourth tables including a fourth number of fourth entries, each of the fourth entries having the mapping information between each of the logical addresses and each of the physical addresses,
the fifth table including a fifth number of fifth entries, each of the fifth entries having information indicating an address where each of the plurality of fourth tables is stored, and
a size of each of the plurality of first tables is same as a size of each of the plurality of fourth tables”
Said limitation is taught by the specification of the instant application as originally filed at least at [P. 0099, 0118, 0147 and FIG. 3]. Said limitations, in combination with the other recited limitations of claim 10, are not taught or suggested by a reasonable combination of the prior art of record.
The closest prior art of record includes: Greiner (2013/0339657); Hashimoto (2015/0370726); Cohen (2014/0047210). None of the references teach the address conversion table having first through fifth tables, where one of the first tables is referenced by an entry of the second tables, one of the fourth tables is referenced by an entry of the fifth table, where each fourth table has the same size as each first table and maps logical addresses to physical addresses.
Claim 20 contains similar limitations to claim 10, and is considered allowable for at least the same reasons as claim 10.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Persson et al. (U.S. Patent No. 10747681)
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/STEPHANIE WU/Primary Examiner, Art Unit 2133
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