DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is responding to the amendments filed on 05/22/2026. Claims 1, 11 and 18 have been amended. Claims 1-20 are subject to examination.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a calibration logic module configured to …”, “a performance monitor module configured to …” and “an address translation cache (ATC) configuration module configured to …” in claim 11.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
According to paragraph ¶0051 of the spec and Fig. 5: “Figure 5 is the system block diagram 500 that includes the host interface module (HIM) that includes the calibration logic performance monitor in order to measure the results and QoS performance. The HIM also has the ATC attribute configuration and that will be changed.” Therefore HIM contains all of the above modules. Therefore, the claimed limitations are considered in light of the structure depicted in Fig. 5.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-4 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borikar et al. [US 2020/0278935 A1] in view of INGRAM et al. [US 2022/0188038 A1] and in further view of Alexander et al. [US 2023/0418763 A1].
Claim 1 is rejected by Borikar, INGRAM and Alexander.
Borikar teaches “A data storage device, comprising: a memory device; and” as [Fig. 1, element 126A] (A local storage is depicted)
“a controller coupled to the memory device, wherein the controller is configured to:” as “a memory controller can include up to eight separate chip selects and may be capable of supporting up to eight ranks.” [¶0035] (A memory controller is coupled to memory devices)
“select a configuration for address translation cache (ATC) attributes for operating the data storage device,” as “ATS can allow the PCIe endpoints 312 to participate in the translation process, and can provide an ATC for the I/O device's own memory accesses.” [¶0064] (ATC is configured to operate storage device)
Borikar does not explicitly teach wherein the configuration comprises ATC size and eviction policy;
operate the data storage device using the configuration;
measure performance of the data storage device using the configuration;
change from the configuration to a different configuration for the ATC attributes based upon the measuring, wherein the different configuration comprises a different eviction policy; and
repeat the operating, the measuring, and the changing.
However, INGRAM teaches “wherein the configuration comprises ATC size and eviction policy;” as “determining when it is appropriate to trigger a prefetch of a memory address translation may be based on a configuration setting corresponding to a retention and/or eviction policy of memory address translations in the cache. In some implementations there may be a high level of precision with regards to storing only the most relevant memory address translations in the cache.” [¶0028]
“wherein the different configuration comprises a different eviction policy; and” as “determining when it is appropriate to trigger a prefetch of a memory address translation may be based on a configuration setting corresponding to a retention and/or eviction policy of memory address translations in the cache. In some implementations there may be a high level of precision with regards to storing only the most relevant memory address translations in the cache.” [¶0028]
Borikar and INGRAM are analogous arts because they teach adaptive address translation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Borikar and INGRAM before him/her, to modify the teachings of Borikar to include the teachings of INGRAM with the motivation of allowing the reduction of the size of the cache which may in turn reduce the time taken to find memory address translations in the cache. [INGRAM, ¶0028]
The combination of Borikar and INGRAM does not explicitly teach operate the data storage device using the configuration;
measure performance of the data storage device using the configuration;
change from the configuration to a different configuration for the ATC attributes based upon the measuring,
repeat the operating, the measuring, and the changing.
However, Alexander teaches “operate the data storage device using the configuration;” as “the TLB prefetcher configured to receive feedback from the miss queue” [¶0085] (The TLB which is essentially the ATC operates on configuration)
“measure performance of the data storage device using the configuration;” as “the TLB prefetcher configured to receive feedback from the miss queue at each TLB level for previously sent TLB prefetches” [¶0085] (measuring from the feedback)
“change from the configuration to a different configuration for the ATC attributes based upon the measuring,” as “control number of TLB prefetches sent for a trained TLB entry to each TLB level of the two or more TLB levels based on the feedback.” [¶0085] (Training the TLB (i.e., changing the configuration based on feedback))
“repeat the operating, the measuring, and the changing.” as “ the feedback includes a confirmation for the trained entry,” [¶0086] (Training involves repeating the process)
Borikar, INGRAM and Alexander are analogous arts because they teach adaptive address translation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Borikar, INGRAM and Alexander before him/her, to modify the teachings of combination of Borikar and INGRAM to include the teachings of Alexander with the motivation of minimizing the number of TLB misses improves processor efficiency. [Alexander, ¶0003]
Claim 3 is rejected by Borikar, INGRAM and Alexander.
The combination of Borikar and INGRAM does not explicitly teach wherein the configuration is a static ATC attribute configuration.
However, Alexander teaches “wherein the configuration is a static ATC attribute configuration.” as “The TLB prefetcher can start generating N L1 TLB prefetch requests, where N is the prefetch degree or distance and can be either statically programmed or dynamically adjusted with a programmable maximum cap.” [¶0016]
Claim 4 is rejected by Borikar, INGRAM and Alexander.
The combination of Borikar and INGRAM does not explicitly teach wherein the controller is configured to: select a working ATC configuration; operate the data storage device using the working configuration; and
determine whether a recalibration should occur after operating the data storage device using the working ATC configuration.
However, Alexander teaches “wherein the controller is configured to: select a working ATC configuration; operate the data storage device using the working configuration; and” as “Once an entry in the TLB prefetcher is trained, certain parameters are set to default values using, for example, configuration status registers.” [¶0028]
“determine whether a recalibration should occur after operating the data storage device using the working ATC configuration.” as “As noted, and described herein, the TLB prefetcher, including the state machine, can use different feedback mechanisms to tune which L1 miss queues and L2 miss queues to use, throttle sending of specific TLB prefetches, and invalidating entries.” [¶0044]
Claim 9 is rejected by Borikar, INGRAM and Alexander.
The combination of Borikar and INGRAM does not explicitly teach wherein the controller is configured to interact with one or more of the following: a virtual function; a physical function; a process address space identification (ID) (PASID); and combinations thereof.
However, Alexander teaches “wherein the controller is configured to interact with one or more of the following: a virtual function; a physical function; a process address space identification (ID) (PASID); and combinations thereof.” as “A translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory ” [¶0003]
Claim 10 is rejected by Borikar, INGRAM and Alexander.
Borikar teaches “wherein the configuration is weighted towards functions that are predetermined to necessitate higher responsiveness compared to other functions.” as “the Translation Request 360 may be generated in accordance with one or more ATC entry replacement policies (e.g., user-defined, QoS, rate limit, workload-based policies, etc.) and/or an ATC entry replacement algorithm (e.g., deficit weighted round robin (DWRR)).” [¶0072]
Claim(s) 11-12, 14 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over BENISTY et al. [US 2024/0143508 A1] in view of Alexander et al. [US 2023/0418763 A1] and in further view of INGRAM et al. [US 2022/0188038 A1].
Claim 11 is rejected by BENISTY, Alexander and INGRAM.
BENISTY teaches “A data storage device, comprising: a memory device; and” as “a data storage device comprises: a memory device; and a controller coupled to the memory device,” [¶0008]
“a controller coupled to the memory device, wherein the controller comprises a host interface module (HIM) comprising:” as “The present disclosure generally relates to improved address translation. Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command. ” [Abstract]
“an address translation cache (ATC) configuration module configured to maintain one or more cache configurations to be used for the adjusting by the calibration logic module,” as “PCIe address translation services (ATS) in the SSD is where the drive maintains an address translation cache (ATC) of the address translation tables so that the device does not have to look up the address translation from the root complex every time.” [¶0040]
BENISTY does not explicitly teach a calibration logic module configured to adjust cache configurations, measure performance of the data storage device, and intelligently select optimal cache configurations;
a performance monitor module configured to monitor the performance of the data storage device; and
wherein configurations comprise ATC size and eviction policy and wherein the adjusting comprises adjusting the eviction policy.
However, Alexander teaches “a calibration logic module configured to adjust cache configurations, measure performance of the data storage device, and intelligently select optimal cache configurations;” as “control number of TLB prefetches sent for a trained TLB entry to each TLB level of the two or more TLB levels based on the feedback.” [¶0085] (Training the TLB (i.e., changing the configuration based on feedback))
“a performance monitor module configured to monitor the performance of the data storage device; and” as “the TLB prefetcher configured to receive feedback from the miss queue at each TLB level for previously sent TLB prefetches” [¶0085] (measuring from the feedback)
BENISTY and Alexander are analogous arts because they teach adaptive address translation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of BENISTY and Alexander before him/her, to modify the teachings of BENISTY to include the teachings of Alexander with the motivation of minimizing the number of TLB misses improves processor efficiency. [Alexander, ¶0003]
The combination of BENISTY and Alexander does not explicitly teach wherein configurations comprise ATC size and eviction policy and wherein the adjusting comprises adjusting the eviction policy.
However, INGRAM teaches “wherein configurations comprise ATC size and eviction policy and wherein the adjusting comprises adjusting the eviction policy.” as “determining when it is appropriate to trigger a prefetch of a memory address translation may be based on a configuration setting corresponding to a retention and/or eviction policy of memory address translations in the cache. In some implementations there may be a high level of precision with regards to storing only the most relevant memory address translations in the cache.” [¶0028]
BENISTY, Alexander and INGRAM are analogous arts because they teach adaptive address translation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of BENISTY, Alexander and INGRAM before him/her, to modify the teachings of combination of BENISTY and Alexander to include the teachings of INGRAM with the motivation of allowing the reduction of the size of the cache which may in turn reduce the time taken to find memory address translations in the cache. [INGRAM, ¶0028]
Claim 12 is rejected by BENISTY, Alexander and INGRAM.
BENISTY does not explicitly teach wherein the calibration logic module is configured to adjust cache configurations based upon historically analyzed workload.
However, Alexander teaches “wherein the calibration logic module is configured to adjust cache configurations based upon historically analyzed workload.” as “In implementations, retraining can retrain the window, the stride, or both. In implementations, the state machine 3000 of FIG. 3 can go to the detect1 state 3200 to reduce the training time.” [¶0048]
Claim 14 is rejected by BENISTY, Alexander and INGRAM.
BENISTY does not explicitly teach wherein calibration performed by the calibration logic module is triggered at a higher rate when measured performance is lower than a threshold compared to when measured performance is equal to or greater than the threshold.
However, Alexander teaches “wherein calibration performed by the calibration logic module is triggered at a higher rate when measured performance is lower than a threshold compared to when measured performance is equal to or greater than the threshold.” as “The TLB forgiveness threshold is a programmable or configurable threshold which can be set, for example, using a configuration status register.” [¶0048]
Claim 17 is rejected by BENISTY, Alexander and INGRAM.
BENISTY does not explicitly teach wherein the modules operate dynamically.
However, Alexander teaches “wherein the modules operate dynamically.” as “The TLB prefetcher can start generating N L1 TLB prefetch requests, where N is the prefetch degree or distance and can be either statically programmed or dynamically adjusted with a programmable maximum cap.” [¶0016]
Claim 18 is rejected by BENISTY, Alexander and INGRAM under the same rationale of rejection of claim 11.
Claim 19 is rejected by BENISTY, Alexander and INGRAM.
BENISTY does not explicitly teach wherein the controller is configured to determine whether recalibration of ATC attributes should occur, wherein the determining occurs after the operating the data storage device using the selected optimal ATC attributes.
However, Alexander teaches “wherein the controller is configured to determine whether recalibration of ATC attributes should occur, wherein the determining occurs after the operating the data storage device using the selected optimal ATC attributes.” as “In implementations, retraining can retrain the window, the stride, or both. In implementations, the state machine 3000 of FIG. 3 can go to the detect1 state 3200 to reduce the training time.” [¶0048]
Claim 20 is rejected by BENISTY, Alexander and INGRAM.
BENISTY teaches “wherein the measuring, changing, selecting, and saving occur in a host interface module (HIM) of the controller.” as “Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command.” [¶0021]
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borikar et al. [US 2020/0278935 A1] in view of INGRAM et al. [US 2022/0188038 A1], in further view of Alexander et al. [US 2023/0418763 A1] and yet in further view of Gara et al. [US 2024/0330201 A1].
Claim 2 is rejected by Borikar, INGRAM, Alexander and Gara.
The combination of Borikar, INGRAM and Alexander does not explicitly teach wherein the configuration is a global ATC configuration.
However, Gara teaches “wherein the configuration is a global ATC configuration.” as “In some embodiments: the global address translation circuit is configured to map a third global virtual address range having a second size” [¶0013]
Borikar, INGRAM, Alexander and Gara are analogous arts because they teach adaptive address translation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Borikar, INGRAM, Alexander and Gara before him/her, to modify the teachings of combination of Borikar, INGRAM and Alexander to include the teachings of Gara with the motivation of it may be advantageous to assemble large numbers of computing elements, capable of exchanging data with each other. [Gara, ¶0003]
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borikar et al. [US 2020/0278935 A1] in view of INGRAM et al. [US 2022/0188038 A1], in further view of Alexander et al. [US 2023/0418763 A1] and yet in further view of Dooley et al. [US 10,372,618 B2].
Claim 5 is rejected by Borikar, INGRAM, Alexander and Dooley.
The combination of Borikar and INGRAM does not explicitly teach wherein the controller, after determining that a recalibration should occur, is configured to: change from the working ATC configuration to a new configuration for the ATC attributes;
operate the data storage device using the new configuration;
measure performance of the data storage device using the new configuration; select a new working ATC configuration for the data storage device; and
operate the data storage device using the selected new working ATC configuration.
However, Alexander teaches “wherein the controller, after determining that a recalibration should occur, is configured to: change from the working ATC configuration to a new configuration for the ATC attributes;” as “In implementations, retraining can retrain the window, the stride, or both. In implementations, the state machine 3000 of FIG. 3 can go to the detect1 state 3200 to reduce the training time.” [¶0048]
“operate the data storage device using the new configuration;” as “The TLB forgiveness threshold is a programmable or configurable threshold which can be set, for example, using a configuration status register.” [¶0048]
The combination of Borikar, INGRAM, and Alexander does not explicitly teach measure performance of the data storage device using the new configuration; select a new working ATC configuration for the data storage device; and
operate the data storage device using the selected new working ATC configuration.
However, Dooley teaches “measure performance of the data storage device using the new configuration; select a new working ATC configuration for the data storage device; and” as “If no hit is detected, then a full page table walk process can be implemented in order to obtain the information required for the table walk response to be returned to the core 10, and during that process one or more entries in the unified address translation cache may be allocated to store full and/or partial address translation data obtained during the page table walk process.” [Col 11, lines 50-57]
“operate the data storage device using the selected new working ATC configuration.” as “ if the lookup process is currently looking for full address translation data but it is known that full address translation data of one particular page size has never been allocated into the address translation cache, then the lookup control circuitry can omit performing a lookup operation for that assumed page size.” [Col 12, lines 4-10]
Borikar, INGRAM, Alexander and Dooley are analogous arts because they teach adaptive address translation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Borikar, INGRAM, Alexander and Dooley before him/her, to modify the teachings of combination of Borikar, INGRAM and Alexander to include the teachings of Dooley with the motivation of it will be seen that such embodiments provide a unified address translation cache that is able to store both full address translation data and partial address translation data, and where the contents may adapt dynamically to changing workload conditions so as to make more optimum use of the available resources for storing address translation data. [Dooley, Col 18, lines 32-38]
Claim 6 is rejected by Borikar, INGRAM, Alexander and Dooley.
The combination of Borikar and INGRAM does not explicitly teach wherein the controller is configured to repeat the changing to a new configuration, operating using the new configuration, and measuring performance using the new configuration.
However, Alexander teaches “wherein the controller is configured to repeat the changing to a new configuration, operating using the new configuration, and measuring performance using the new configuration.” as “FIG. 8 is a flowchart of a method 8000 for feedback when a TLB prefetcher is in a trained state. After the TLB prefetcher is in a trained state, it sends out TLB prefetches based on the training for each entry (operation 8002).” [¶0076]
Claim(s) 7-8, 13 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borikar et al. [US 2020/0278935 A1] in view of INGRAM et al. [US 2022/0188038 A1], in further view of Alexander et al. [US 2023/0418763 A1] and yet in further view of BENISTY et al. [US 2024/0143508 A1].
Claim 7 is rejected by Borikar, INGRAM, Alexander and BENISTY.
The combination of Borikar, INGRAM and Alexander does not explicitly teach wherein the controller comprises a host interface module (HIM) and wherein the ATC is disposed in the HIM.
However, BENISTY teaches “wherein the controller comprises a host interface module (HIM) and wherein the ATC is disposed in the HIM.” as “PCIe address translation services (ATS) in the SSD is where the drive maintains an address translation cache (ATC) of the address translation tables so that the device does not have to look up the address translation from the root complex every time.” [¶0040]
Borikar, INGRAM, Alexander and BENISTY are analogous arts because they teach adaptive address translation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Borikar, INGRAM, Alexander and BENISTY before him/her, to modify the teachings of combination of Borikar, INGRAM and Alexander to include the teachings of BENISTY with the motivation of the ATC is different from the TLB translation cache used by the host. When the ATS enabled SSD device shall implement and maintain a designated ATC to minimize performance dependencies on the TA and alleviate TA resource pressure. [BENISTY, ¶0034]
Claim 8 is rejected by Borikar, INGRAM, Alexander and BENISTY.
The combination of Borikar, INGRAM and Alexander does not explicitly teach wherein the HIM comprises an ATC attribute configuration module, a performance monitor module, and a calibration logic module.
However, BENISTY teaches “wherein the HIM comprises an ATC attribute configuration module, a performance monitor module, and a calibration logic module.” as “PCIe address translation services (ATS) in the SSD is where the drive maintains an address translation cache (ATC)” [¶0040]
Claim 13 is rejected by Borikar, INGRAM, Alexander and BENISTY.
The combination of Borikar, INGRAM and Alexander does not explicitly teach wherein the calibration logic module is configured to adjust cache configurations with a preconfigured weight towards functions that necessitate more responsiveness as compared to other functions that necessitate less responsiveness.
However, Borikar teaches “wherein the calibration logic module is configured to adjust cache configurations with a preconfigured weight towards functions that necessitate more responsiveness as compared to other functions that necessitate less responsiveness.” as “the Translation Request 360 may be generated in accordance with one or more ATC entry replacement policies (e.g., user-defined, QoS, rate limit, workload-based policies, etc.) and/or an ATC entry replacement algorithm (e.g., deficit weighted round robin (DWRR)).” [¶0072]
BENISTY, INGRAM, Alexander and Borikar are analogous arts because they teach adaptive address translation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of BENISTY, INGRAM, Alexander and Borikar before him/her, to modify the teachings of combination of BENISTY, INGRAM and Alexander to include the teachings of Borikar with the motivation of operate more efficiently with respect to energy consumption than conventional systems. [Borikar, ¶0025]
Claim 15 is rejected by BENISTY, INGRAM, Alexander and Borikar.
The combination of BENISTY, INGRAM and Alexander does not explicitly teach wherein calibration performed by the calibration logic module is triggered based upon external conditions and workloads of functions.
However, Borikar teaches “wherein calibration performed by the calibration logic module is triggered based upon external conditions and workloads of functions.” as “In addition, ATS is a general specification intended to provide interoperability for all types of PCIe endpoints and may not be optimal for specific types of workloads, heterogeneous workloads, and certain types of I/O devices.” [¶0003]
BENISTY, INGRAM, Alexander and Borikar are analogous arts because they teach adaptive address translation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of BENISTY, INGRAM, Alexander and Borikar before him/her, to modify the teachings of combination of BENISTY, INGRAM and Alexander to include the teachings of Borikar with the motivation of operate more efficiently with respect to energy consumption than conventional systems. [Borikar, ¶0025]
Claim 16 is rejected by BENISTY, INGRAM, Alexander and Borikar.
The combination of BENISTY, INGRAM and Alexander does not explicitly teach wherein calibration frequency is decreased when workload is increased.
However, Borikar teaches “wherein calibration frequency is decreased when workload is increased.” as “Various embodiments of the present disclosure can overcome these and other deficiencies of the prior art by utilizing an ATC that can intelligently adapt to heterogeneous workloads and applying one or more ATC entry replacement policies that can depend upon a number of different criteria,” [¶0018]
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132
Prosecution Insights