CTNF 18/967,946 CTNF 81061 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are pending. This is in response to communications filed on 12/4/24. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim(s) 1-7, 9-20 are is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kashyap et al (US Patent Application Publication 2025/0293692) For claim 1, Kashyap et al teach the following limitations: An apparatus for clock calibration (Fig 1; [0027]) , comprising: a first data path configured to generate a first signal (first clock signal mentioned in [0017][0029], which can be either reference clock 106 or delayed clock signal 116; reference clock signal 106 in Fig 2 is the first signal, Fig 1 shows that 106 generates from 108) the first signal comprising a first edge and a second edge (rising edge and falling edge as shown in Fig 2; 202 is the first edge and 204 is the second edge); and a calibration circuit (calibrator 114 in Fig 1 and Fig 4) coupled to the first data path (Fig 1), the calibration circuit being configured to determine a timing difference between the first edge and the second edge ([0042] – measuring high phase and low phase of reference clock 108; high phase and low refers to time difference of the two edges of rising edge and falling edge) , the calibration circuit comprising: a clock generator configured to generate a reference clock signal (reference delay signal 118 is the second clock; second clock signal mentioned in [0017] [0029]; Fig 1 and Fig 2 show the second clock 118 as reference clock generated from 104) , the reference clock signal comprising a third edge and a fourth edge (reference signal 118 has rising and falling edges as shown in Fig 2, which includes third and fourth edges); a delay tuner coupled to the clock generator and the first data path (114 is coupled to 108 and 104 as shown in Fig 1 and include a delay tuner 124 to determine delay as shown in Fig 1; [0027] – delay code 112 based on delay), the delay tuner being configured to determine a first delay between the first edge and the third edge ([0035] – first offset between rising edge 202 of reference clock 106 and corresponding rising edge 202 of reference delay signal 118 is determined) and a second delay between the second edge and the fourth edge ([0035] – third offset between falling edge 202 of reference clock 106 and corresponding falling edge 202 of reference delay signal 118 is determined) ; and a phase detector ( adjuster 126 in Fig 1; phase detector 402 through phase filter 406 in Fig 4) coupled to the delay tuner (Fig 1; Fig 4 ) and configured to determine a phase difference between the first signal and the reference clock signal ([0046]; [0062] – high to low transition of phase detector 402 is tracked; [0037] – delay is adjusted to synchronize the clock signals) based at least on the first delay and the second delay ([0037]-[0038]; [0050]; [0068] Fig 5 – Fig 7; the calibration reduces the phase difference based on the offsets). For claim 2, Kashyap et al teach the following limitations: wherein the calibration circuit is further configured to generate a second signal by shifting the first signal relative to the reference clock signal (Fig 4 shows that the delay code is applied to 102 to generate adjusted 116, which has associated edges), the second signal comprises a fifth edge associated with the first edge and a sixth edge associated with the second edge (116 in Fig 4 is delayed by 416 and 116 has edges shown in Fig 2). For claim 3, Kashyap et al teach the following limitations: the delay tuner is further configured to determine a third delay between the third edge and the fifth edge and a fourth delay between the fourth edge and the sixth edge (Fig 4 shows that as the feedback loop so delay determination and adjustment are continuous process; [0048] – C1 between two rising edges; [0049]- offsets between edges; thus delays on various edges are determined). For claim 4, Kashyap et al teach the following limitations: wherein the timing difference between the first edge and the second edge is associated with the first delay, the second delay, the third delay, and the fourth delay ([0049]-[0050] – various edges and offsets are used to calculate the amount of delay to adjust for synchronization [0031] and [0037]). For claim 5, Kashyap et al teach the following limitations: wherein the calibration circuit is configured to generate the second signal by shifting the first signal by a predetermined interval relative to the reference clock signal (Fig 2 shows first signal 106, second signal 116 and the reference signal 118; delay line 102 cause the shift and predetermined interval is the invert relationship [0032] “less than length of a period”; [0044] known delay with respect to reference signal 104). For claim 6, Kashyap et al teach the following limitations: wherein the first edge is associated with an even clock signal and the second edge is associated with an odd clock signal (first clock edge associated with rising edge – even clock, second edge associated with falling edge – odd clock; Fig 2; [0035]). For claim 7, Kashyap et al teach the following limitations: wherein the calibration circuit is configured to generate a calibration signal (Fig 4 shows the calibration signals include 414, 416 and 422) to adjust at least one of the even clock signals or the odd clock signal (the even clock and odd clock edges of 116 is calibrated) based on the timing difference between the first edge and the second edge (the timing offsets are used to generate phase adjustment signals ([0048]-[0050]). For claim 9, Kashyap et al teach the following limitations: wherein the calibration circuit further comprises a controller coupled to the phase detector (state machine 404 is the controller), the controller is configured to transmit a control signal to the phase detector to select between the first edge and the second edge for delay measurement (414 and 422 are the control signal selecting edges between 108 – first and second edge and edges in MUX 412 including edges of clock signal 116 and 118). For claim 10, Kashyap et al teach the following limitations: An apparatus for clock calibration (Fig 1; [0027]) , comprising: a first data path configured to generate a first signal (first clock signal mentioned in [0017][0029], which can be either reference clock 106 or delayed clock signal 116; reference clock signal 106 in Fig 2 is the first signal, Fig 1 shows that 106 generates from 108) the first signal comprising a first edge and a second edge (rising edge and falling edge as shown in Fig 2; 202 is the first edge and 204 is the second edge), the first edge being associated with a first clock signal, and the second edge being associated with a second clock signal ([0017] – first clock signal is reference clock or input clock to delay line; [0026] reference clock 106 corresponds to first clock; [0043] delay line 102 causes delay in reference clock 106 to generate 116, which is the second clock; 106 and 116 are shown in Fig 2; thus the first edge and second edge are associated with both 106 and 116 – the first and second clock signal); and a calibration circuit (calibrator 114 in Fig 1 and Fig 4) coupled to the first data path (Fig 1), the calibration circuit being configured to determine a timing difference between the first edge and the second edge ([0042] – measuring high phase and low phase of reference clock 108; high phase and low refers to time difference of the two edges of rising edge and falling edge) , the calibration circuit comprising: a clock generator configured to generate a reference clock signal (reference delay signal 118 is the second clock; second clock signal mentioned in [0017] [0029]; Fig 1 and Fig 2 show the second clock 118 as reference clock generated from 104) , the reference clock signal comprising a third edge and a fourth edge (reference signal 118 has rising and falling edges as shown in Fig 2, which includes third and fourth edges); a delay tuner coupled to the clock generator and the first data path (114 is coupled to 108 and 104 as shown in Fig 1 and include a delay tuner 124 to determine delay as shown in Fig 1; [0027] – delay code 112 based on delay), the delay tuner being configured to determine a first delay between the first edge and the third edge ([0035] – first offset between rising edge 202 of reference clock 106 and corresponding rising edge 202 of reference delay signal 118 is determined) and a second delay between the second edge and the fourth edge ([0035] – third offset between falling edge 202 of reference clock 106 and corresponding falling edge 202 of reference delay signal 118 is determined) ; and a phase detector ( adjuster 126 in Fig 1; phase detector 402 through phase filter 406 in Fig 4) coupled to the delay tuner (Fig 1; Fig 4 ) and configured to determine a phase difference between the first signal and the reference clock signal ([0046]; [0062] – high to low transition of phase detector 402 is tracked; [0037] – delay is adjusted to synchronize the clock signals) based at least on the first delay and the second delay ([0037]-[0038]; [0050]; [0068] Fig 5 – Fig 7; the calibration reduces the phase difference based on the offsets). For claim 11, Kashyap et al teach the following limitations: wherein the calibration circuit is further configured to generate a second signal by shifting the first signal relative to the reference clock signal (Fig 4 shows that the delay code is applied to 102 to generate adjusted 116, which has associated edges), the second signal comprises a fifth edge associated with the first edge and a sixth edge associated with the second edge (116 in Fig 4 is delayed by 416 and 116 has edges shown in Fig 2). For claim 12, Kashyap et al teach the following limitations: wherein the delay tuner is further configured to determine a third delay between the third edge and the fifth edge and a fourth delay between the fourth edge and the sixth edge (Fig 4 shows that as the feedback loop so delay determination and adjustment are continuous process; [0048] – C1 between two rising edges; [0049]- offsets between edges). For claim 13, Kashyap et al teach the following limitations: wherein the timing difference between the first edge and the second edge is associated with the first delay, the second delay, the third delay, and the fourth delay ([0049]-[0050] – various edges and offsets are used to calculate the amount of delay to adjust for synchronization [0031] and [0037]). For claim 14, Kashyap et al teach the following limitations: wherein the first clock signal comprises an even clock signal (Fig 2). For claim 15, Kashyap et al teach the following limitations: wherein the second clock signal comprises an odd clock signal (Fig 2). For claim 16, Kashyap et al teach the following limitations: wherein the calibration circuit further comprises a controller coupled to the phase detector (state machine 404 is the controller), the controller is configured to transmit a control signal to the phase detector to select between the first edge and the second edge for delay measurement (414 and 422 are the control signal selecting edges between 108 – first and second edge and edges in MUX 412 including edges of clock signal 116 and 118). For claim 17, Kashyap et al teach the following limitations: An apparatus for clock calibration (Fig 1; [0027]) comprising: a first data path configured to generate a first signal (first clock signal mentioned in [0017][0029], which can be either reference clock 106 or delayed clock signal 116; reference clock signal 106 in Fig 2 is the first signal, Fig 1 shows that 106 generates from 108) , the first signal comprising a first edge and a second edge (rising edge and falling edge as shown in Fig 2; 202 is the first edge and 204 is the second edge) ; a clock generator configured to generate a reference clock signal (reference delay signal 118 is the second clock; second clock signal mentioned in [0017] [0029]; Fig 1 and Fig 2 show the second clock 118 as reference clock generated from 104) , the reference clock signal comprising a third edge and a fourth edge (reference signal 118 has rising and falling edges as shown in Fig 2, which includes third and fourth edges); a delay tuner coupled to the clock generator and the first data path (114 is coupled to 108 and 104 as shown in Fig 1 and include a delay tuner 124 to determine delay as shown in Fig 1; [0027] – delay code 112 based on delay), the delay tuner being configured to determine a first delay between the first edge and the third edge ([0035] – first offset between rising edge 202 of reference clock 106 and corresponding rising edge 202 of reference delay signal 118 is determined) and a second delay between the second edge and the fourth edge ([0035] – third offset between falling edge 202 of reference clock 106 and corresponding falling edge 202 of reference delay signal 118 is determined) ; and a phase detector ( adjuster 126 in Fig 1; phase detector 402 through phase filter 406 in Fig 4) coupled to the delay tuner (Fig 1; Fig 4 ) and configured to determine a phase difference between the first signal and the reference clock signal ([0046]; [0062] – high to low transition of phase detector 402 is tracked; [0037] – delay is adjusted to synchronize the clock signals) based at least on the first delay and the second delay ([0037]-[0038]; [0050]; [0068] Fig 5 – Fig 7; the calibration reduces the phase difference based on the offsets). For claim 18, Kashyap et al teach the following limitations: wherein the delay tuner is further configured to generate a second signal by shifting the first signal relative to the reference clock signal (Fig 4 shows that the delay code is applied to 102 to generate adjusted 116, which has associated edges), the second signal comprises a fifth edge associated with the first edge and a sixth edge associated with the second edge (116 in Fig 4 is delayed by 416 and 116 has edges shown in Fig 2). For claim 19, Kashyap et al teach the following limitations: wherein the delay tuner is further configured to determine a third delay between the third edge and the fifth edge and a fourth delay between the fourth edge and the sixth edge (Fig 4 shows that as the feedback loop so delay determination and adjustment are continuous process; [0048] – C1 between two rising edges; [0049]- offsets between edges; thus delays on various edges are determined). For claim 20, Kashyap et al teach the following limitations: wherein the timing difference between the first edge and the second edge is associated with the first delay, the second delay, the third delay, and the fourth delay ([0049]-[0050] – various edges and offsets are used to calculate the amount of delay to adjust for synchronization [0031] and [0037]) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kashyap et al (US Patent Application Publication 2025/0293692) in view of Zerbe et al (US Patent 6643787) . For claim 8, Kashyap et al teach the delay value of delay buffer adjustment ([0037]), but does not mention the calibration signal is configured to adjust at least one of a capacitance, a bias current, or a reference voltage in a clock buffer. Zebre teaches a system where delay value of the delay buffer is adjusted by adjustment of the capacitance (Fig 10; lines 39-46 of col 10). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to adjust the capacitance in the clock buffer for delay adjustment, since that way the clock buffer can be controlled digitally to provide the desired delay adjustment. The digital control has associated benefits of using known and simpler circuitries. Conclusion PTO-892 cites additional references that are not relied upon for rejection, but provide background information related to the Invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAHMIDA RAHMAN whose telephone number is (571)272-8159. The examiner can normally be reached Monday - Friday 10 AM - 7 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAHMIDA RAHMAN/Primary Examiner, Art Unit 2175 Application/Control Number: 18/967,946 Page 2 Art Unit: 2175 Application/Control Number: 18/967,946 Page 3 Art Unit: 2175 Application/Control Number: 18/967,946 Page 4 Art Unit: 2175 Application/Control Number: 18/967,946 Page 5 Art Unit: 2175 Application/Control Number: 18/967,946 Page 6 Art Unit: 2175 Application/Control Number: 18/967,946 Page 7 Art Unit: 2175 Application/Control Number: 18/967,946 Page 8 Art Unit: 2175 Application/Control Number: 18/967,946 Page 9 Art Unit: 2175 Application/Control Number: 18/967,946 Page 10 Art Unit: 2175 Application/Control Number: 18/967,946 Page 11 Art Unit: 2175
Prosecution Insights