DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 18968236, filed on 12/04/2024.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/04/2024 and 08/05/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2, 3, 5, 8-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2, 9, and 15 recite the limitation "the basis”. There is insufficient antecedent basis for this limitation in the claim. This is being interpreted as “a basis”.
Claims 3, 10-14, and 16-19 are rejected as dependent on the above claims.
Claims 5, 8, 12, and 17 recite the limitation "the corresponding layout”. There is insufficient antecedent basis for this limitation in the claim. This is being interpreted as “a corresponding layout”.
Claims 9-14 are rejected as dependent on the above claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-19 are rejected under 35 U.S.C. 101.
Claim 1 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea of generating images, without significantly more.
The claim recites: “A device for generating a defect image, the device comprising:
a memory configured to store a plurality of normal patterns with different sizes and a plurality of defect patterns; and
a processor configured to generate a layout image including at least one layout, generate a composite image by acquiring at least one normal pattern corresponding to a physical feature of each layout of the layout image from the memory, and generate a defect image by integrating at least one defect pattern with the composite image.”
The limitations, as drafted, are processes that, under their broadest reasonable interpretation, cover performance of the limitation in the mind and by pen and paper1. A person can mentally store normal patterns and defect patterns, then generate a layout image, composite image, and defect image by pen and paper.
This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements of a device with a memory and processor. These are recited at a high level of generality such that they amount to no more than generic computational and storage means. Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements are recited at a high-level of generality. It is therefore a judicial exception that is not integrated into a practical application, and does not include additional elements that are sufficient to amount to significantly more than the judicial exception. This claim is not patent eligible.
Claims 2-3 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea of generating the normal patterns based on a photograph, wherein the normal patterns include pixel-unit patterns and region-unit patterns. This amounts to a series of mental processes, and the photographing amounts to insignificant extra-solution activity (data collection). The claims are not patent eligible.
Claims 4-6 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea of describing the layout image being generated based on layout information with various features (mental process, pen and paper), generating the composite image by inpainting a normal pattern (mental process, pen and paper), and generating the defect image by inpainting a defect pattern (mental process, pen and paper). The claims are not patent eligible.
Claims 7 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea of generating ground truth data based on a position, which can be done mentally and with pen and paper. The claim is not patent eligible.
Claims 8-19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea of a method analogous to the abstract idea of the invention of claims 1-7. The claims are not patent eligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Riley (US20190294923A1) in view of Inoue (US20100152876A1).
Regarding claim 8, Riley teaches “A method of generating a defect image, the method comprising: generating, by a processor, a layout image including at least one layout;” (Riley, Paragraphs 22, 66, and 43, “The terms “design,” “design data,” and “design information” as used interchangeably herein generally refer to the physical design (layout) of an IC and data derived from the physical design through complex simulation or simple geometric and Boolean operations. In addition, an image of a reticle acquired by a reticle inspection system and/or derivatives thereof can be used as a “proxy” or “proxies” for the design. Such a reticle image or a derivative thereof can serve as a substitute for the design layout in any embodiments described herein that use a design. The design may include any other design data or design data proxies described in commonly owned U.S. Pat. No. 7,570,796 issued on Aug. 4, 2009 to Zafar et al. and U.S. Pat. No. 7,676,077 issued on Mar. 9, 2010 to Kulkarni et al., both of which are incorporated by reference as if fully set forth herein. In addition, the design data can be standard cell library data, integrated layout data, design data for one or more layers, derivatives of the design data, and full or partial chip design data. “In a further embodiment, the one or more alterations include one or more manually drawn alterations input by the user with a drawing tool included in the image editing tools. The drawing tool may include the drawing, painting, and erasing icons shown in portion 210 of the GUI in FIG. 2. The drawing tool may be used for freehand drawing of a polygon or irregular shape. The user may manually draw alterations on any available images to thereby insert or create painted synthetic defects therein. For example, the GUI may display a variety of reference images generated for a specimen or specimens, which are images that are subtracted from test images to detect defects therein, and/or other defect-free images. The reference images may be generated by imaging an actual specimen (as would be the case for die-to-die or cell-to-cell defect detection) or by simulating a reference image from a design for the specimen.”; “The computer subsystems shown in FIG. 1 (as well as other computer subsystems described herein) may also be referred to herein as computer system(s). Each of the computer subsystem(s) or system(s) described herein may take various forms, including a personal computer system, image computer, mainframe computer system, workstation, network appliance, Internet appliance, or other device. In general, the term “computer system” may be broadly defined to encompass any device having one or more processors, which executes instructions from a memory medium. The computer subsystem(s) or system(s) may also include any suitable processor known in the art such as a parallel processor. In addition, the computer subsystem(s) or system(s) may include a computer platform with high speed processing and software, either as a standalone or a networked tool.” Note that Riley discloses that the design includes integrated layout data, and the reference image is a simulated image generated according to the design, therefore the reference image amounts to a layout image (simulated image of the integrated layout data).
While Riley further discloses generating a defect image by integrating a defect pattern into an image (Riley, Paragraph 65, and Figure 6, “In another embodiment, the one or more alterations include creating a synthetic defect in the at least one of the one or more images. For example, the GUI may be configured to allow the user to add defects to at least one of the images using a suite of image editing tools. The user may add defects to one or more of the images, and the defect that is added to any one of the images may be the same or different as any of the other synthetic defects. For example, a user may add the same synthetic defect to different images, which may be useful if the same DOI type is known to show up in different areas in a design for the specimen. The user may also or alternatively add different synthetic defects to different instances of the same image. The different synthetic defects may be different types of defects, which may be useful when a portion of a design is known to be susceptible to different types of defects, but the different synthetic defects may also be the same type of defect but with one or more different characteristics such as those described further herein. Creating the synthetic defect may be performed using one or more of the image editing tools described further herein including, but not limited to, a drawing tool, a painting tool, an erasing tool, cut and paste tools, and the like. For example, the user may manually draw or paint a synthetic defect into an image in the GUI, the user may manually erase a portion of an image in the GUI to thereby create a synthetic defect in the image, and the user may also cut and/or copy a defect image or a portion of an image and paste it into another image to create a synthetic defect in the other image.”), Riley does not expressly disclose “generating, by the processor, a composite image by integrating at least one normal pattern corresponding to a physical feature of each layout included in the layout image with the corresponding layout;”.
Inoue teaches generating a composite layout by integrating normal patterns corresponding to physical features of layouts included in a layout design (Inoue, Paragraphs 44-45, “At step S4, in response to an instruction from a user via the input unit 4, the layout generating section 22 refers to the cell library 12 based on the net list 10 to read patterns of macro cells and logic cells, and arranges them in a generation area of the semiconductor chip area. The net list 10 stores an inter-cell wiring state, and at the same time, stores data for specifying each of the cells. Based on this data, even if the same function is included, a cell specified based on required current capacitance, driving capability, cell size, cell shape, etc. is arranged. As a result, in the generation area, cells that would be required to achieve a desired function are arranged. For a cell arrangement, the cells are arranged based on a conventionally known technique. For example, a large-sized macro cell is first arranged, and then the cells such as the logic cell are arranged around the macro cell. The layout generating section 22 registers a coordinate position of each of the arranged cells, a size of each cell, etc. into the layout data table 34 in relation with the data specifying this cell. A format of the data of each of the cells registered at this point is the same as that of a conventional layout pattern generating apparatus.”)
It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date of the claimed invention of the instant application to use a composite layout generated from integrating normal patterns corresponding to physical features of layouts, as taught by Inoue, with respect to the layout image of Riley, for the generation of a composite image into which the defect pattern is integrated by Riley to generate the defect image.
The motivation for doing so would have been to increase training sample diversity for better training. Further, one skilled in the art could have combined the elements as described above by known methods with no change in their respective functions, and the combination would have yielded nothing more than predictable results. Therefore, it would have been obvious to combine Riley with the above teaching of Inoue to fully disclose, “generating, by the processor, a composite image by integrating at least one normal pattern corresponding to a physical feature of each layout included in the layout image with the corresponding layout; and generating, by the processor, a defect image by integrating at least one defect pattern with the composite image.”
Regarding claim 1, claim 1 recites a system with elements corresponding to the steps recited in Claim 8. Therefore, the recited elements of this claim are mapped to the analogous steps in the corresponding method claim. Additionally, the rationale and motivation to combine the references apply to this claim. Claim 1 differs from claim 8 by the recitation of a device “comprising: a memory configured to store a plurality of normal patterns with different sizes and a plurality of defect patterns;”. These features are expressly taught by the references: (Inoue, Paragraphs 44-45, “At step S4, in response to an instruction from a user via the input unit 4, the layout generating section 22 refers to the cell library 12 based on the net list 10 to read patterns of macro cells and logic cells, and arranges them in a generation area of the semiconductor chip area. The net list 10 stores an inter-cell wiring state, and at the same time, stores data for specifying each of the cells. Based on this data, even if the same function is included, a cell specified based on required current capacitance, driving capability, cell size, cell shape, etc. is arranged. As a result, in the generation area, cells that would be required to achieve a desired function are arranged. For a cell arrangement, the cells are arranged based on a conventionally known technique. For example, a large-sized macro cell is first arranged, and then the cells such as the logic cell are arranged around the macro cell. The layout generating section 22 registers a coordinate position of each of the arranged cells, a size of each cell, etc. into the layout data table 34 in relation with the data specifying this cell. A format of the data of each of the cells registered at this point is the same as that of a conventional layout pattern generating apparatus.” Note that this was incorporated with rationale and motivation in the rejection of claim 8.; Riley, Paragraph 67, “In another embodiment, the one or more alterations include pasting a portion of an image corresponding to a known DOI into the at least one of the one or more images. For example, the image editing tools may include a copy/paste tool that can be used to copy/paste an image patch from one image to another. In this manner, a defect image, which may be an image of an actual defect found on an actual specimen or a synthetic defect created by the user, may be copied and pasted from one image to another image to thereby add that defect to the other image. Such functionality may be particularly useful when a DOI is known to be possible in different areas in a design for the specimen.”; Riley, Paragraph 43, “The computer subsystems shown in FIG. 1 (as well as other computer subsystems described herein) may also be referred to herein as computer system(s). Each of the computer subsystem(s) or system(s) described herein may take various forms, including a personal computer system, image computer, mainframe computer system, workstation, network appliance, Internet appliance, or other device. In general, the term “computer system” may be broadly defined to encompass any device having one or more processors, which executes instructions from a memory medium. The computer subsystem(s) or system(s) may also include any suitable processor known in the art such as a parallel processor. In addition, the computer subsystem(s) or system(s) may include a computer platform with high speed processing and software, either as a standalone or a networked tool.”) Therefore, Riley in view of Inoue fully disclose the limitations of claim 1.
Claim(s) 9-19 and 2-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Riley in view of Inoue further in view of Woodward (US20210034805A1).
Regarding claim 9, Riley in view of Inoue disclose “The method of claim 8,”
While Riley in view of Inoue disclose storing a plurality of normal patterns in a memory before generating the layout image (Inoue, Paragraphs 44-45, “At step S4, in response to an instruction from a user via the input unit 4, the layout generating section 22 refers to the cell library 12 based on the net list 10 to read patterns of macro cells and logic cells, and arranges them in a generation area of the semiconductor chip area. The net list 10 stores an inter-cell wiring state, and at the same time, stores data for specifying each of the cells. Based on this data, even if the same function is included, a cell specified based on required current capacitance, driving capability, cell size, cell shape, etc. is arranged. As a result, in the generation area, cells that would be required to achieve a desired function are arranged. For a cell arrangement, the cells are arranged based on a conventionally known technique. For example, a large-sized macro cell is first arranged, and then the cells such as the logic cell are arranged around the macro cell. The layout generating section 22 registers a coordinate position of each of the arranged cells, a size of each cell, etc. into the layout data table 34 in relation with the data specifying this cell. A format of the data of each of the cells registered at this point is the same as that of a conventional layout pattern generating apparatus.” Note that the cell library/net list is pre-stored for repeated use in composite image generation, therefore it is stored before the generating of the layout image. Further note that the above was incorporated with rationale and motivation in the rejection of claim 8.), Riley in view of Inoue do not expressly disclose generating the plurality of normal patterns (cell library/net list) “on the basis of a normal image obtained by photographing a normal mask”.
Woodward teaches generating a plurality of normal patterns “on the basis of a normal image obtained by photographing a normal mask” (Woodward, Figure 5 and Paragraph 11, “In light of the above, various methods and apparatuses are disclosed herein to extract standard cells to form a standard cell candidate library for RE of an IC, which requires no prior knowledge of the design of the IC and improves cell boundary detection between two cells. Systems structured in accordance with various embodiments of the present disclosure overcome challenges faced by existing systems by way of utilizing a feature vector encoding mechanism and a set of model rules to analyze the extracted contact layer image for cell boundary detection. Standard cells then can be extracted from raw images to form a standard cell library without prior knowledge of the IC design. As such, systems structured in accordance with various embodiments of the present disclosure provide specific, technical solutions to technical problems faced by existing systems, the details of which are described hereinafter.” Additionally, see the 1st sentence of Paragraph 37, “Accordingly, various embodiments provide a process for automatically extracting standard cells to form a standard cell candidate library using raw multi-layered images of an IC.”)
It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date of the claimed invention of the instant application to perform the generating of a plurality of normal patterns based on a normal image of a normal of a normal mask of Woodward to use as the cell library/net list data (plurality of generated normal patterns) of Riley in view of Inoue.
The motivation for doing so would have been to create the cell library/net list. Riley in view of Inoue utilize said data, but are silent on the origin of the data. Therefore, the above incorporation enables the performance of the steps already expressly taught by Riley in view of Inoue. Further, one skilled in the art could have combined the elements as described above by known methods with no change in their respective functions, and the combination would have yielded nothing more than predictable results. Therefore, it would have been obvious to combine Riley in view of Inoue with the above teaching of Woodward to fully disclose, “further comprising, before the generating of the layout image, generating, by the processor, a plurality of normal patterns on the basis of a normal image obtained by photographing a normal mask and storing the plurality of generated normal patterns in a memory.”
Regarding claim 10, Riley in view of Inoue further in view of Woodward disclose “The method of claim 9,”
“wherein the storing of the plurality of generated normal patterns comprises extracting, by the processor, one or more pixel-unit patterns from the normal image, generating one or more region-unit patterns by combining a plurality of pixel-unit patterns among the extracted pixel-unit patterns, and
generating the one or more pixel-unit patterns and the one or more region-unit patterns as the normal patterns.” (In view of the combination statement in claim 9, the references disclose extracting cells from raw images, wherein the cells are the normal patterns. These cells are mapped to “region-unit patterns”, which are inherently a combination of extracted pixels (pixel-unit patterns) from the normal image. The normal patterns therefore are made up of “the one or more pixel-unit patterns and the one or more region-unit patterns”.)
Regarding claim 11, Riley in view of Inoue further in view of Woodward disclose “The method of claim 9,”
“wherein the generating of the layout image comprises, when layout information including at least one of physical features, a number, sizes, and directions of layouts is input, generating, by the processor, the layout image including one or more layouts in accordance with the layout information.” (Riley, Paragraphs 22 and 66, “The terms “design,” “design data,” and “design information” as used interchangeably herein generally refer to the physical design (layout) of an IC and data derived from the physical design through complex simulation or simple geometric and Boolean operations. In addition, an image of a reticle acquired by a reticle inspection system and/or derivatives thereof can be used as a “proxy” or “proxies” for the design. Such a reticle image or a derivative thereof can serve as a substitute for the design layout in any embodiments described herein that use a design. The design may include any other design data or design data proxies described in commonly owned U.S. Pat. No. 7,570,796 issued on Aug. 4, 2009 to Zafar et al. and U.S. Pat. No. 7,676,077 issued on Mar. 9, 2010 to Kulkarni et al., both of which are incorporated by reference as if fully set forth herein. In addition, the design data can be standard cell library data, integrated layout data, design data for one or more layers, derivatives of the design data, and full or partial chip design data. “In a further embodiment, the one or more alterations include one or more manually drawn alterations input by the user with a drawing tool included in the image editing tools. The drawing tool may include the drawing, painting, and erasing icons shown in portion 210 of the GUI in FIG. 2. The drawing tool may be used for freehand drawing of a polygon or irregular shape. The user may manually draw alterations on any available images to thereby insert or create painted synthetic defects therein. For example, the GUI may display a variety of reference images generated for a specimen or specimens, which are images that are subtracted from test images to detect defects therein, and/or other defect-free images. The reference images may be generated by imaging an actual specimen (as would be the case for die-to-die or cell-to-cell defect detection) or by simulating a reference image from a design for the specimen.” The integrated layout data is mapped to the claimed “layout information including at least one of physical features, a number, sizes, and directions of layouts” with which the layout image is generated in accordance.)
Regarding claim 12, Riley in view of Inoue further in view of Woodward disclose “The method of claim 9,”
“wherein the generating of the composite image comprises acquiring, by the processor, at least one normal pattern between a region-unit pattern and a pixel-unit pattern corresponding to the physical feature of each layout included in the layout image from the memory and generating the composite image by inpainting the corresponding layout using the acquired normal pattern. (Inoue, Paragraphs 44-45, “At step S4, in response to an instruction from a user via the input unit 4, the layout generating section 22 refers to the cell library 12 based on the net list 10 to read patterns of macro cells and logic cells, and arranges them in a generation area of the semiconductor chip area. The net list 10 stores an inter-cell wiring state, and at the same time, stores data for specifying each of the cells. Based on this data, even if the same function is included, a cell specified based on required current capacitance, driving capability, cell size, cell shape, etc. is arranged. As a result, in the generation area, cells that would be required to achieve a desired function are arranged. For a cell arrangement, the cells are arranged based on a conventionally known technique. For example, a large-sized macro cell is first arranged, and then the cells such as the logic cell are arranged around the macro cell. The layout generating section 22 registers a coordinate position of each of the arranged cells, a size of each cell, etc. into the layout data table 34 in relation with the data specifying this cell. A format of the data of each of the cells registered at this point is the same as that of a conventional layout pattern generating apparatus.” As described above, cells (region-unit patterns) are inpainted according to physical feature (size/shape). Note that the above teaching of Inoue was incorporated with rationale and motivation in the rejection of claim 8.)
Regarding claim 13, Riley in view of Inoue further in view of Woodward disclose “The method of claim 9,”
“wherein the generating of the defect image comprises generating, by the processor, the defect image by inpainting at least one position in the composite image using the at least one defect pattern.” (Riley, Paragraph 65, and Figure 6, “In another embodiment, the one or more alterations include creating a synthetic defect in the at least one of the one or more images. For example, the GUI may be configured to allow the user to add defects to at least one of the images using a suite of image editing tools. The user may add defects to one or more of the images, and the defect that is added to any one of the images may be the same or different as any of the other synthetic defects. For example, a user may add the same synthetic defect to different images, which may be useful if the same DOI type is known to show up in different areas in a design for the specimen. The user may also or alternatively add different synthetic defects to different instances of the same image. The different synthetic defects may be different types of defects, which may be useful when a portion of a design is known to be susceptible to different types of defects, but the different synthetic defects may also be the same type of defect but with one or more different characteristics such as those described further herein. Creating the synthetic defect may be performed using one or more of the image editing tools described further herein including, but not limited to, a drawing tool, a painting tool, an erasing tool, cut and paste tools, and the like. For example, the user may manually draw or paint a synthetic defect into an image in the GUI, the user may manually erase a portion of an image in the GUI to thereby create a synthetic defect in the image, and the user may also cut and/or copy a defect image or a portion of an image and paste it into another image to create a synthetic defect in the other image.”)
Regarding claim 14, Riley in view of Inoue further in view of Woodward disclose “The method of claim 13,”
“wherein the generating of the defect image comprises generating, by the processor, ground truth (GT) data for training using the position which is inpainted using the defect pattern.” (Riley, Paragraph 11, “One embodiment relates to a system configured to train a machine learning model. The system includes one or more computer subsystems and one or more components executed by the one or more computer subsystems. The one or more components include a graphical user interface (GUI) configured for displaying one or more images for a specimen and image editing tools to a user. The GUI is also configured for receiving input from the user, which includes one or more alterations to at least one of the one or more images using one or more of the image editing tools. The component(s) also include an image processing module configured for applying the one or more alterations to the at least one of the one or more images thereby generating at least one modified image and storing the at least one modified image in a training set. The component(s) further include a machine learning model configured for performing one or more functions for the specimen using images generated for the specimen by an imaging subsystem. The computer subsystem(s) are configured for training the machine learning model with the training set in which the at least one modified image is stored. The system may be further configured as described herein.” Note that according to the above excerpt, the modified (inpainted) images are used for training as ground truth data. The inpainted images inherently include an inpainted defect at a position. Accordingly, the positional defect data is ‘used’ as part of the GT training data.)
Regarding claims 15-19, these claims recite a method with steps analogous to the steps recited in the method of claims 8, 9, and 11-14. Note that the claim 15 steps amount to a combination of the steps recited in both claims 8 and 9. Therefore, the recited steps of these claims are mapped to the analogous steps in the corresponding method claims. Additionally, the rationale and motivation to combine the references are applied here.
Regarding claims 2-7, these claims recite a system with elements analogous to the steps recited in the method of claims 9-14. Therefore, the recited elements of these claims are mapped to the analogous steps in the corresponding method claims. Additionally, the rationale and motivation to combine the references are applied here.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shabu (US20200226420A1) teaches generation of synthetic training images of a semiconductor specimen, wherein the generation is performed using a DNN.
Zhang (US20170148226A1) teaches a generative model with encoder and decoder layers configured for generating simulated images of a semiconductor specimen.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON JOSEPH SORRIN whose telephone number is (703)756-1565. The examiner can normally be reached Monday - Friday 9am - 5pm.
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/AARON JOSEPH SORRIN/
Examiner, Art Unit 2672
/SUMATI LEFKOWITZ/Supervisory Patent Examiner, Art Unit 2672
1 The courts consider a mental process (thinking) that “can be performed in the human mind, or by a human using a pen and paper” to be an abstract idea. CyberSource Corp. v. Retail Decisions, Inc., 654 F.3d 1366, 1372, 99 USPQ2d 1690, 1695 (Fed. Cir. 2011). MPEP 2106.04(a)(2)
Prosecution Insights