DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 – 12 and 14 – 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 6, 8, 12, and 13 of U.S. Patent No. 12,175,129. Although the claims at issue are not identical, they are not patentably distinct from each other because the application claims are anticipated by the patented claims as seen in the mapping below.
US Patent Number 12,175,129
Instant Application
1. A method, comprising: sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy and wherein the first notification is sent to a logic gate that routes the first notification from the logic gate to each of a number of memory controllers; blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment; sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy; and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.
1. A method, comprising: sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy; and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment.
3. The method of claim 1, further including sending the first notification from the physical layer to a logic gate that routes the first notification to each of the number of memory controllers.
6. The method of claim 1, further including sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy.
7. The method of claim 6, further including resuming processing commands on each of the number of memory controllers in response to receiving the second notification.
2. The method of claim 1, further including sending the first notification and the second notification on a side band bus.
2. The method of claim 1, further including sending the first notification on a side band bus.
10. The method of claim 9, further including sending the first notification on a side band bus.
4. The method of claim 1, further including sending an acknowledgement from one of the number of memory controllers to the physical layer in response to receiving the first notification.
4. The method of claim 1, further including sending an acknowledgement from one of the number of memory controllers to the physical layer in response to receiving the first notification.
12. The method of claim 9, further including sending an acknowledgement from one of the number of memory controllers to the physical layer in response to receiving the first notification.
6. The method of claim 1, further including performing a training operation on the physical layer while the commands are blocked on each of the number of memory controllers.
5. The method of claim 1, further including performing a training operation on the physical layer while the commands are blocked on each of the number of memory controllers.
9. A method, comprising: sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer has completed a training operation and is no longer busy; and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.
11. The method of claim 9, further including sending the first notification from the physical layer to a logic gate that routes the first notification to each of the number of memory controllers.
8. The method of claim 1, wherein each of the number memory controllers is associated with one of a number of physical layers and further including performing a training operation on each of the number of physical layers while the commands are blocked on each of the number of memory controllers.
8. The method of claim 1, wherein each of the number memory controllers is associated with one of a number of physical layers and further including performing a training operation on each of the number of physical layers while the commands are blocked on each of the number of memory controllers.
12. An apparatus, comprising: a central controller; a number of memory controllers coupled to the central controller via a data bus and a command bus, wherein each of the number of memory controllers include one of a number of physical layers; and a number of memory devices, wherein each particular memory device of the number of memory devices is coupled to a particular memory controller of the number of memory controllers, wherein the apparatus is configured to: send a first notification from a physical layer of the number of physical layers to each of the number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device of the number of memory devices coupled to the physical layer is busy and wherein the first notification is sent to a logic gate that routes the first notification from the logic gate to each of a number of memory controllers; block commands on each of the number of memory controllers in response to receiving the first notification; send a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy; and resume processing commands on each of the number of memory controllers in response to receiving the second notification.
14. An apparatus, comprising: a central controller; a number of memory controllers coupled to the central controller via a data bus and a command bus, wherein each of the number of memory controllers include one of a number of physical layers; and a number of memory devices, wherein each particular memory device of the number of memory devices is coupled to a particular memory controller of the number of memory controllers, wherein the apparatus is configured to: send a first notification from a physical layer of the number of physical layers to each of the number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device of the number of memory devices coupled to the physical layer is busy; and block commands on each of the number of memory controllers in response to receiving the first notification.
16. The apparatus of claim 14, wherein the first notification is sent from the physical layer to a logic gate that routes the first notification to each of the number of memory controllers.
18. The apparatus of claim 14, wherein the apparatus is configured to send a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy.
19. The apparatus of claim 18, wherein the apparatus is configured to resume processing commands on each of the number of memory controllers in response to receiving the second notification.
13. The apparatus of claim 12, wherein the first notification is sent from the physical layer to each of the number of memory controllers on a side band bus.
15. The apparatus of claim 14, wherein the first notification is sent from the physical layer to each of the number of memory controllers on a side band bus.
15. The apparatus of claim 12, wherein a training operation is performed on the physical layer while the commands are blocked on the number of memory controllers.
17. The apparatus of claim 14, wherein a training operation is performed on the physical layer while the commands are blocked on the number of memory controllers.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pappu et al. (US Publication Number 2023/0113953, hereinafter “Pappu”).
5. As per claims 1 and 14, Pappu teaches a method and apparatus (figures 3, 5, and 8), comprising: a central controller (320, figure 3); a number of memory controllers (mc0…23, 325, figure 3) coupled to the central controller via a data bus and a command bus (paragraph 68, buses 810, figure 8, interface bus 321, figure 3), wherein each of the number of memory controllers include one of a number of physical layers (PHY 0…11, 326, figure 3); and a number of memory devices (330, figure 3, devices, figure 8), wherein each particular memory device of the number of memory devices is coupled to a particular memory controller of the number of memory controllers (figure 3, connectivity seen between device and controller), wherein the apparatus (figures 7a…c) is configured to: send a first notification from a physical layer of the number of physical layers to each of the number of memory controllers (702, figure 5, paragraph 57, first notification of disabling), wherein the first notification indicates that the physical layer and/or a memory device of the number of memory devices coupled to the physical layer is busy (notification is to indicate a busy signal, paragraph 61); and block commands on each of the number of memory controllers in response to receiving the first notification (waits for completion and disables traffic in the busy duration, paragraph 61, figure 7c).
6. As per claim 9, Pappu teaches a method, comprising: sending a first notification (702, figure 7a and 7c) from a physical layer (PHY 0…11, 326, figure 3) to each of a number of memory controllers (723, figure 7b), wherein the first notification indicates that the physical layer has completed a training operation and is no longer busy (710, figure 7a and 7c, refresh signal after 706); and resuming processing commands on each of the number of memory controllers in response to receiving the second notification (714 and 716, figure 7a and 7c, paragraph 57, enable memory controller for data flow and re-enable communication between the MC and PHY).
7. As per claims 2, 10, and 15, Pappu teaches a method and apparatus, further including sending the first notification on a side band bus (paragraph 40).
8. As per claims 3, 11, and 16, Pappu teaches a method and apparatus, further including sending the first notification from the physical layer to a logic gate that routes the first notification to each of the number of memory controllers (321, figure 3, paragraph 39).
9. As per claims 4 and 12, Pappu teaches a method, further including sending an acknowledgement from one of the number of memory controllers to the physical layer in response to receiving the first notification (723 to 525, figure 7b).
10. As per claims 5 and 17, Pappu teaches a method and apparatus, further including performing a training operation on the physical layer while the commands are blocked on each of the number of memory controllers (404, memory training, paragraph 49).
11. As per claims 6 and 18, Pappu teaches a method and apparatus, further including sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy (710, figure 7a and 7c, refresh signal after 706).
12. As per claims 7 and 19, Pappu teaches a method and apparatus, further including resuming processing commands on each of the number of memory controllers in response to receiving the second notification (714 and 716, figure 7a and 7c, paragraph 57, enable memory controller for data flow and re-enable communication between the MC and PHY).
13. As per claim 8, Pappu teaches a method, wherein each of the number memory controllers is associated with one of a number of physical layers and further including performing a training operation on each of the number of physical layers while the commands are blocked on each of the number of memory controllers (404, memory training, paragraph 49).
14. As per claims 13 and 20, Pappu teaches a method and apparatus, receiving a command at each of the number of memory controllers and performing the command on each of the number of memory controllers in response to receiving the first notification at each of the number of memory controllers (command processing on each memory controller, paragraph 86).
Conclusion
15. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rastogi/Moro/Karamcheti/Ellis/Dearth have command handling with timing of the processing therein.
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/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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