DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 12 and 14 – 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 6, 8, 12, and 13 of U.S. Patent No. 12,175,129. Although the claims at issue are not identical, they are not patentably distinct from each other because the application claims are anticipated by the patented claims as seen in the mapping below.
US Patent Number 12,175,129
Instant Application
1. A method, comprising: sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy and wherein the first notification is sent to a logic gate that routes the first notification from the logic gate to each of a number of memory controllers; blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment; sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy; and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.
1. A method, comprising: sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy and wherein the first notification is sent to a logic gate that routes the first notification from the logic gate to each of a number of memory controllers; and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment.
3. The method of claim 1, further including sending the first notification from the physical layer to a logic gate that routes the first notification to each of the number of memory controllers.
6. The method of claim 1, further including sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy.
7. The method of claim 6, further including resuming processing commands on each of the number of memory controllers in response to receiving the second notification.
2. The method of claim 1, further including sending the first notification and the second notification on a side band bus.
2. The method of claim 1, further including sending the first notification on a side band bus.
10. The method of claim 9, further including sending the first notification on a side band bus.
4. The method of claim 1, further including sending an acknowledgement from one of the number of memory controllers to the physical layer in response to receiving the first notification.
4. The method of claim 1, further including sending an acknowledgement from one of the number of memory controllers to the physical layer in response to receiving the first notification.
12. The method of claim 9, further including sending an acknowledgement from one of the number of memory controllers to the physical layer in response to receiving the first notification.
6. The method of claim 1, further including performing a training operation on the physical layer while the commands are blocked on each of the number of memory controllers.
5. The method of claim 1, further including performing a training operation on the physical layer while the commands are blocked on each of the number of memory controllers.
9. A method, comprising: sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer has completed a training operation and is no longer busy; and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.
11. The method of claim 9, further including sending the first notification from the physical layer to a logic gate that routes the first notification to each of the number of memory controllers.
8. The method of claim 1, wherein each of the number memory controllers is associated with one of a number of physical layers and further including performing a training operation on each of the number of physical layers while the commands are blocked on each of the number of memory controllers.
8. The method of claim 1, wherein each of the number memory controllers is associated with one of a number of physical layers and further including performing a training operation on each of the number of physical layers while the commands are blocked on each of the number of memory controllers.
12. An apparatus, comprising: a central controller; a number of memory controllers coupled to the central controller via a data bus and a command bus, wherein each of the number of memory controllers include one of a number of physical layers; and a number of memory devices, wherein each particular memory device of the number of memory devices is coupled to a particular memory controller of the number of memory controllers, wherein the apparatus is configured to: send a first notification from a physical layer of the number of physical layers to each of the number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device of the number of memory devices coupled to the physical layer is busy and wherein the first notification is sent to a logic gate that routes the first notification from the logic gate to each of a number of memory controllers; block commands on each of the number of memory controllers in response to receiving the first notification; send a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy; and resume processing commands on each of the number of memory controllers in response to receiving the second notification.
14. An apparatus, comprising: a central controller; a number of memory controllers coupled to the central controller via a data bus and a command bus, wherein each of the number of memory controllers include one of a number of physical layers; and a number of memory devices, wherein each particular memory device of the number of memory devices is coupled to a particular memory controller of the number of memory controllers, wherein the apparatus is configured to: send a first notification from a physical layer of the number of physical layers to each of the number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device of the number of memory devices coupled to the physical layer is busy and wherein the first notification is sent to a logic gate that routes the first notification from the logic gate to each of a number of memory controllers; and block commands on each of the number of memory controllers in response to receiving the first notification.
16. The apparatus of claim 14, wherein the first notification is sent from the physical layer to a logic gate that routes the first notification to each of the number of memory controllers.
18. The apparatus of claim 14, wherein the apparatus is configured to send a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy.
19. The apparatus of claim 18, wherein the apparatus is configured to resume processing commands on each of the number of memory controllers in response to receiving the second notification.
13. The apparatus of claim 12, wherein the first notification is sent from the physical layer to each of the number of memory controllers on a side band bus.
15. The apparatus of claim 14, wherein the first notification is sent from the physical layer to each of the number of memory controllers on a side band bus.
15. The apparatus of claim 12, wherein a training operation is performed on the physical layer while the commands are blocked on the number of memory controllers.
17. The apparatus of claim 14, wherein a training operation is performed on the physical layer while the commands are blocked on the number of memory controllers.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pappu et al. (US Publication Number 2023/0113953, hereinafter “Pappu”) in view of MacLaren et al. (US Patent Number 10,642,538, hereinafter “MacLaren”).
5. As per claims 1 and 14, Pappu teaches a method and apparatus (figures 3, 5, and 8), comprising: a central controller (320, figure 3); a number of memory controllers (mc0…23, 325, figure 3) coupled to the central controller via a data bus and a command bus (paragraph 68, buses 810, figure 8, interface bus 321, figure 3), wherein each of the number of memory controllers include one of a number of physical layers (PHY 0…11, 326, figure 3); and a number of memory devices (330, figure 3, devices, figure 8), wherein each particular memory device of the number of memory devices is coupled to a particular memory controller of the number of memory controllers (figure 3, connectivity seen between device and controller), wherein the apparatus (figures 7a…c) is configured to: send a first notification from a physical layer of the number of physical layers to each of the number of memory controllers (702, figure 5, paragraph 57, first notification of disabling), wherein the first notification indicates that the physical layer and/or a memory device of the number of memory devices coupled to the physical layer is busy (notification is to indicate a busy signal, paragraph 61); and block commands on each of the number of memory controllers in response to receiving the first notification (waits for completion and disables traffic in the busy duration, paragraph 61, figure 7c).
Pappu does not appear to explicitly discloses wherein the first notification is sent to a logic gate that routes the first notification from the logic gate to each of the number of memory controllers.
However, MacLaren discloses wherein the first notification (via 250, figure 2) is sent to a logic gate (224, figure 2) that routes the first notification from the logic gate to each of the number of memory controllers (210-1, 210-2, figure 2, column 8, lines 20 – 63).
Pappu and MacLaren are analogous art because they are from the same field of endeavor memory controller handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pappu and MacLaren before him or her, to modify the signal handling of Pappu to include the routing mechanism of Maclaren because it would enhance multichannel memory handling.
One of ordinary skill would be motivated to make such modification in order to facilitate memory/PHY communication (column 1, lines 22- 30) Therefore, it would have been obvious to combine MacLaren with Pappu to obtain the invention as specified in the instant claims.
6. Pappu modified by the teachings of MacLaren as seen in claim 1 above, as per claim 9, Pappu teaches a method, comprising: sending a first notification (702, figure 7a and 7c) from a physical layer (PHY 0…11, 326, figure 3) to each of a number of memory controllers (723, figure 7b), wherein the first notification indicates that the physical layer has completed a training operation and is no longer busy (710, figure 7a and 7c, refresh signal after 706); and resuming processing commands on each of the number of memory controllers in response to receiving the second notification (714 and 716, figure 7a and 7c, paragraph 57, enable memory controller for data flow and re-enable communication between the MC and PHY).
7. Pappu modified by the teachings of MacLaren as seen in claim 1 above, as per claims 2, 10, and 15, Pappu teaches a method and apparatus, further including sending the first notification on a side band bus (paragraph 40).
8. Pappu modified by the teachings of MacLaren as seen in claim 1 above, as per claims 3, 11, and 16, Pappu teaches a method and apparatus, further including sending the first notification from the physical layer to a logic gate that routes the first notification to each of the number of memory controllers (321, figure 3, paragraph 39).
9. Pappu modified by the teachings of MacLaren as seen in claim 1 above, as per claims 4 and 12, Pappu teaches a method, further including sending an acknowledgement from one of the number of memory controllers to the physical layer in response to receiving the first notification (723 to 525, figure 7b).
10. Pappu modified by the teachings of MacLaren as seen in claim 1 above, as per claims 5 and 17, Pappu teaches a method and apparatus, further including performing a training operation on the physical layer while the commands are blocked on each of the number of memory controllers (404, memory training, paragraph 49).
11. Pappu modified by the teachings of MacLaren as seen in claim 1 above, as per claims 6 and 18, Pappu teaches a method and apparatus, further including sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy (710, figure 7a and 7c, refresh signal after 706).
12. Pappu modified by the teachings of MacLaren as seen in claim 1 above, as per claims 7 and 19, Pappu teaches a method and apparatus, further including resuming processing commands on each of the number of memory controllers in response to receiving the second notification (714 and 716, figure 7a and 7c, paragraph 57, enable memory controller for data flow and re-enable communication between the MC and PHY).
13. Pappu modified by the teachings of MacLaren as seen in claim 1 above, as per claim 8, Pappu teaches a method, wherein each of the number memory controllers is associated with one of a number of physical layers and further including performing a training operation on each of the number of physical layers while the commands are blocked on each of the number of memory controllers (404, memory training, paragraph 49).
14. Pappu modified by the teachings of MacLaren as seen in claim 1 above, as per claims 13 and 20, Pappu teaches a method and apparatus, receiving a command at each of the number of memory controllers and performing the command on each of the number of memory controllers in response to receiving the first notification at each of the number of memory controllers (command processing on each memory controller, paragraph 86).
Response to Arguments
15. Applicant’s arguments with respect to claims 1 – 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
16. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shimada/Chen/Kajihara/Karamcheti has teachings of memory controller signaling.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AURANGZEB HASSAN whose telephone number is (571)272-8625. The examiner can normally be reached 7 AM to 3 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
Prosecution Insights