Prosecution Insights
Last updated: October 01, 2026
Application No. 18/968,274

RANGE IMAGING ELEMENT AND RANGE IMAGING APPARATUS

Non-Final OA §103
Filed
Dec 04, 2024
Priority
Jun 06, 2022 — JP 2022-091696 +1 more
Examiner
HULKA, JAMES R
Art Unit
Tech Center
Assignee
Toppan Holdings Inc.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
1y 4m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
754 granted / 988 resolved
+16.3% vs TC avg
Moderate +12% lift
Without
With
+11.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
28 currently pending
Career history
1010
Total Applications
across all art units

Statute-Specific Performance

§101
6.7%
-33.3% vs TC avg
§103
56.3%
+16.3% vs TC avg
§102
18.7%
-21.3% vs TC avg
§112
14.5%
-25.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 988 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Isogai (US 20230154950) in view of Nakamura (US 2022/0373653). Regarding Claim 1, Isogai discloses a range imaging element [#22 of Fig 1; 0049], comprising: a pixel circuit configured to be positioned on a semiconductor substrate [#50, #100, #111 of Fig 5; 0105] and comprising a photoelectric converter [#122 of Fig 5; 0106], a charge storage [0069], at least one transfer MOS transistor [#52A, #52B of Fig 6; 0107], and at least one discharge MOS transistor [#53A, #53B, #54A, #54B of Fig 6; 0107], wherein the photoelectric converter is configured to generate electric charge corresponding to incident light received from a space [#122 of Fig 5; 0106], a charge storage is configured to store the electric charge generated by the photoelectric converter [0069], the at least one transfer MOS transistor is positioned on a transfer path of the electric charge being transferred from the photoelectric converter to the charge storage [#52A, #52B of Fig 6; 0107], the at least one discharge MOS transistor is positioned on a discharge path of the electric charge being discharged from the photoelectric converter [#52A, #52B of Fig 6; 0107], the photoelectric converter is positioned on the semiconductor substrate [#50, #100, #111 of Fig 5; 0105] and is N-gonal where N is an integer equal to or greater than 4 [Fig 6; 0107], the at least one transfer MOS transistor and the at least one discharge MOS transistor are positioned on sides of the photoelectric converter, respectively [Fig 6; 0107], and at least one of the at least one transfer MOS transistor and the at least one discharge MOS transistor has a tapered shape that has a width dimension parallel with a respective one of the sides [#52A, #52B of Fig 6; 0107] on which the at least one MOS transistor is positioned and gradually decreasing within the photoelectric converter away from the respective one of the sides of the photoelectric converter [Fig 6; 0107]. Regarding Claim 2, Isogai also discloses wherein the photoelectric converter has a planar shape of a rectangle with long sides and short sides [Fig 6; 0107], the at least one transfer MOS transistor comprises 2M transfer MOS transistors where M is an integer greater than or equal to 2 such that M of the 2M transfer MOS transistors are positioned on each of the long sides line symmetrically about an x-axis parallel with the long sides and extending through a center of the photoelectric converter [Fig 6; 0107], and the at least one discharge MOS transistor comprises 2n discharge MOS transistors where n is an integer equal to or greater than 1 such that n of the discharge MOS transistors are positioned on each of the short sides [Fig 6; 0107]. Regarding Claim 3, Isogai also discloses wherein the 2M transfer MOS transistors are positioned line symmetrically about a y-axis parallel with the short sides and extending through the center of the photoelectric converter [Fig 6; 0107]. Regarding Claim 7, Isogai also teaches a range imaging apparatus… and a range image processing unit comprising circuitry configured to calculate a distance from the range imaging element to a subject based on a range image taken by the range imaging element [0049] Claim(s) 4-6, 8-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Isogai (US 20230154950), as applied to Claim 1 above, and further in view of Nakamura (US 2022/0373653). Regarding Claim 4, Isogai does not explicitly teach – but Nakamura does teach wherein N is an integer equal to or greater than 5, the at least one transfer MOS transistor and the at least one discharge MOS transistor sum to N or more, and at least one of the at least one transfer MOS transistor is positioned on each side of the photoelectric converter except for a side on which the at least one discharge MOS transistor is positioned [Fig 3-5; 0133-36; 0139-40; 0152-55]. It would have been obvious to modify the element of Isogai to include specific positioning and number of sides of the polygon of the photoelectric converter as it is preferable to form the distribution transistors into a more ideal state in all light receiving elements in order to ensure high distance measurement accuracy. Regarding Claim 5, Isogai does not explicitly teach – but Nakamura does teach wherein the at least one transfer MOS transistor is positioned line symmetrically about an axis perpendicular to at least one of sides of the N-gon and extending through a center of the N-gon. [Fig 3-5; 0133-36; 0152-55]. It would have been obvious to modify the element of Isogai to include specific positioning and number of sides of the polygon of the photoelectric converter as it is preferable to form the distribution transistors into a more ideal state in all light receiving elements in order to ensure high distance measurement accuracy. Regarding Claim 6, Isogai does not explicitly teach – but Nakamura does teach a micro-lens positioned on a face of the pixel circuit to which the light is incident such that the micro-lens has an optical axis perpendicular to a plane of incidence of the photoelectric converter and is aligned with a center of the plane of incidence [Fig 10-13; 0101; 0161; 0178-84]. It would have been obvious to modify the element of Isogai to include a lens optically aligned with the center, in order to better allow the signal processing circuit to photoelectrically convert the formed optical image in units of pixels, reads a signal of each pixel as an imaging signal, and performs image processing to acquire a captured image. Regarding Claim 8, which is dependent on Claim 2, the rejection for Claim 4 above also applies to Claim 8, mutatis mutandis. Regarding Claim 9, which is dependent on Claim 2 and 8, the rejection for Claim 5 above also applies to Claim 9, mutatis mutandis. Regarding Claim 10, which is dependent on Claim 2, the rejection for Claim 6 above also applies to Claim 10, mutatis mutandis. Regarding Claim 11, which is dependent on Claim 2, the rejection for Claim 7 above also applies to Claim 11, mutatis mutandis. Regarding Claim 12, which is dependent on Claim 3, the rejection for Claim 4 above also applies to Claim 12, mutatis mutandis. Regarding Claim 13, which is dependent on Claim 3 and 12, the rejection for Claim 5 above also applies to Claim 13, mutatis mutandis. Regarding Claim 14, which is dependent on Claim 3, the rejection for Claim 6 above also applies to Claim 14, mutatis mutandis. Regarding Claim 15, which is dependent on Claim 3, the rejection for Claim 7 above also applies to Claim 15, mutatis mutandis. Regarding Claim 16, which is dependent on Claim 4, the rejection for Claim 6 above also applies to Claim 16, mutatis mutandis. Regarding Claim 17, which is dependent on Claim 4, the rejection for Claim 7 above also applies to Claim 17, mutatis mutandis. Regarding Claim 18, which is dependent on Claim 5, the rejection for Claim 6 above also applies to Claim 18, mutatis mutandis. Regarding Claim 19, which is dependent on Claim 5, the rejection for Claim 7 above also applies to Claim 19, mutatis mutandis. Regarding Claim 20, which is dependent on Claim 6, the rejection for Claim 7 above also applies to Claim 20, mutatis mutandis. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES R HULKA whose telephone number is (571)270-7553. The examiner can normally be reached M-R: 9am-6pm, F: 10am-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Helal Algahaim can be reached at 5712705227. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JAMES R. HULKA Primary Examiner Art Unit 3645 /JAMES R HULKA/Primary Examiner, Art Unit 3645
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Prosecution Timeline

Dec 04, 2024
Application Filed
Sep 24, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
88%
With Interview (+11.8%)
3y 1m (~1y 4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 988 resolved cases by this examiner. Grant probability derived from career allowance rate.

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