DETAILED ACTION
The instant action is in response to application 4 December 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title is not specific. Examiner Suggests LDO with Independent Miller Conpensation Entry and Exit Values.
Though the Italian reference appears to have the earliest filing date, and it is not technical required to have any other references listed, it is ordinary and customary to include copending applications filing date and their publication date (if available).
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Italy on 7 December 2023..
Claim Rejections - 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Van Ettinger (US 20140327416) in view of Buxton (US 6680837).
As to claim 11, A discloses (see annotated figure below) A method, comprising: generating an error signal at an intermediate node as a function of a difference between a first reference voltage and a regulator output voltage; amplifying the error signal to generate an amplified error signal; generating an output drive signal from the amplified error signal; controlling an output MOS transistor with the output drive signal to generate the regulator output voltage; comparing the output drive signal to a second reference voltage to generate a feedback current;
Van Ettinger does not explicitly teach and applying the feedback current to the intermediate node.
Butxton teaches (Figure 1) a method, comprising: generating an error signal (12) at an intermediate node (14) as a function of a difference between a first reference voltage (Vset) and a regulator output voltage (Vout); generating an output drive signal from the error signal; controlling an output MOS transistor (MN1) with the output drive signal to generate the regulator output voltage (Vout); comparing (CMP3) the output drive signal to a second reference voltage (Vthr3) to generate a feedback current (current through 30); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use current modification as disclosed in Butxton to protect the pass device.
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Claims 1, 7, 10, 12 is rejected under 35 U.S.C. 103 as being unpatentable over Van Ettinger (US 20140327416) in view of Buxton (US 6680837) and Xi (US 6600299).
As to calim 1, Van Etinger teaches A linear voltage regulator, comprising: an input supply terminal configured to receive an input supply voltage; a regulated output terminal configured to produce a regulated output voltage; a first amplification stage having a first input terminal coupled to a reference node to receive a first reference voltage and a second input terminal coupled to said regulated output terminal to receive said regulated output voltage, wherein the first amplification stage is configured to produce an error signal at an intermediate node; an intermediate amplification stage having an input terminal coupled to said intermediate node to receive said error signal and an output terminal configured to produce an amplified error signal at a further intermediate node; a driver stage configured to receive said amplified error signal and produce a drive signal as a function thereof; a pass device having a conductive channel arranged between said input supply terminal and said regulated output terminal, wherein a conductance of said pass device is controlled by said drive signal to produce said regulated output voltage (this is an apparatus coinciding with the method of claim 11 above);
Van Ettinger does not explicitly teach compensation capacitance coupled between said regulated output terminal and said intermediate node; a feedback circuit including a comparison circuit configured to compare said drive signal to a second reference voltage and produce a feedback current as a function of a difference between said drive signal and said second reference voltage; wherein said feedback current is sourced to said intermediate node to limit a gain of said first amplification stage.
Butxton teaches a feedback circuit including a comparison circuit configured to compare said drive signal to a second reference voltage and produce a feedback current as a function of a difference between said drive signal and said second reference voltage; wherein said feedback current is sourced to said intermediate node to limit a gain of said first amplification stage (this is similar to claim 11 above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use current modification as disclosed in Butxton to protect the pass device.
Xi teaches teach compensation capacitance coupled between said regulated output terminal and said intermediate node (Fig. 1, CC).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use miller compensation as disclosed in Xi to improve the rejection ratio.
As to claim 7, Van Ettinger in view of Buxton and Xi teaches wherein said intermediate amplification stage comprises an inverter circuit (broadly interpreted, 26 doubly inverts a signal) . As to claim 10, Van Ettinger in view of Buxton and Xi teaches wherein said pass device comprises a MOS transistor having a gate terminal configured to receive said drive signal (the pass device is a MOSFET).
As to claim 12, Van Bellinger in view of Buxton does not teach further comprising applying a Miller compensation capacitance between the regulator output voltage and the intermediate node.
Xi teaches further comprising applying a Miller compensation capacitance between the regulator output voltage and the intermediate node (Fig. 1, CC).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use miller compensation as disclosed in Xi to improve the rejection ratio.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Van Ettinger (US 20140327416) in view of Buxton (US 6680837) and Lin (US 20150185754).
As to claim 13, Van Ettinger in view of Buxton does not explicitly teach further comprising generating the second reference voltage by applying a first current through a diode-connected MOS transistor.
Lin teaches further comprising generating the second reference voltage by applying a first current through a diode-connected MOS transistor (claim 13/20). It has been held that art recognized equivalents are obvious (MPEP 2144.06).
As to claim 14, Van Ettinger in view of Buxton and Lin teaches further comprising biasing an amplifier configured to generate the amplified error signal with a second current (this would be taught either by the power current to the amplifier or by the current fed from the intermediate node, dependent upon interpretation).
As to claim 15, Van Ettinger in view of Buxton and Lin does not explicitly teach wherein the first current is larger than the second current. However, the currents can only be, equal, bigger, or smaller in magnitude. It has been held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007).
Claims 3-4, 6, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Van Ettinger (US 20140327416) in view of Buxton (US 6680837) and Xi (US 6600299 and Lin (US 20150185754).
As to claim 3, Van Ettinger in view of Buxton and Xi does not explicitly teach wherein said comparison circuit comprises a differential transistor pair including a first transistor having a control terminal configured to receive said second reference voltage, and a second transistor having a control terminal configured to receive said drive signal.
Lin teaches wherein said comparison circuit comprises a differential transistor pair including a first transistor having a control terminal configured to receive said second reference voltage, and a second transistor having a control terminal configured to receive said drive signal (112). It has been held that art recognized equivalents are obvious (MPEP 2144.06).
As to claim 4, Van Ettinger in view of Buxton and Lin teaches wherein said comparison circuit further comprises a second current generator configured to bias said differential transistor pair (transistors attached to point D).
As to claim 6, Van Ettinger in view of Buxton and Xi does not explicitly teach wherein said first amplification stage comprises: an input differential pair of transistors configured to receive said first reference voltage and said regulated output voltage; a biasing current mirror of transistors coupled to a biasing node of the input differential pair; and a load current mirror of transistors coupled to said input differential pair.
Lin teaches wherein said first amplification stage comprises: an input differential pair of transistors configured to receive said first reference voltage and said regulated output voltage; a biasing current mirror of transistors coupled to a biasing node of the input differential pair; and a load current mirror of transistors coupled to said input differential pair (112). It has been held that art recognized equivalents are obvious (MPEP 2144.06).
As to claim 8, Van Ettinger in view of Buxton and Xi does not explicitly teach wherein said intermediate amplification stage comprises a common source amplifier including a common source MOS transistor having a gate terminal configured to receive said error signal, and a further MOS transistor coupled in series with the common source MOS transistor; wherein the said amplified error signal is produced at node intermediate therebetween.
Lin teaches wherein said intermediate amplification stage comprises a common source amplifier including a common source MOS transistor having a gate terminal configured to receive said error signal, and a further MOS transistor coupled in series with the common source MOS transistor; wherein the said amplified error signal is produced at node intermediate therebetween (112). It has been held that art recognized equivalents are obvious (MPEP 2144.06)..
As to claim 13, Van Ettinger in view of Buxton and Xi does not explicitly teach further comprising generating the second reference voltage by applying a first current through a diode-connected MOS transistor.
Lin teaches further comprising generating the second reference voltage by applying a first current through a diode-connected MOS transistor (claim 13/20). It has been held that art recognized equivalents are obvious (MPEP 2144.06).
As to claim 14, Van Ettinger in view of Buxton and Lin teaches further comprising biasing an amplifier configured to generate the amplified error signal with a second current (this would be taught either by the power current to the amplifier or by the current fed from the intermediate node, dependent upon interpretation).
Allowable Subject Matter
Claims 5, 9 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 5, the prior art fails to disclose: “wherein said feedback circuit further includes a current mirror circuit comprising: a diode-connected transistor having a conductive channel coupled in series to a conductive channel of the first transistor of the differential transistor pair; and a mirroring transistor having a conductive channel coupled between said input supply terminal and said intermediate node, and having a control terminal connected to a control terminal of said diode-connected transistor.” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 9, the prior art fails to disclose: “wherein said driver stage comprises a common source stage including: a common source MOS transistor having a gate terminal configured to receive said amplified error signal; and a diode-connected driver MOS transistor having a gate terminal configured to produce said drive signal; wherein the common source MOS transistor and the diode-connected driver MOS transistor are coupled in series..” in combination with the additionally claimed features, as are claimed by the Applicant.
`Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839
Prosecution Insights