DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-30 of U.S. Patent No. US 12191883 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Limitations of current claim 1
corresponding limitations of claims 1, 4 and 5 in US 12191883 B2
Obtaining a set of information bits
The limitation starting “encode or decode the packet…” clearly suggests obtaining a set of information bits for encoding
generating a lifted low density parity check (LDPC) code via a lifling size value from a plurality of families of Hfting size values, each family of lifting size values being a product of a plurality of powers of two and an integer
Selected lifting value from a set/tower of lifting values based on a packet size of a packet to be encoded or decoded; Note: the next limitation recites: where in the set of lifting values is limited to lifting values that are each a different power two. Examiner would like to point out that the tower/set in claim 2 of the ‘249 patent also satisfies the following limitation: determining a lifting size value/lift size .from a tower of lifting size values {4, 8, 16, 32, 64, 128, 256, 512}, the tower lifting size values {4, 8, 16, 32, 64, 128, 256, 512}={2*2, 2*4, 2*8, 2*16, 2*32, 2*64, 2*128, 2*156} comprising a product 2*2n-1 of a plurality of powers 2n-1 of an integer 2 and a plurality of lifting size values n=2, 3, 4, 5, 6, 7, 8, 9).
Claim 5 recites: generate the lifted parity check matrix based further on cyclic shift values for the nonzero element of the base parity check matrix
applying a set of cyclic {fling values to interconnect edges in a number of coples of a base parity check matrix (PCM), the number of copies corresponding to the lifting size value,
Claim 5 recites: generate the lifted parity check matrix based further on cyclic shift values for the nonzero element of the base parity check matrix; Note: the 0 or 1 values in a lifted parity check matrix inherently identify interconnect edges for the number of copies generated corresponding to lifting size.
encoding the set of information bits based on the lifted LDPC code to produce one or wore codewords;
Claim 4 recites: encode or decode the packet based on the lifted parity check matrix
transmitting signaling associated with the one or more codewords in accordance with a radio technology across a wireless channel,
See Figure 2; note: the publication date of this patent is a valid 102(a)(1) priority date since it exceeds one year prior to the effective filing date of the current application
Citations
US 20110066916 A1 is directed to a method and apparatus for error correction encoding using a low density parity check LDPC family of codes; and, is a good teaching and or 103 reference.
US 20110047433 A1 is directed to a method and apparatus for error correction using a low density parity check algorithm for determining a low-density parity check matrix based on code length and code rate; and, is a good teaching reference.
US 20100257425 A1 is directed to a method and apparatus for error correction encoding using a low-density parity check LDPC family of codes that are generated should from a base matrix structure based on targeted lifting sizes and exciting constraints on girth, local girth and local minimum ACE; and, is a good teaching reference.
US 20090204868 A1 is directed to a method and apparatus for error correction using a low-density parity check code by determining lifting elements for a base parity check matrix based on information size and code length; and, is a good teaching reference.
US 20080178065 A1 is directed to an apparatus and method for generating an LDPC error correction code; and, was used in a 10d rejection, above.
US 20120166914 A1 is from the same family as US 20080178065 A1 with the same specification as US 20080178065 A1, which was used in a 102 rejection, above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D TORRES whose telephone number is (571)272-3829. The examiner can normally be reached Monday-Friday 10-7 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached on 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH D TORRES/Primary Examiner, Art Unit 2112
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