DETAILED ACTION
This action is responsive to the application filed 27 Jul 2026 and the Information Disclosure Statement filed 12 Feb 2025. Claims 2-21 are pending. Claims 2, 12, and 20 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed 27 Jul 2026 has been entered. Claims 2-21 are currently pending in the application.
Allowable Subject Matter
Claims 4, 8, 9, 15, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments filed on 27 Jul 2026 have been fully considered. Applicant’s arguments are not persuasive in regards to the 35 USC § 103 rejections as the claims are currently written. Arguments and corresponding examiner’s responses are shown below for independent Claim 1. The same arguments are valid for the similar features of the other independent claims.
Argument 1: The applicant states (page 13) “However, Takashima does not teach or suggest the "plurality of memory cells," for at least the reason that Takashima does not teach or suggest that "the second node [of the respective selection element] is connected with a bit line pillar of the plurality of bit line pillars," or that "the respective selection element is connected with the respective storage element and configured to selectively connect the respective storage element with the bit line pillar," as recited in independent claim 2.
First, Takashima depicts the resistance change element "RE" as separating the cell transistor "MT" from the local bit line "LBL," which is not the same as, and does not teach or suggest, "the second node [of the respective selection element] is connected with a bit line pillar," as recited in independent claim 2.
Response 1: The examiner respectfully disagrees. The terms “connected” is defined much more broadly in applicant’s specification than just a physical node to a physical node. Applicant’s specification (as published) paragraph 0124 states:
“[0124] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with ( or in conductive contact with or connected with or coupled with) one another if there is ANY conductive path between the components that can, at any time, support the flow of signals between the components.”
Thus, Takashima ONLY has to show that the associated memory transistor (MT) provides an electrical connection for a “conductive path” from the bitline (BL) through both the MT, the resistance change element (RE) to the source line (SL) to be “connected”, because the order of the MT and resistance change element (RE) in the claim are not specified as “node 1 connected to node 2 connected to node 3” type of claim limitation.
Argument 2: The applicant states (page 13) “Second, even if a resistance change element separating a transistor from a local bit line, as in Takashima, could be interpreted as "the second node [of the respective selection element] is connected with a bit line pillar," as recited in independent claim 1-which Applicant does not concede the constant electrical connection between the local bit line "LBL," the resistance change element "RE," and the cell transistor "MT" of Takashima does not teach or suggest "selectively connect[ing] the respective storage element with the bit line pillar," as recited in independent claim 2. Indeed, it would be impossible to "selectively connect" the local bit line "LBL" with the cell transistor "MT," as the resistance change element "RE" simply offers resistance without acting as a switch or gate.”
Response 2: The examiner respectfully disagrees. As cited above, the physical layout is consistent with applicant’s specification. Therefore Takashima teaches the claimed “position” of the MT by supporting the flow of signals. In this case, the MT has a gate which when “selected” can either block the electrical conductive pate or enable the electrical conductive path of the claimed circuit – therefore Takashima’s MT “is connected with the respective storage element… based at least in part on a second voltage of the word pillar of the plurality of word line pillars.” As written, the claimed circuit only requires the MT be “selectively connected” in any order to allow the voltage to complete the conductive path, in this case the path can be BL- RE- MT- SL, not that the MT have a physical position between the BL and the RE the circuit.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 2, 5 – 7, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Takashima, D., U.S. Patent Application Publication 2022/0399400 (“Takashima”) in view of Takaki, et al, U.S. Patent Application Publication 2016/0056210 (“Takaki”).
Regarding claim 2, Takashima teaches:
(New) An apparatus, comprising: a substrate; a plurality of plate lines; a plurality of bit line pillars connected with a bit line decoder; a plurality… word line decoder; and (Takashima, fig 2, 3, “[0087] The nonvolatile semiconductor memory device 1 includes a cell array 5, a row decoder 6, a sense amplifier 7, a peripheral circuit 8, … Each of the plurality of word lines is associated with a row address. Each of the plurality of bit lines is associated with a column address. [0094] As illustrated in FIG. 3, in the cell array 5, the columnar cell blocks CB are two-dimensionally arranged in the XY direction on the +Z side of a substrate 21, and a stacked body 22 is penetrated by the columnar cell blocks CB in the Z direction to form a three-dimensional arrangement of memory cells MC.”; a memory device with a substrate, word lines in a lateral pillar, word line drivers, bit lines in a vertical pillar, bit line drivers. Examiner’s Note: applicant’s specification paragraph [0124] states “Components are considered in electronic communication with ( or in conductive contact with or connected with or coupled with) one another if there is ANY conductive path between the components that can, at any time, support the flow of signals between the components.” Thus the components, unless further limited by a specified node to a specified node to a third specified node- do not require a physical order in their “connections”).
a plurality of memory cells each comprising a respective storage element and a respective selection element that comprises a first node, a second node, and a gate, (Takashima, fig 3, 4, “[0091] Each memory cell MC is configured by series connection of a resistance change element RE and a cell transistor MT.”; a memory array of “cell blocks”; each cell block has an individual cell transistor (i.e. selector element) and resistance change element).
wherein: the first node is connected with the respective storage element, the second node is connected with a bit line pillar of the plurality of bit line pillars, and the gate is connected with a word line pillar of the plurality of word line pillars; and (Takashima, fig 3, 4, 7, “[0092] At the time of an access operation to the resistance change element (resistance change film) RE, the select transistor SG of the select cell block CB is turned on, and the select transistor SG of the non-select cell block CB is kept off. In the select cell block CB, the cell transistor MT of the select memory cell MC is turned on, and the cell transistor MT of the non-select memory cell MC is kept off. [0096] In the stacked body 22, word lines WL and insulating layers 222 are alternately and repeatedly stacked in the Z direction. [0112] the memory cell MC is configured by series connection of the cell transistor MT connected to a word line WLi (i=O to 63) and a two-terminal resistance change element RE. [0065] A gate of the cell transistor is connected to a word line.”; a memory with a connection from the bit line to the storage element RE to the cell transistor MT to the local source line; that the gate of the MT is attached to the WL).
the respective selection element is connected with the respective storage element and configured to selectively connect the respective storage element with the bit line pillar of the plurality of bit line pillars based at least in part on a second voltage of the word line pillar of the plurality of word line pillars. (Takashima, fig 3, 4, 7, “[0092] In the select cell block CB, the cell transistor MT of the select memory cell MC is turned on, and the cell transistor MT of the non-select memory cell MC is kept off. … When a voltage is applied to the bit line BL and the source line SL, a cell current may flow in the path of the bit line BL->, the local bit line LBL->, the resistance change element RE of the select memory cell MC->, the cell transistor MT of the select memory cell MC the local source line LSL->, the source line SL.”; the MT (i.e. selection element) has a gate that is activated by the word line when allows current to flow through the memory cell selection element and RE storage element).
Takashima does not explicitly teach a plurality of word line pillars connected with a word line decoder.
Takaki teaches a plurality of word line pillars connected with a word line decoder (Takaki, fig 4D, “[0045] The word line connection regions 407 may also include a stack of an alternating plurality of electrically conductive layers (i.e., word line connection layers) and electrically insulating layers which may be continuous with the word lines 503 and insulating layers 505 of the word line stack 506 extending in the adjacent device regions 403. This is shown more clearly in FIGS. 4A-4D. The stack may be connected to the source regions 411 (see FIG. 2) of the word line select transistors 405 by the conductive vias 437.”; that word lines can be connected via a peripheral pillar to energize the word lines).
In view of the teachings of Takaki it would have been obvious for a person of ordinary skill in the art to apply the teachings of Takaki to Takashima before the effective filing date of the claimed invention in order to teach chalcogenide memory operations. The teachings of Takaki, in the same or in a similar field of endeavor with Takashima, can combine Takaki’s explicit word line pillar construction in the peripheral region and Takashima’s more general word line connections. The two connections to word lines merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 5, Takashima, as modified by Takaki, teaches (New) The apparatus of claim 2.
Takashima further teaches:
wherein: the respective selection element of each memory cell of the plurality of memory cells comprises a transistor; and (Takashima, fig 3, 4, “[0091] Each memory cell MC is configured by series connection of a resistance change element RE and a cell transistor MT.”; a memory array of “cell blocks”; each cell block has an individual cell transistor (i.e. selector element) and resistance change element).
the word line pillar of the plurality of word line pillars is connected with the transistor. (Takashima, fig 7, “[0112] As illustrated in the equivalent circuit diagram of FIG. 7, the memory cell MC is configured by series connection of the cell transistor MT connected to a word line WLi (i=O to 63) and a two-terminal resistance change element RE.”; a memory array of “cell blocks”; each cell block has an individual cell transistor (i.e. selector element); that the transistor is attached to the word line).
Regarding claim 6, Takashima, as modified by Takaki, teaches (New) The apparatus of claim 2.
Takashima further teaches wherein each bit line pillar of the plurality of bit line pillars is configured to be connected with a voltage source. (Takashima, fig 7, 1, “[0112] As illustrated in the equivalent circuit diagram of FIG. 7,… One of a plurality of memory cells MC0 to MC63 connected to word lines WL0 to WL63 is connected to the common local bit line (local bit lines LBL0 and LBLl) and the other is connected to the common local source line LSL in parallel connection. The local bit line LBL is connected to the bit lines BL0 and BLl via cell block select transistors SG0 and SGl. [0088] Under the control of the sequencer 10, the sense amplifier 6 can decode the address held in the address register 11 and select the bit line corresponding to the decoded column address.”; that the bit lines are driven by SG0 and SG1, that the sequencer 10 provides the power for the bit lines and selection gates during chip operations).
Regarding claim 7, Takashima, as modified by Takaki, teaches (New) The apparatus of claim 2.
Takashima further teaches wherein each bit line pillar of the plurality of bit line pillars is configured to be biased independently. (Takashima, fig 7, “[0079] (C) Third, one local bit line column and one local source line column may be disposed in each memory hole MH to form one cell block.”; that one bit line can have a singular local bit line for operations).
Regarding claim 10, Takashima, as modified by Takaki, teaches (New) The apparatus of claim 2.
Takashima further teaches:
further comprising: circuitry connected with the plurality of bit line pillars, the plurality of word line pillars, and the plurality of plate lines, the circuitry configured to: (Takashima, fig 1, 5, 6C, 8, “[0088] The sequencer 10 executes a command held in the command register 12 and controls a write operation or a read operation of data with respect to the cell array 5. Under the control of the sequencer 10, the row decoder 6 can decode the address held in the address register 11 and select the word line corresponding to the decoded row address. Under the control of the sequencer 10, the sense amplifier 6 can decode the address held in the address register 11 and select the bit line corresponding to the decoded column address.”; a memory array can be controlled by a plurality of bit lines and word lines for read and write operations).
couple, via the respective selection element of a target memory cell, the target memory cell with the bit line pillar of the plurality of bit line pillars associated with the target memory cell; (Takashima, fig 8, “[0114] It is assumed that (the potential of the bit line BL0)>(the potential of the source line SL) corresponding to the cell block CB0 on the left side in the drawing. As a result, the cell current selectively flows through the memory cell MCl corresponding to the select word line WLl, and the cell block CB0 may be read/written.”; that a ME is connected to the energized bit line and source line for a read operation).
apply a read voltage between a plate line of the plurality of plate lines associated with the target memory cell and the bit line pillar of the plurality of bit line pillars associated with the target memory cell; and (Takashima, fig 8, “[0114] FIG. 8 is a circuit diagram illustrating the operation of the cell block CB, and a current path when the select word line is WLl is indicated by an alternate long and short dash line.”; that applying a read voltage to the associated bit line allows current to flow through the read circuit).
determine a logic state of a set of logic states, the logic state stored by the target memory cell based at least in part on a current through the target memory cell that is responsive to the read voltage. (Takashima, fig 8, “[0114] At this time, since the current amount changes in accordance with the resistance state (set/reset state) of the resistance change film RE, the read operation becomes possible.”; that the RE from the memory element allows the read operation to determine the logic state of a read memory cell).
Regarding claim 11, Takashima, as modified by Takaki, teaches (New) The apparatus of claim 2.
Takashima further teaches further comprising: a first selection element and a second selection element comprising a source contact connected with a common bit line pillar of the plurality of bit line pillars. (Takashima, fig 3, 8, “[0065] The cell block includes a plurality of memory cells and a select transistor. The plurality of memory cells is connected in parallel between the local source line and the local bit line corresponding to the plurality of word lines. The select transistor is connected between the local bit line and the bit line. The local bit line LBL is connected to the bit lines BL0 and BLl via cell block select transistors SG0 and SGl.”; at least three selection elements for each memory cell: a select transistor between the global bit line and local bit lines, a select transistor to select the individual bit lines of that memory block, and the individual word line attached to the gate of the SE at the source/drain to read the individual cell).
Claims 3, 12 – 14, 16, and 18 – 21 are rejected under 35 U.S.C. 103 as being unpatentable over Takashima, as modified by Takaki, in view of Pirovano, et al, U.S. Patent Application Publication 2020/0243136 (“Pirovano”).
Regarding claim 3, Takashima, as modified by Takaki, teaches (New) The apparatus of claim 2.
Takashima, as modified by Takaki, does not explicitly teach wherein: the respective storage element is configured to have a first threshold voltage when a first applied voltage has a first polarity and a second threshold voltage when the first applied voltage has a second polarity; and the first threshold voltage and the second threshold voltage respectively correspond to a first logic state and a second logic state of a set of logic states..
Pirovano teaches wherein: the respective storage element is configured to have a first threshold voltage when a first applied voltage has a first polarity and a second threshold voltage when the first applied voltage has a second polarity; and the first threshold voltage and the second threshold voltage respectively correspond to a first logic state and a second logic state of a set of logic states. (Pirovano, fig 2, 3, “[0082] In one example, when the target memory cell 105-a-ll has been selected for a write operation, the voltage difference across the material portion 220-a-ll ( e.g., V BL H-V sL L) may be selected to have a magnitude that is high enough to write a desired logic state. … In the example of timing diagram 300, the voltage across the material portion 220-a-ll may have a positive polarity ( e.g., where a voltage at the first node 221-a-ll is higher than a voltage at the second node 222-a-11), which may be associated with writing a particular logic state ( e.g., a logic state different than a logic state that would be written with a negative polarity).”; a chalcogenide memory that has two voltage thresholds with separate polarities respectively for two logic states).
In view of the teachings of Pirovano it would have been obvious for a person of ordinary skill in the art to apply the teachings of Pirovano to Takashima before the effective filing date of the claimed invention in order to teach chalcogenide memory cell operations. The teachings of Pirovano, in the same or in a similar field of endeavor with Takashima, can combine Pirovano’s dual polarity writing with Takashima’s less descriptive programming The two writing methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 12, Takashima teaches:
(New) A method, comprising: identifying a memory cell that comprises a selection element comprising a first node connected with a storage element, a second node connected with a bit line pillar of a plurality of bit line pillars, and a gate connected with a word line… (Takashima, fig 3, 4, “[0087] The nonvolatile semiconductor memory device 1 includes a cell array 5, a row decoder 6, a sense amplifier 7, a peripheral circuit 8, … Each of the plurality of word lines is associated with a row address. Each of the plurality of bit lines is associated with a column address. [0091] Each memory cell MC is configured by series connection of a resistance change element RE and a cell transistor MT. [0094] As illustrated in FIG. 3, in the cell array 5, the columnar cell blocks CB are two-dimensionally arranged in the XY direction on the +Z side of a substrate 21, and a stacked body 22 is penetrated by the columnar cell blocks CB in the Z direction to form a three-dimensional arrangement of memory cells MC.”; a memory array of “cell blocks”; each cell block has an individual cell transistor (i.e. selector element) and resistance change element connected to bit and word line pillars).
connecting, via the selection element of the memory cell, the memory cell with the bit line pillar of the plurality of bit line pillars, (Takashima, fig 3, 4, 7, “[0092] At the time of an access operation to the resistance change element (resistance change film) RE, the select transistor SG of the select cell block CB is turned on, and the select transistor SG of the non-select cell block CB is kept off. In the select cell block CB, the cell transistor MT of the select memory cell MC is turned on, and the cell transistor MT of the non-select memory cell MC is kept off. [0096] In the stacked body 22, word lines WL and insulating layers 222 are alternately and repeatedly stacked in the Z direction. [0112] the memory cell MC is configured by series connection of the cell transistor MT connected to a word line WLi (i=O to 63) and a two-terminal resistance change element RE. [0065] A gate of the cell transistor is connected to a word line.”; a memory with a connection from the bit line to the storage element RE to the cell transistor MT to the local source line; that the gate of the MT is attached to the WL).
wherein the connecting is based at least in part on an activation voltage applied to the selection element via the word line pillar of the plurality of word line pillars; and (Takashima, fig 3, 4, 7, “[0092] In the select cell block CB, the cell transistor MT of the select memory cell MC is turned on, and the cell transistor MT of the non-select memory cell MC is kept off. … When a voltage is applied to the bit line BL and the source line SL, a cell current may flow in the path of the bit line BL->, the local bit line LBL->, the resistance change element RE of the select memory cell MC->, the cell transistor MT of the select memory cell MC the local source line LSL->, the source line SL.”; the MT (i.e. selection element) has a gate that is activated by the word line when allows current to flow through the memory cell selection element and RE storage element).
Takashima does not explicitly teach:
writing, to the memory cell, a first logic state of a set of logic states based at least in part on a polarity of a write voltage applied between a plate line coupled with the memory cell and the bit line pillar of the plurality of bit line pillars.
(a gate connected to a word line) pillar of a plurality of word line pillars;.
Takaki teaches (a gate connected to a word line) pillar of a plurality of word line pillars; (Takaki, fig 4D, “[0045] The word line connection regions 407 may also include a stack of an alternating plurality of electrically conductive layers (i.e., word line connection layers) and electrically insulating layers which may be continuous with the word lines 503 and insulating layers 505 of the word line stack 506 extending in the adjacent device regions 403. This is shown more clearly in FIGS. 4A-4D. The stack may be connected to the source regions 411 (see FIG. 2) of the word line select transistors 405 by the conductive vias 437.”; that word lines can be connected via a peripheral pillar to energize the word lines).
In view of the teachings of Takaki it would have been obvious for a person of ordinary skill in the art to apply the teachings of Takaki to Takashima before the effective filing date of the claimed invention in order to teach chalcogenide memory operations. The teachings of Takaki, in the same or in a similar field of endeavor with Takashima, can combine Takaki’s explicit word line pillar construction in the peripheral region and Takashima’s more general word line connections. The two connections to word lines merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Pirovano teaches writing, to the memory cell, a first logic state of a set of logic states based at least in part on a polarity of a write voltage applied between a plate line coupled with the memory cell and the bit line pillar of the plurality of bit line pillars. (Pirovano, fig 2, 3, “[0082] In one example, when the target memory cell 105-a-ll has been selected for a write operation, the voltage difference across the material portion 220-a-ll ( e.g., V BL H-V sL L) may be selected to have a magnitude that is high enough to write a desired logic state. … In the example of timing diagram 300, the voltage across the material portion 220-a-ll may have a positive polarity ( e.g., where a voltage at the first node 221-a-ll is higher than a voltage at the second node 222-a-11), which may be associated with writing a particular logic state ( e.g., a logic state different than a logic state that would be written with a negative polarity).”; a chalcogenide memory that has two voltage thresholds with separate polarities respectively for two logic states).
In view of the teachings of Pirovano it would have been obvious for a person of ordinary skill in the art to apply the teachings of Pirovano to Takashima before the effective filing date of the claimed invention in order to teach chalcogenide memory cell operations. The teachings of Pirovano, in the same or in a similar field of endeavor with Takashima, can combine Pirovano’s dual polarity writing with Takashima’s less descriptive programming The two writing methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 13, Takashima, as modified by Takaki and Pirovano, teaches (New) The method of claim 12.
Takashima further teaches further comprising: isolating, during the writing to the memory cell, a second memory cell from the bit line pillar of the plurality of bit line pillars via a second selection element of the second memory cell. (Takashima, fig 7, 8, “[0112] The local bit line LBL is connected to the bit lines BL0 and BLl via cell block select transistors SG0 and SGl. With this configuration, by turning on the cell block select transistors SG0 and SG3 to select the cell blocks CB0 and CB3 and turning on the cell transistor MT connected to the select word line WL in the select cell blocks CB0 and CB3, voltage application and current application can be selectively performed to the resistance change element RE of the select memory cell MC”; that local bit lines are energized, that individual word lines are energized to isolate all other neighboring memory cells while reading resistance levels in the desired memory cell).
Regarding claim 14, Takashima, as modified by Takaki and Pirovano, teaches (New) The method of claim 12.
Takashima further teaches:
wherein the writing comprises: applying a first voltage to the plate line; and (Takashima, fig 8, “[0114] Alternatively, as illustrated in FIG. 8, the potential of the bit line BLl corresponding to the cell block CB3 on the right side in the drawing is set to a fixed potential equal to the source line SL potential, and a voltage is applied to the select word line WL1.”; that reading and writing can be accomplished by powering the associated bit lines and word lines for a memory cell).
applying a second voltage that is different than the first voltage to the bit line pillar of the plurality of bit line pillars. (Takashima, fig 8, “It is assumed that (the potential of the bit line BL0)>(the potential of the source line SL) corresponding to the cell block CB0 on the left side in the drawing. As a result, the cell current selectively flows through the memory cell MCl corresponding to the select word line WLl, and the cell block CB0 may be read/written.”; that the bit line voltage applied and the source line voltage applied create a current; that the current is used to read or write the cell logic value).
Regarding claim 16, Takashima, as modified by Takaki and Pirovano, teaches (New) The method of claim 12.
Pirovano further teaches wherein the memory cell has a first threshold voltage when the polarity of the write voltage is a first polarity and a second threshold voltage when the polarity of the write voltage is a second polarity. (Pirovano, fig 2, 3, “[0082] In one example, when the target memory cell 105-a-ll has been selected for a write operation, the voltage difference across the material portion 220-a-ll ( e.g., V BL H-V sL L) may be selected to have a magnitude that is high enough to write a desired logic state. … In the example of timing diagram 300, the voltage across the material portion 220-a-ll may have a positive polarity ( e.g., where a voltage at the first node 221-a-ll is higher than a voltage at the second node 222-a-11), which may be associated with writing a particular logic state ( e.g., a logic state different than a logic state that would be written with a negative polarity).”; a chalcogenide memory that has two voltage thresholds with separate polarities respectively for two logic states).
In view of the teachings of Pirovano it would have been obvious for a person of ordinary skill in the art to apply the teachings of Pirovano to Takashima before the effective filing date of the claimed invention in order to teach chalcogenide memory cell operations. The teachings of Pirovano, in the same or in a similar field of endeavor with Takashima, can combine Pirovano’s dual polarity writing with Takashima’s less descriptive programming The two writing methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 18, Takashima, as modified by Takaki and Pirovano, teaches (New) The method of claim 12.
Takashima further teaches:
wherein: the selection element comprises a transistor; and (Takashima, fig 3, 4, “[0091] Each memory cell MC is configured by series connection of a resistance change element RE and a cell transistor MT.”; a memory array of “cell blocks”; each cell block has an individual cell transistor (i.e. selector element) and resistance change element).
the word line pillar of the plurality of word line pillars is connected with a gate of the transistor. (Takashima, fig 7, 8, “[0112] As illustrated in the equivalent circuit diagram of FIG. 7, the memory cell MC is configured by series connection of the cell transistor MT connected to a word line WLi (i=O to 63) and a two-terminal resistance change element RE.”; a memory array of “cell blocks”; each cell block has an individual cell transistor (i.e. selector element); that the transistor is attached to the word line).
Regarding claim 19, Takashima, as modified by Takaki and Pirovano, teaches (New) The method of claim 12.
Takashima further teaches wherein the selection element and a second selection element of a second memory cell comprise a common source contact connected with the bit line pillar of the plurality of bit line pillars. (Takashima, fig 7, 8, “[0112] As illustrated in the equivalent circuit diagram of FIG. 7, the memory cell MC is configured by series connection of the cell transistor MT connected to a word line WLi (i=O to 63). One of a plurality of memory cells MC0 to MC63 connected to word lines WL0 to WL63 is connected to the common local bit line (local bit lines LBL0 and LBLl) and the other is connected to the common local source line LSL in parallel connection.”; that the memory cells can have a selection element attached to each of the local bit lines as described above; that the two columns of memory cells have a common source line connected to the memory array).
Regarding claim 20, Takashima teaches:
(New) A method, comprising: identifying a memory cell that comprises a selection element comprising a first node connected with a storage element, a second node connected with a bit line pillar of a plurality of bit line pillars, and a gate connected with a word line … (Takashima, fig 3, 4, “[0087] The nonvolatile semiconductor memory device 1 includes a cell array 5, a row decoder 6, a sense amplifier 7, a peripheral circuit 8, … Each of the plurality of word lines is associated with a row address. Each of the plurality of bit lines is associated with a column address. [0091] Each memory cell MC is configured by series connection of a resistance change element RE and a cell transistor MT. [0094] As illustrated in FIG. 3, in the cell array 5, the columnar cell blocks CB are two-dimensionally arranged in the XY direction on the +Z side of a substrate 21, and a stacked body 22 is penetrated by the columnar cell blocks CB in the Z direction to form a three-dimensional arrangement of memory cells MC.”; a memory array of “cell blocks”; each cell block has an individual cell transistor (i.e. selector element) and resistance change element connected to bit and word line pillars).
connecting, via the selection element of the memory cell, the memory cell with the bit line pillar of the plurality of bit line pillars, (Takashima, fig 3, 4, 7, “[0092] At the time of an access operation to the resistance change element (resistance change film) RE, the select transistor SG of the select cell block CB is turned on, and the select transistor SG of the non-select cell block CB is kept off. In the select cell block CB, the cell transistor MT of the select memory cell MC is turned on, and the cell transistor MT of the non-select memory cell MC is kept off. [0096] In the stacked body 22, word lines WL and insulating layers 222 are alternately and repeatedly stacked in the Z direction. [0112] the memory cell MC is configured by series connection of the cell transistor MT connected to a word line WLi (i=O to 63) and a two-terminal resistance change element RE. [0065] A gate of the cell transistor is connected to a word line.”; a memory with a connection from the bit line to the storage element RE to the cell transistor MT to the local source line; that the gate of the MT is attached to the WL).
wherein the connecting is based at least in part on an activation voltage applied to the selection element via the word line pillar of the plurality of word line pillars; (Takashima, fig 3, 4, 7, “[0092] In the select cell block CB, the cell transistor MT of the select memory cell MC is turned on, and the cell transistor MT of the non-select memory cell MC is kept off. … When a voltage is applied to the bit line BL and the source line SL, a cell current may flow in the path of the bit line BL->, the local bit line LBL->, the resistance change element RE of the select memory cell MC->, the cell transistor MT of the select memory cell MC the local source line LSL->, the source line SL.”; the MT (i.e. selection element) has a gate that is activated by the word line when allows current to flow through the memory cell selection element and RE storage element).
applying a read voltage across the memory cell, wherein applying the read voltage comprises applying a first voltage to a plate line coupled with the memory cell and applying a second voltage to the bit line pillar of the plurality of bit line pillars; and determining a first logic state stored by the memory cell based at least in part on applying the read voltage, (Takashima, fig 7, 8, “[0114] FIG. 8 is a circuit diagram illustrating the operation of the cell block CB, and a current path when the select word line is WLl is indicated by an alternate long and short dash line. At this time, since the current amount changes in accordance with the resistance state (set/reset state) of the resistance change film RE, the read operation becomes possible.”; that a memory cell can be read based on the resistance state of the cell).
Takashima does not explicitly teach:
the first logic state based at least in part on a threshold voltage of the memory cell.
(a gate connected with a word line) pillar of a plurality of word line pillars;.
Takaki teaches (a gate connected with a word line) pillar of a plurality of word line pillars; (Takaki, fig 4D, “[0045] The word line connection regions 407 may also include a stack of an alternating plurality of electrically conductive layers (i.e., word line connection layers) and electrically insulating layers which may be continuous with the word lines 503 and insulating layers 505 of the word line stack 506 extending in the adjacent device regions 403. This is shown more clearly in FIGS. 4A-4D. The stack may be connected to the source regions 411 (see FIG. 2) of the word line select transistors 405 by the conductive vias 437.”; that word lines can be connected via a peripheral pillar to energize the word lines).
In view of the teachings of Takaki it would have been obvious for a person of ordinary skill in the art to apply the teachings of Takaki to Takashima before the effective filing date of the claimed invention in order to teach chalcogenide memory operations. The teachings of Takaki, in the same or in a similar field of endeavor with Takashima, can combine Takaki’s explicit word line pillar construction in the peripheral region and Takashima’s more general word line connections. The two connections to word lines merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Pirovano teaches the first logic state based at least in part on a threshold voltage of the memory cell. (Pirovano, fig 11, “[0170] At 1120, the memory device may determine a logic state stored by the memory cell based on applying the read voltage, the logic state based on a threshold voltage of the chalcogenide material of the memory cell.”; that a “threshold” voltage can be applied when reading a chalcogenide memory cell with two states of resistance).
In view of the teachings of Pirovano it would have been obvious for a person of ordinary skill in the art to apply the teachings of Pirovano to Takashima before the effective filing date of the claimed invention in order to teach chalcogenide memory cell operations. The teachings of Pirovano, in the same or in a similar field of endeavor with Takashima, can combine Pirovano’s threshold voltage to read a memory cell with Takashima’s less descriptive reading of figure 8. The two reading methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 21, Takashima, as modified by Takaki and Pirovano, teaches (New) The method of claim 20.
Takashima further teaches further comprising: isolating, during the applying of the read voltage across the memory cell, a second memory cell from the bit line pillar of the plurality of bit line pillars via a second selection element of the second memory cell. (Takashima, fig 7, 8, “[0114] Alternatively, as illustrated in FIG. 8, the potential of the bit line BLl corresponding to the cell block CB3 on the right side in the drawing is set to a fixed potential equal to the source line SL potential, and a voltage is applied to the select word line WLl.”; that a fixed potential is set across BL1 and the SL such that the second memory cell is isolated from the read operation on MC1).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
