DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/4/2024 has been considered by the examiner.
Election/Restrictions
Applicant's election of Group I, Claims 1-10, without traverse in the reply filed on 07/14/2026 is acknowledged.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet preferably within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc. In addition, the form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided.
The abstract of the disclosure is objected to because it uses implied phrases such as “The present disclosure relates to” and “This disclosure also provides”. Correction is required. See MPEP § 608.01(b).
Claim Objection
Claim 1 is objected to because of the following informalities:
Claim 1: please amend “the electrodes” to -- the plurality of electrodes --; “defining a plurality of electrodes” to --defining [[a]] the plurality of electrodes--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Cui et al. (Single grain boundary break junction for suspended nanogap electrodes with gapwidth down to 1-2 nm by focused ion beam milling, Advanced Materials, 2015, 27, 3002-3006), and in view of Demirkol (Development of nanogap fabrication method for applications in nanoelectromechanical systems and nanoelectronics, PhD thesis of Sabanci University, 2013).
Regarding claim 1, Cui teaches a method for manufacturing a plurality of electrodes wherein the electrodes comprise noble metal (Fig.2 shows a method for fabricating two Au electrodes with a nanograp [title and abstract]), the method comprising:
providing a substrate having a dielectric layer in physical contact therewith (providing a silicon substrate having a dielectric layer of 300 nm SiO2 in physical contact therewith [the 2nd paragraph in Col.1 on page 3003; Fig.2]);
wherein the dielectric layer comprises at least a sacrificial part (the SiO2 under the edge of the Au is removed [the 2nd paragraph in Col.1 on page 3003]; see the formed cavity/recess in the SiO2 layer in Fig.2b-1; thus the SiO2 layer comprising at least a sacrificial part for forming the cavity/recess]), wherein the sacrificial part comprises a top surface (the sacrificial part of the SiO2 layer corresponds to the removed SiO2 layer to form the cavity/recess, and it has a top surface in contact with the Au layer);
forming a conductive layer on the dielectric layer and in physical contact with the top surface of the sacrificial part (Au layer on the SiO2 layer as shown in Fig.2), wherein the conductive layer comprises the noble metal (Au layer comprises the noble metal of Au);
providing a masking layer (resist in Fig.2) over the conductive layer (see Fig.2) ;
patterning the masking layer to expose at least the conductive layer above the sacrificial part thereby defining a plurality of electrodes wherein the smallest distance between the plurality of electrodes is not larger than 500 nm (EBL and RIE are used to pattern the Au films into desired conditions [the 2nd paragraph in Col. 1 on page 3003]; Fig.2a shows patterning the masking layer to expose at least the conductive layer above the sacrificial part thereby defining a plurality of electrodes wherein the smallest distance between the plurality of electrodes is not larger than 500 nm; nanogap electrodes with gapwidth down to 1-2 nm [title]);
etching the conductive layer by ion-beam thereby forming the plurality of electrodes comprising the noble metal (Fig.2b shows etching the Au layer by FIB to form two Au electrodes separated by a nanogap);
etching at least a portion of the sacrificial part (Fig.2 shows etching at least a portion of the SiO2 layer by HF to form a suspended Au wire [the 2nd paragraph in Col.1 on page 3003]); and
removing the masking layer (the masking layer must be removed since the final device comprises suspended nanogap electrodes on the substrate as shown in Fig.3. This limitation will be further rejected in view of Demirkol in the following).
Cui teaches etching at least a portion of the sacrificial part by using HF solution instead of by dry etching.
Demirkol teaches fabrication methods to fabricate electrodes separated with nanogap (title and section 4.2), and further teaches dry etching for the anisotropic etching of the insulating layers like Si3N4 and SiO2 (section 4.2.5 on page 47). Demirkol further teaches removing mask after patterning (see Fig.4.5 wherein the mask is removed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the step of etching at least a portion of the sacrificial part in Cui to etching at least a portion of the sacrificial part by dry etching, as taught by Demirkol, since it would allow for the anisotropic etching of the insulating layer such as SiO2 (corresponding to the sacrificial part of SiO2) (section 4.2.5 on page 47 in Demirkol).
Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove the mask after patterning, as taught by Demirkol, since it would expose the electrodes with nanogap for single molecular devices (Fig.3 and the last paragraph in Col. 2 on page 3005 in Cui).
The limitation “such that resistance at the smallest distance between the plurality of electrodes is at least 1e8 ohm” is an intended result of a positively recited step. The court noted that a "‘whereby clause in a method claim is not given weight when it simply expresses the intended result of a process step positively recited.’" Id. (quoting Minton v. Nat’l Ass’n of Securities Dealers, Inc., 336 F.3d 1373, 1381, 67 USPQ2d 1614, 1620 (Fed. Cir. 2003)).
Regarding claim 2, modified Cui teaches the method according to claim 1, and Cui teaches wherein the sacrificial part comprises a protruded structure of the dielectric layer (Fig.2 shows the sacrificial part of the SiO2 layer comprises a protruded structure of the dielectric layer to provide the cavity/recess beneath the Au film).
Regarding claim 4, modified Cui teaches the method according to claim 2, wherein etching at least a portion of the sacrificial part by dry etching comprises reactive ion etching (Demirkol teaches wherein the dry etching comprises reactive ion etching using DSE PM 2000 ICP-RIE system [section 4.2.5]).
Regarding claim 5, modified Cui teaches the method according to claim 1, and Cui teaches wherein a top surface of the dielectric layer is planar and the top surface of the sacrificial part is coplanar with a surrounding top surface of the dielectric layer (Fig.2b-1 shows a top surface of the dielectric SiO2 layer is planar and the top surface of the sacrificial part [top surface of the removed SiO2 layer between the Si layer and the Au film to form the cavity/recess] is coplanar with a surrounding top surface of the dielectric SiO2 layer), wherein etching at least a portion of the sacrificial part by dry etching comprises reactive ion etching (Demirkol teaches wherein the dry etching comprises reactive ion etching using DSE PM 2000 ICP-RIE system [section 4.2.5]).
Regarding claim 6, modified Cui teaches the method according to claim 1, and Cui teaches wherein the noble metal is gold (Au) (Au in Fig.2).
Regarding claim 7, modified Cui teaches the method according to claim 1, and Cui teaches wherein the dielectric layer comprises SiO2 (SiO2 in Fig.2).
Regarding claim 9, modified Cui teaches the method according to claim 1, wherein etching at least a portion of the sacrificial part by dry etching is performed such that a recessed region in the dielectric layer is obtained between the plurality of electrodes (Fig.2b-1 in Cui shows a recessed region in the SiO2 layer is obtained between the two Au electrodes to form a nanogap down to 1-2 nm [title and Fig.2b1 in Cui]).
Regarding claim 10, modified Cui teaches the method according to claim 1, and Cui teaches wherein the sacrificial part is recessed for at least 20 nm with regard to the top surface after the step of etching at least a portion of the sacrificial part by dry etching (the thickness of the SiO2 layer is 300 nm [the 2nd paragraph in Col.1 on page 3003 in Cui], and Fig.2b-1 of Cui shows the sacrificial part of the SiO2 layer is removed in the entire thickness of the SiO2 layer to form the cavity/recess between the Si layer and the Au film, thus the sacrificial part is recessed for 300 nm with regard to the top surface after the step of etching at least a portion of the sacrificial part by dry etching);
and “such that the resistance at the smallest distance between the plurality of electrodes is at least 1e8 ohm” is an intended result of a positively recited step. The court noted that a "‘whereby clause in a method claim is not given weight when it simply expresses the intended result of a process step positively recited.’" Id. (quoting Minton v. Nat’l Ass’n of Securities Dealers, Inc., 336 F.3d 1373, 1381, 67 USPQ2d 1614, 1620 (Fed. Cir. 2003)).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cui and Demirkol, as applied to claim 2 above, and further in view of Desbiolles et al. (Ion beam etching redeposition for 3D multimaterial nanostructure manufacturing, Microsystems & Nanoengineering, 2019, 5, 11).
Regarding claim 3, modified Cui teaches the method according to claim 2, and is silent to wherein etching at least a portion of the sacrificial part by dry etching comprises ion-beam etching.
Desbiolles teaches selectively etching Si/SiO2 using the ion beam dry etching technique (see caption of Fig.3; the 2nd paragraph in Col. 1 on page 4 to the 2nd paragraph in Col.2 on page 4; title).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the ion-beam etching technique to etch the at least a portion of the sacrificial part, as taught by Desbiolles, since it would allow to easily fabricate nanostructures of various shapes, profiles, heights, thickness and complexity in a short period of time (the 2nd paragraph in Col. 1 on page 2 in Desbiolles).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cui and Demirkol, as applied to claim 1 above, and further in view of Hsu et al. (US20220320090A1).
Regarding claim 8, modified Cui teaches the method according to claim 1, and is silent to wherein the masking layer comprises SiO2, SixNy, Ti, TiN, or DLC.
Hsu teaches a method to fabricate a semiconductor device comprising a first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures (abstract) by using a hard mask layer 209 formed over the epitaxial stack 204. In some embodiments, the hard mask layer 209 includes a dielectric material such as, for example, silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), or a combination thereof [para. 0019].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the mask in modified Cui to a silicon nitride mask, as taught by Hsu, since it would allow to protect portions of the substrate and/or the stack and/or used to define a suitable pattern [para. 0019 in Hsu].
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure: Zhang et al. (US20240218415A1) teaches a pair of electrodes separated by a nanogap on a substrate. Merriman et al. (US20180340220A1) teaches a method of manufacturing electronic sensors comprising two electrodes separated by a nanogap. Choi et al. (US20220170879A1) teaches a method of fabricating nanogap electrode structures. Son et al. (US20050285275A1) teaches fabrication of nano-gap electrode arrays.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIZHI QIAN whose telephone number is (571)272-3487. The examiner can normally be reached Monday-Thursday 8:00 am-5:00 pm.
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/SHIZHI QIAN/Primary Examiner, Art Unit 1795
