DETAILED ACTION
The instant application having Application No. 18/969,093 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
INFORMATION CONCERNING THE SPECIFICATION
Specification
The applicant’s specification submitted is acceptable for examination purposes.
REJECTIONS BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 5-7, 9-10, and 12-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 6, 8-10, and 14-17 of U.S. Patent No. 12,164,449 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because both disclose eyewear with system on a chip (SoC) on different parts of the eyewear’s frame.
Instant Application 18/969,093
Patent Number US 12,164,449 B2
Claim 1
Eyewear, comprising: a frame;
a modem;
and a plurality of system on a chips including a system on a chip (SoC) and another SoC, the other SoC comprising a universal serial bus (USB) component having a USB 3.0 connection interface pinout, wherein the USB component supports USB 2.0 communications via a first subset of the USB 3.0 connection interface pinout that is coupled to the modem and supports USB 3.0 communications via a second subset of the USB 3.0 connection interface pinout that is coupled to the SoC.
Claim 1
Eyewear, comprising: a frame having a first side and a second side;
a first temple portion adjacent the first side of the frame;
a second temple portion adjacent the second side of the frame;
a plurality of electronic components;
a system on a chip (SoC) disposed within the first temple portion, the SoC comprising a central processing unit (CPU), a graphical processing unit (GPU), an image signal processor (ISP), and a universal serial bus (USB) component including a USB connection interface with a first USB sub connection interface and a second USB sub connection interface, wherein the USB connection interface has a USB 3.0 connection interface pinout, the first USB sub connection interface has a first subset of the USB 3.0 connection interface pinout that only has power, ground, and D+/D− connection pins and supports USB 2.0 communications but not USB 3.0 communications, and the second USB sub connection interface has a second subset of the USB 3.0 connection interface pinout that supports USB 3.0 communications;
and another SoC disposed within the second temple portion, the other SoC comprising another CPU, another GPU, another ISP, and another USB connection interface coupled to the first USB sub connection interface;
wherein the first USB sub connection interface of the USB connection interface of the SoC is coupled to the other USB connection interface of the other SoC and the second USB sub connection interface of the USB connection interface of the SoC is coupled to one of the plurality of electronic components or an external device, wherein the USB connection interface of the USB component is simultaneously connected to the other SoC via the first USB sub connection interface and the one of the plurality of electronic components via the second USB sub connection interface.
Claim 2
wherein the SoC is coupled to a first side of the frame and the other SoC is coupled to a second side of the frame.
Claim 6
wherein the one of the plurality of electronic components is an additional SoC and the additional SoC is adjacent a second side of the frame.
Claim 3
wherein the USB component is configured for high speed (HS) USB communications via the first subset of the USB 3.0 connection interface pinout and the USB component is configured for SuperSpeed (SS) USB communications via the second subset of the USB 3.0 connection interface pinout.
Claim 3
wherein the first USB sub connection interface of the USB component is configured for high speed (HS) USB communications and the second USB sub connection interface of the USB component is configured for SuperSpeed (SS) USB communications.
Claim 4
wherein the first subset of the USB 3.0 connection interface pinout includes a D+ connection pin and a D- connection pin and wherein the second subset of USB 3.0 connection interface pinout includes a TX+ connection pin, a TX- connection pin, an RX+ connection pin, and an RX- connection pin.
Claim 5
wherein the plurality of system on a chips further comprises at least one additional SoC.
Claim 8
wherein the plurality of electronic components comprises an additional SoC, the other USB connection interface of the other SoC has a third USB sub connection interface coupled to the first USB connection interface of the SoC and a fourth USB sub connection interface coupled to the additional SoC.
Claim 6
wherein a first of the at least one additional SoC is coupled to the SoC.
Claim 8
wherein the plurality of electronic components comprises an additional SoC, the other USB connection interface of the other SoC has a third USB sub connection interface coupled to the first USB connection interface of the SoC and a fourth USB sub connection interface coupled to the additional SoC.
Claim 7
wherein the first of the at least one additional SoC communicates with the SoC via a D+ connection and a D-connection.
Claim 1
Eyewear, comprising: a frame having a first side and a second side;
a first temple portion adjacent the first side of the frame;
a second temple portion adjacent the second side of the frame;
a plurality of electronic components;
a system on a chip (SoC) disposed within the first temple portion, the SoC comprising a central processing unit (CPU), a graphical processing unit (GPU), an image signal processor (ISP), and a universal serial bus (USB) component including a USB connection interface with a first USB sub connection interface and a second USB sub connection interface, wherein the USB connection interface has a USB 3.0 connection interface pinout, the first USB sub connection interface has a first subset of the USB 3.0 connection interface pinout that only has power, ground,
and D+/D− connection pins and supports USB 2.0 communications but not USB 3.0 communications, and the second USB sub connection interface has a second subset of the USB 3.0 connection interface pinout that supports USB 3.0 communications;
and another SoC disposed within the second temple portion, the other SoC comprising another CPU, another GPU, another ISP, and another USB connection interface coupled to the first USB sub connection interface;
wherein the first USB sub connection interface of the USB connection interface of the SoC is coupled to the other USB connection interface of the other SoC and the second USB sub connection interface of the USB connection interface of the SoC is coupled to one of the plurality of electronic components or an external device, wherein the USB connection interface of the USB component is simultaneously connected to the other SoC via the first USB sub connection interface and the one of the plurality of electronic components via the second USB sub connection interface.
Claim 8
wherein the other SoC communicates with the SoC via SuperSpeed communication and the first of the at least one additional SoC communicates with the SoC via high speed communication.
Claim 9
wherein all of the plurality of SoCs comprise a USB 3.0 connection interface pinout.
Claim 1
Eyewear, comprising: a frame having a first side and a second side;
a first temple portion adjacent the first side of the frame;
a second temple portion adjacent the second side of the frame;
a plurality of electronic components;
a system on a chip (SoC) disposed within the first temple portion, the SoC comprising a central processing unit (CPU), a graphical processing unit (GPU), an image signal processor (ISP), and a universal serial bus (USB) component including a USB connection interface with a first USB sub connection interface and a second USB sub connection interface, wherein the USB connection interface has a USB 3.0 connection interface pinout, the first USB sub connection interface has a first subset of the USB 3.0 connection interface pinout that only has power, ground, and D+/D− connection pins and supports USB 2.0 communications but not USB 3.0 communications, and the second USB sub connection interface has a second subset of the USB 3.0 connection interface pinout that supports USB 3.0 communications;
and another SoC disposed within the second temple portion, the other SoC comprising another CPU, another GPU, another ISP, and another USB connection interface coupled to the first USB sub connection interface;
wherein the first USB sub connection interface of the USB connection interface of the SoC is coupled to the other USB connection interface of the other SoC and the second USB sub connection interface of the USB connection interface of the SoC is coupled to one of the plurality of electronic components or an external device, wherein the USB connection interface of the USB component is simultaneously connected to the other SoC via the first USB sub connection interface and the one of the plurality of electronic components via the second USB sub connection interface.
Claim 10
A method for use with eyewear comprising a frame, a modem, and a plurality of system on a chips including a system on a chip (SoC) and another SoC, the other SoC comprising a universal serial bus (USB) component having a USB 3.0 connection interface pinout, the method comprising: establishing USB 2.0 communication between the other SoC and the modem via a first subset of the USB 3.0 connection interface pinout;
and establishing USB 3.0 communication between the other SoC and the SoC via a second subset of the USB 3.0 connection interface pinout; wherein the universal serial bus (USB) component of the other SoC simultaneously communicates with the modem via the first subset of the USB 3.0 connection interface pinout and with the SoC via the second subset of the USB 3.0 connection interface pinout.
Claim 9
A method for use with eyewear comprising a frame having a first side and a second side, a first temple portion adjacent the first side of the frame, and a second temple portion adjacent the second side of the frame, the eyewear further comprising a system on a chip (SoC) disposed within the first temple portion comprising a central processing unit (CPU), a graphical processing unit (GPU), an image signal processor (ISP), and a universal serial bus (USB) component including a USB connection interface with a first USB sub connection interface and a second USB sub connection interface, wherein the USB connection interface has a USB 3.0 connection interface pinout, the first USB sub connection interface has a first subset of the USB 3.0 connection interface pinout that only has power, ground, and D+/D− connection pins and supports USB 2.0 communications but not USB 3.0 communications, and the second USB sub connection interface has a second subset of the USB 3.0 connection interface pinout that supports USB 3.0 communications, and another SoC disposed within the second temple portion comprising another CPU, another GPU, another ISP, and another USB connection interface coupled to the first USB sub connection interface of the SoC, the method comprising: establishing communication with the other SoC in the second temple portion through the first USB sub connection interface of the SoC in the first temple portion;
establishing communication with an electronic component through the second USB sub connection interface;
and communicating with the other SoC in the second temple through the first USB sub connection interface of the SoC in the first temple and communicating with the second component through the second USB sub connection interface of the SoC in the first temple, wherein the USB connection interface of the USB component is simultaneously connected to the other SoC via the first USB sub connection interface and the electronic component via the second USB sub connection interface.
Claim 11
further comprising: configuring the USB component for high speed (HS) USB communications via the first subset of the USB 3.0 connection interface pinout;
and configuring the USB component for SuperSpeed (SS) USB communications via the second subset of the USB 3.0 connection interface pinout.
Claim 12
wherein to configure the USB component for high speed (HS) USB communications via the first subset of the USB 3.0 connection interface pinout the USB component of the other SoC is configured in a host state for HS USB communications;
and wherein to configure the USB component for SuperSpeed (SS) USB communications via the second subset of the USB 3.0 connection interface pinout the USB component of the other SoC is configured in a device state for SS USB communications.
Claim 9
A method for use with eyewear comprising a frame having a first side and a second side, a first temple portion adjacent the first side of the frame, and a second temple portion adjacent the second side of the frame, the eyewear further comprising a system on a chip (SoC) disposed within the first temple portion comprising a central processing unit (CPU), a graphical processing unit (GPU), an image signal processor (ISP), and a universal serial bus (USB) component including a USB connection interface with a first USB sub connection interface and a second USB sub connection interface, wherein the USB connection interface has a USB 3.0 connection interface pinout, the first USB sub connection interface has a first subset of the USB 3.0 connection interface pinout that only has power, ground, and D+/D− connection pins and supports USB 2.0 communications but not USB 3.0 communications, and the second USB sub connection interface has a second subset of the USB 3.0 connection interface pinout that supports USB 3.0 communications, and another SoC disposed within the second temple portion comprising another CPU, another GPU, another ISP, and another USB connection interface coupled to the first USB sub connection interface of the SoC, the method comprising: establishing communication with the other SoC in the second temple portion through the first USB sub connection interface of the SoC in the first temple portion;
establishing communication with an electronic component through the second USB sub connection interface;
and communicating with the other SoC in the second temple through the first USB sub connection interface of the SoC in the first temple and communicating with the second component through the second USB sub connection interface of the SoC in the first temple, wherein the USB connection interface of the USB component is simultaneously connected to the other SoC via the first USB sub connection interface and the electronic component via the second USB sub connection interface.
Claim 13
wherein the plurality of system on a chips further comprises at least one additional SoC and wherein a first of the at least one additional SoC is coupled to the SoC.
Claim 14
wherein the eyewear comprises an additional SoC, the other USB connection interface of the other SoC has a third USB sub connection interface coupled to the first USB connection interface of the SoC and a fourth USB sub connection interface coupled to the additional SoC.
Claim 14
wherein the first of the at least one additional SoC communicates with the SoC via a D+ connection and a D- connection.
Claim 9
A method for use with eyewear comprising a frame having a first side and a second side, a first temple portion adjacent the first side of the frame, and a second temple portion adjacent the second side of the frame, the eyewear further comprising a system on a chip (SoC) disposed within the first temple portion comprising a central processing unit (CPU), a graphical processing unit (GPU), an image signal processor (ISP), and a universal serial bus (USB) component including a USB connection interface with a first USB sub connection interface and a second USB sub connection interface, wherein the USB connection interface has a USB 3.0 connection interface pinout, the first USB sub connection interface has a first subset of the USB 3.0 connection interface pinout that only has power, ground, and D+/D− connection pins and supports USB 2.0 communications but not USB 3.0 communications, and the second USB sub connection interface has a second subset of the USB 3.0 connection interface pinout that supports USB 3.0 communications, and another SoC disposed within the second temple portion comprising another CPU, another GPU, another ISP, and another USB connection interface coupled to the first USB sub connection interface of the SoC, the method comprising: establishing communication with the other SoC in the second temple portion through the first USB sub connection interface of the SoC in the first temple portion;
establishing communication with an electronic component through the second USB sub connection interface;
and communicating with the other SoC in the second temple through the first USB sub connection interface of the SoC in the first temple and communicating with the second component through the second USB sub connection interface of the SoC in the first temple, wherein the USB connection interface of the USB component is simultaneously connected to the other SoC via the first USB sub connection interface and the electronic component via the second USB sub connection interface.
Claim 15
wherein the other SoC communicates with the SoC via SuperSpeed communication and the first of the at least one additional SoC communicates with the SoC via high speed communication.
Claim 10
configuring the first USB sub connection interface of the USB component for high speed (HS) USB communications; and configuring the second USB sub connection interface of the USB component for SuperSpeed (SS) USB communications.
Claim 16
A non-transitory computer readable medium having instructions for use with eyewear comprising a frame, a modem, and a plurality of system on a chips including a system on a chip (SoC) and another SoC, the other SoC comprising a universal serial bus (USB) component having a USB 3.0 connection interface pinout, the instructions, when executed by a processor configure the eyewear to:
establish USB 2.0 communication between the other SoC and the modem via a first subset of the USB 3.0 connection interface pinout; and establish USB 3.0 communication between the other SoC and the SoC via a second subset of the USB 3.0 connection interface pinout;
wherein the universal serial bus (USB) component of the other SoC is configured to simultaneously communicate with the modem via the first subset of the USB 3.0 connection interface pinout and with the SoC via the second subset of the USB 3.0 connection interface pinout.
Claim 15
A non-transitory computer readable medium having instructions for use with eyewear comprising a frame having a first side and a second side, a first temple portion adjacent the first side of the frame, and a second temple portion adjacent the second side of the frame, the eyewear further comprising a system on a chip (SoC) disposed within the first temple portion comprising a central processing unit (CPU), a graphical processing unit (GPU), an image signal processor (ISP), and a universal serial bus (USB) component including a USB connection interface with a first USB sub connection interface and a second USB sub connection interface, wherein the USB connection interface has a USB 3.0 connection interface pinout, the first USB sub connection interface has a first subset of the USB 3.0 connection interface pinout that only has power, ground, and D+/D− connection pins and supports USB 2.0 communications but not USB 3.0 communications, and the second USB sub connection interface has a second subset of the USB 3.0 connection interface pinout that supports USB 3.0 communications, and another SoC disposed within the second temple portion comprising another CPU, another GPU, another ISP, and another USB connection interface coupled to the first USB sub connection interface of the SoC, the instructions, when executed by a processor configure the eyewear to: establish communication with the other SoC in the second temple portion through the first USB sub connection interface of the SoC in the first temple portion;
establish communication with an electronic component through the second USB sub connection interface; and communicate with the other SoC in the second temple through the first USB sub connection interface of the SoC in the first temple and communicating with the second component through the second USB sub connection interface of the SoC in the first temple, wherein the USB connection interface of the USB component is simultaneously connected to the other SoC via the first USB sub connection interface and the electronic component via the second USB sub connection interface.
Claim 17
wherein the instructions, when executed by the processor, further configure the eyewear to: configure the USB component for high speed (HS) USB communications via the first subset of the USB 3.0 connection interface pinout; and configure the USB component for SuperSpeed (SS) USB communications via the second subset of the USB 3.0 connection interface pinout.
Claim 16
wherein the instructions, when executed by the processor, further configure the eyewear to: configure the first USB sub connection interface of the USB component for high speed (HS) USB communications; and configure the second USB sub connection interface of the USB component for SuperSpeed (SS) USB communications.
Claim 18
wherein to configure the USB component for high speed (HS) USB communications via the first subset of the USB 3.0 connection interface pinout the USB component of the other SoC is configured in a host state for HS USB communications;
and wherein to configure the USB component for SuperSpeed (SS) USB communications via the second subset of the USB 3.0 connection interface pinout the USB component of the other SoC is configured in a device state for SS USB communications.
Claim 17
wherein to configure the first USB sub connection interface of the USB component for high speed (HS) USB communications the USB component of the SoC is configured in a host state for HS USB communications via the first USB sub connection interface;
and wherein to configure the second USB sub connection interface of the USB component for SuperSpeed (SS) USB communications the USB component of the SoC is configured in a device state for SS USB communications via the second USB sub connection interface.
Claim 19
wherein the plurality of system on a chips further comprises at least one additional SoC, a first of the at least one additional SoC is coupled to the SoC, and the first of the at least one additional SoC communicates with the SoC via a D+ connection and a D- connection.
Claim 15
A non-transitory computer readable medium having instructions for use with eyewear comprising a frame having a first side and a second side, a first temple portion adjacent the first side of the frame, and a second temple portion adjacent the second side of the frame, the eyewear further comprising a system on a chip (SoC) disposed within the first temple portion comprising a central processing unit (CPU), a graphical processing unit (GPU), an image signal processor (ISP), and a universal serial bus (USB) component including a USB connection interface with a first USB sub connection interface and a second USB sub connection interface, wherein the USB connection interface has a USB 3.0 connection interface pinout, the first USB sub connection interface has a first subset of the USB 3.0 connection interface pinout that only has power, ground, and D+/D− connection pins and supports USB 2.0 communications but not USB 3.0 communications, and the second USB sub connection interface has a second subset of the USB 3.0 connection interface pinout that supports USB 3.0 communications, and another SoC disposed within the second temple portion comprising another CPU, another GPU, another ISP, and another USB connection interface coupled to the first USB sub connection interface of the SoC, the instructions, when executed by a processor configure the eyewear to: establish communication with the other SoC in the second temple portion through the first USB sub connection interface of the SoC in the first temple portion;
establish communication with an electronic component through the second USB sub connection interface; and communicate with the other SoC in the second temple through the first USB sub connection interface of the SoC in the first temple and communicating with the second component through the second USB sub connection interface of the SoC in the first temple, wherein the USB connection interface of the USB component is simultaneously connected to the other SoC via the first USB sub connection interface and the electronic component via the second USB sub connection interface.
Claim 20
wherein the plurality of system on a chips further comprises at least one additional SoC, the other SoC communicates with the SoC via SuperSpeed communication, and the first of the at least one additional SoC communicates with the SoC via high speed communication.
Claim 16
wherein the instructions, when executed by the processor, further configure the eyewear to: configure the first USB sub connection interface of the USB component for high speed (HS) USB communications; and configure the second USB sub connection interface of the USB component for SuperSpeed (SS) USB communications.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(c), the applicant's submission of the Information Disclosure Statement dated March 4, 2025, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
CLOSING COMMENTS
Conclusion
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Yu whose telephone number is (571)272-9779. The examiner can normally be reached Monday - Friday.
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/H.W.Y/Examiner, Art Unit 2181 February 18, 2026
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181