DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/04/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“resolving, by an address unit[…] a difference between a memory address and a second offset” in claim 1, which will be interpreted as an adder according to [0040] of the specification
“resolve, by an address unit[…] a difference between a memory address and a second offset” in claim 28, which will be interpreted as an adder according to [0040] of the specification
“resolve, by an address unit[…] a difference between a memory address and a second offset” in claim 35, which will be interpreted as an adder according to [0040] of the specification
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-22 and 35-36 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,204,907. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the reference patent teaches claims 21-22 and 35-36 of the instant application as follows (claims of the instant application are in bold/italics, claims of reference patent are in parenthesis):
21. A method, comprising:
executing, by a processor, an instruction of an application (claim 1: “a load instruction of an application”, “the processor… configured to execute the load instruction”), wherein the instruction comprises a position-independent addressing mode (claim 1: “the load instruction indicating a position-independent addressing mode”), and wherein the executing comprises:
obtaining a first offset for a memory location identified by the instruction from a hardware lookup table of the processor, the first offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the memory location (claim 1: “wherein to execute the load instruction, the processor is configured in hardware circuitry to[…] obtain the offset for the source memory address from the hardware lookup table of the processor, the offset previously established by an operating system, different from the application, according to an allocation of a portion of the memory containing the source memory address”); and
resolving, by an address unit coupled to the processor, a difference between a memory address and a second offset associated with the memory location (claim 1: “add the obtained offset to the normalized memory address to determine a particular memory address”; that is, adding the obtained offset to the normalized memory address (i.e., a second offset) resolves a difference between the particular memory address (i.e., a memory address) and the normalized address (i.e., the second offset)).
22.The method of claim 21, wherein:
the instruction is a load instruction (claim 1: “a load instruction”);
the method further comprises loading the second offset loaded from the memory location (claim 1: “load a normalized memory address from a location of the memory identified by the source memory address”); and
resolving the difference between the memory address and the second offset comprises adding the first offset to the second offset to determine the memory address responsive to determining that the second offset is different from a reserved value indicating an invalid memory address (claim 1: “responsive to determining that the normalized memory address is different from a reserved value, the reserved value indicating an invalid memory address… add the obtained offset to the normalized memory address to determine a particular memory address”).
35. A processor, comprising:
a hardware lookup table that stores a first offset for a memory location (claim 1: “a processor different from the memory, the processor comprising a hardware lookup table that stores an offset for a source memory address”);
wherein the processor is configured to execute an instruction of an application, wherein the instruction comprises a position-independent addressing mode (claim 1: “a load instruction of an application, the load instruction indicating a position-independent addressing mode”, “a processor […] configured to execute the load instruction”), and wherein to execute the instruction the processor is configured to:
obtain the first offset from the hardware lookup table of the processor, the first offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the memory location (claim 1: “obtain the offset for the source memory address from the hardware lookup table of the processor, the offset previously established by an operating system, different from the application, according to an allocation of a portion of the memory containing the source memory address”); and
resolve, by an address unit coupled to the processor, a difference between a memory address and a second offset associated with the memory location (claim 1: “add the obtained offset to the normalized memory address to determine a particular memory address”; that is, adding the obtained offset to the normalized memory address (i.e., a second offset) resolves a difference between the particular memory address (i.e., a memory address) and the normalized address (i.e., the second offset)).
36. The processor of claim 35, wherein:
the instruction is a load instruction (claim 1: “a load instruction”);
the processor is further configured to load the second offset loaded from the memory location (claim 1: “load a normalized memory address from a location of the memory identified by the source memory address”); and
to resolve the difference between the memory address and the second offset the processor is configured to add the first offset to the second offset to determine the memory address responsive to determining that the second offset is different from a reserved value indicating an invalid memory address (claim 1: “responsive to determining that the normalized memory address is different from a reserved value, the reserved value indicating an invalid memory address… add the obtained offset to the normalized memory address to determine a particular memory address”).
Claims 21, 25, 35, and 39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 12,204,907. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 14 of the reference patent teaches claims 21 and 25 of the instant application as follows (claims of the instant application are in bold/italics, claims of reference patent are in parenthesis):
21. A method, comprising:
executing, by a processor, an instruction of an application, wherein the instruction comprises a position-independent addressing mode (claim 14: “executing, by a processor[…] a store instruction of an application, the store instruction indicating the position-independent addressing mode”), and wherein the executing comprises:
obtaining a first offset for a memory location identified by the instruction from a hardware lookup table of the processor, the first offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the memory location (claim 14: “wherein the executing comprises[…] obtaining the offset for the destination memory address from the hardware lookup table of the processor, the offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the destination memory address;”); and
resolving, by an address unit coupled to the processor, a difference between a memory address and a second offset associated with the memory location (claim 14: “subtracting the obtained offset from the normalized pointer to generate a normalized memory address”; that is subtracting the obtained offset from the normalized pointer (i.e., a memory address) resolves a difference between the normalized pointer (i.e., the memory address) and the normalized memory address (i.e., a second offset)).
25. The method of claim 21, wherein:
the instruction is a store instruction (claim 14: a store instruction);
the method further comprises storing the second offset to the memory location (claim 14: “storing the normalizing memory address in memory location[…] identified by the destination memory address”); and
resolving the difference between the memory address and the second offset comprises subtracting the first offset from the memory address to determine the second offset responsive to determining that the memory address is not an invalid memory address (claim 14: “responsive to determining that a normalized pointer is different from a memory address value, the memory address value indicating an invalid memory pointer[…] subtracting the obtained offset from the normalized pointer to generate a normalized memory address”).
35. A processor, comprising:
a hardware lookup table that stores a first offset for a memory location (claim 14: “a hardware lookup table that stores an offset for a destination memory address”);
wherein the processor is configured to execute an instruction of an application, wherein the instruction comprises a position-independent addressing mode (claim 14: “executing, by a processor […] a store instruction of an application, the store instruction indicating the position-independent addressing mode”), and wherein to execute the instruction the processor is configured to:
obtain the first offset from the hardware lookup table of the processor, the first offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the memory location (claim 14: “obtaining the offset for the destination memory address from the hardware lookup table of the processor, the offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the destination memory address”); and
resolve, by an address unit coupled to the processor, a difference between a memory address and a second offset associated with the memory location (claim 14: “subtracting the obtained offset from the normalized pointer to generate a normalized memory address”; that is subtracting the obtained offset from the normalized pointer (i.e., a memory address) resolves a difference between the normalized pointer (i.e., the memory address) and the normalized memory address (i.e., a second offset)).
39. The processor of claim 35, wherein:
the instruction is a store instruction (claim 14: a store instruction);
the processor is further configured to store the second offset to the memory location (claim 14: “storing the normalizing memory address in memory location[…] identified by the destination memory address”); and
to resolve the difference between the memory address and the second offset the processor is configured to subtract the first offset from the memory address to determine the second offset responsive to determining that the memory address is not an invalid memory address (claim 14: “responsive to determining that a normalized pointer is different from a memory address value, the memory address value indicating an invalid memory pointer[…] subtracting the obtained offset from the normalized pointer to generate a normalized memory address”).
Claims 28-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,204,907 in view of Shen US 2015/0169226. Claim 1 of the reference patent in view of Shen teaches claims 28-29 of the instant application as follows (claims of the instant application are in bold/italics, claims of reference patent are in parenthesis):
28. A system, comprising:
a memory storing an instruction of an application, the instruction indicating a position- independent addressing mode (claim 1: “a memory storing a load instruction of an application, the load instruction indicating a position-independent addressing mode”); and
a processor different from the memory subsystem, the processor comprising a hardware lookup table that stores a first offset for a memory location and configured to execute the instruction, wherein to execute the instruction, the processor is configured in hardware circuitry to (claim 1: “a processor different from the memory, the processor comprising a hardware lookup table that stores an offset for a source memory address and configured to execute the load instruction, wherein to execute the load instruction, the processor is configured in hardware circuitry to:”):
obtain the first offset from the hardware lookup table of the processor, the first offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the memory location (claim 1: “obtain the offset for the source memory address from the hardware lookup table of the processor, the offset previously established by an operating system, different from the application, according to an allocation of a portion of the memory containing the source memory address”); and
resolve, by an address unit coupled to the processor, a difference between a memory address and a second offset associated with the memory location (claim 1: “add the obtained offset to the normalized memory address to determine a particular memory address”; that is, adding the obtained offset to the normalized memory address (i.e., a second offset) resolves a difference between the particular memory address (i.e., a memory address) and the normalized address (i.e., the second offset)).
Claim 1 of the reference patent does not teach a memory subsystem comprising persistent memory. However, Shen teaches a memory subsystem comprising persistent memory (see [0027]). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify claim 1 to include a persistent memory as taught by Shen. One of ordinary skill in the art would have been motivated to make this modification to enable retaining data when power is removed, which would improve reliability.
29. The system of claim 28, wherein:
the instruction is a load instruction (claim 1: “a load instruction”);
the processor is further configured in hardware circuitry to load the second offset loaded from the memory location (claim 1: “the processor is configured in hardware circuitry to: load a normalized memory address from a location of the memory identified by the source memory address”); and
to resolve the difference between the memory address and the second offset the processor is configured in hardware circuitry to add the first offset to the second offset to determine the memory address responsive to determining that the second offset is different from a reserved value indicating an invalid memory address (claim 1: “responsive to determining that the normalized memory address is different from a reserved value, the reserved value indicating an invalid memory address… add the obtained offset to the normalized memory address to determine a particular memory address”).
Claims 28 and 32 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 12,204,907 in view of Shen US 2015/0169226. Claim 14 of the reference patent in view of Shen teaches claims 28 and 32 of the instant application as follows (claims of the instant application are in bold/italics, claims of reference patent are in parenthesis):
28. A system, comprising:
an instruction of an application, the instruction indicating a position- independent addressing mode (claim 14: “a store instruction of an application, the store instruction indicating the position-independent addressing mode”); and
a processor different from the memory subsystem, the processor comprising a hardware lookup table that stores a first offset for a memory location and configured to execute the instruction, wherein to execute the instruction, the processor is configured in hardware circuitry to (claim 14: “executing, by a processor comprising a hardware lookup table that stores an offset for a destination memory address […] a store instruction”):
obtain the first offset from the hardware lookup table of the processor, the first offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the memory location (claim 14: “obtaining the offset for the destination memory address from the hardware lookup table of the processor, the offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the destination memory address”); and
resolve, by an address unit coupled to the processor, a difference between a memory address and a second offset associated with the memory location (claim 14: “subtracting the obtained offset from the normalized pointer to generate a normalized memory address”; that is subtracting the obtained offset from the normalized pointer (i.e., a memory address) resolves a difference between the normalized pointer (i.e., the memory address) and the normalized memory address (i.e., a second offset)).
The reference application does not teach a memory subsystem comprising persistent memory and a memory storing an instruction. However, Shen teaches a memory subsystem comprising persistent memory and a memory storing an instruction ([0027]: memory subsystem 124 includes volatile memory and persistent memory, the persistent memory includes programs similar to the volatile memory, which indicates that the volatile memory also stores programs/instructions). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify claim 1 to include the memory subsystem comprising persistent memory and memory storing an instruction as taught by Shen. One of ordinary skill in the art would have been motivated to make this modification to enable storing programs and to enable retaining data when power is removed (Shen [0027]), which would improve reliability.
32. The system of claim 28, wherein:
the instruction is a store instruction (claim 14: “a store instruction”);
the processor is further configured in hardware circuitry to store the second offset to the memory location (claim 14: “storing the normalizing memory address in a memory location […] identified by the destination memory address”); and
to resolve the difference between the memory address and the second offset the processor is configured in hardware circuitry to subtract the first offset from the memory address to determine the second offset responsive to determining that the memory address is not an invalid memory address (claim 14: “responsive to determining that a normalized pointer is different from a memory address value, the memory address value indicating an invalid memory pointer […] subtracting the obtained offset from the normalized pointer to generate a normalized memory address”).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22-24, 29-31, and 36-38 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites “the second offset loaded from the memory location” in lines 3-4. There is insufficient antecedent basis for this limitation because the claims do not introduce a second offset that is loaded from the memory location. Although claim 21 introduces a second offset associated with the memory location, this is different from the second offset being loaded from the memory location.
Claim 23 recites the same limitation and is rejected for the same reasons.
Claim 29 recites “the second offset loaded from the memory location” in lines 3-4. There is insufficient antecedent basis for this limitation because the claims do not introduce a second offset that is loaded from the memory location. Although claim 28 introduces a second offset associated with the memory location, this is different from the second offset being loaded from the memory location.
Claim 30 recites the same limitation and is rejected for the same reasons.
Claim 36 recites “the second offset loaded from the memory location” in lines 3-4. There is insufficient antecedent basis for this limitation because the claims do not introduce a second offset that is loaded from the memory location. Although claim 35 introduces a second offset associated with the memory location, this is different from the second offset being loaded from the memory location.
Claim 37 recites the same limitation and is rejected for the same reasons.
Claims dependent from a rejected base claim are further rejected based on their dependence.
Prior Art Considerations
While no prior art rejection is given for claims 21-25, 28-32, and 35-39, these claims are currently rejected under double patenting and/or 112(b) and are thus not allowable at the current point. The following is a statement of the prior art considerations given for these claims:
The known prior art of record, taken alone or in combination, was not found to teach, in combination with other limitations in the claims, executing an instruction comprising a position-independent addressing mode, the executing comprising: obtaining an offset for a memory location identified by the instruction from a hardware lookup table, the offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the memory location; and resolving a difference between a memory address and a second offset associated with the memory location, as required by claims 21, 28, and 35.
The closest prior art of record was found to be:
Shen US 2015/0169226 which teaches dereferencing a persistent pointer by determining the offset between a current virtual base address and a stored virtual base address, see [0084]. However, Shen does not teach obtaining the offset from a hardware lookup table, the offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the memory location.
Pawlowski US 10,929,132 which teaches indirect load and store instructions (Fig. 4) the indirect load instruction having a source memory address identifier, destination location, and a LEV-IND modifier that indicates a level of indirection for the load, see col 3 lines 19-31 and col 6 lines 18-23. However, Pawlowski does not teach executing the indirect load instruction by obtaining an offset for a memory location identified by the indirection load instruction from a hardware lookup table, the offset previously established by an operating system, different from the application, according to an allocation of a portion of a memory containing the memory location.
Allowable Subject Matter
Claims 26-27, 33-34, and 40 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/KASIM ALLI/Examiner, Art Unit 2183 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183