DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 6, 8, 10-12, 14, 15, 18, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Katsura et al. (JP 2019-075887 A), as cited in the IDS 02/03/2025.
Regarding Claim 1, Katsura et al. teaches in Figure 1 a semiconductor switch drive circuit comprising:
connection switching circuitry electrically connected between a drive power source and a semiconductor switch, and configured to switch a connection state of the semiconductor switch (charge/discharge control unit 13(a) and 13(b), as connected between 5 and 2, 3);
a first capacitor electrically connected between the drive power source and the connection switching circuitry, and configured to be charged by the drive power source, and to generate a positive voltage to set the semiconductor switch to an ON state (11(a) and 11(b), as connected between 5 and 2, 3);
a second capacitor electrically connected in parallel with the first capacitor with respect to the drive power source, and configured to be charged by the drive power source (12(a) is in parallel with 11(a) and charged by 5; 12(b) is in parallel with 11(b) and charged by 5); and
a third capacitor electrically connected between the second capacitor and the connection switching circuitry, and configured to be charged by the second capacitor, and to generate a negative voltage to set the semiconductor switch to an OFF state (16(a) is connected between 12(a) and 13(a); 16(b) is connected between 12(b) and 13(b)),
wherein the connection switching circuitry is configured to alternately switch between:
a first connection state forming a positive voltage application closed circuit configured to apply the positive voltage to a control terminal of the semiconductor switch by an electrical connection between a positive terminal of the first capacitor and the control terminal of the semiconductor switch (see Figure 3: W4); and
a second connection state forming a negative voltage application closed circuit configured to apply the negative voltage to the control terminal of the semiconductor switch by an electrical connection between a negative terminal of the third capacitor and the control terminal of the semiconductor switch (see Figure 2: W3), and
wherein the semiconductor switch drive circuit further comprises transfer restricting circuitry connected between the first capacitor and an input terminal of the semiconductor switch, wherein the transfer restricting circuitry is configured to supply the positive voltage output from the first capacitor, to the control terminal of the semiconductor switch, by suppressing a supply of the positive voltage to the second capacitor and to the input terminal of the semiconductor switch (using 8(a), 8(b)).
Regarding Claim 5, Katsura et al. further teaches the semiconductor switch drive circuit,
wherein the positive terminal of the first capacitor is electrically connected to a positive terminal of the drive power source and the control terminal of the semiconductor switch (connected with 5 through 8(a) and to gate of 2 as shown in Figure 3),
wherein a positive terminal of the second capacitor is electrically connected to the positive terminal of the drive power source (as connected through 8(a) and 9(a),
wherein the negative terminal of the third capacitor is electrically connected to a negative terminal of the second capacitor (as connected through 14(a)), and
wherein a positive terminal of the third capacitor is electrically connected to the control terminal of the semiconductor switch (as shown in Figure 2: W3).
Regarding Claim 6, Katsura et al. further teaches the semiconductor switch drive circuit comprising:
a first semiconductor switch drive sub-circuit configured to drive the semiconductor switch which corresponds to a first semiconductor switch, wherein the first semiconductor switch drive sub-circuit includes the connection switching circuitry, the first capacitor, the second capacitor, the third capacitor, and the transfer restricting circuitry (6(a), which includes connection switching circuitry 13(a), first capacitor 11(a), second capacitor 12(a), third capacitor16(a), and transfer restricting circuitry 8(a));
a second semiconductor switch drive sub-circuit configured to drive a second semiconductor switch that is electrically connected in series with the first semiconductor switch (6(b), which drives 3; wherein 3 is serially connected to 2); and
the drive power source that is configured to supply electric power to both the first semiconductor switch drive sub-circuit and the second semiconductor switch drive sub-circuit (using 5).
Regarding Claim 8, Katsura et al. further teaches the semiconductor switch drive circuit,
wherein the connection switching circuitry of the first semiconductor switch drive sub-circuit corresponds to a first connection switching circuitry (13(a)), wherein the second semiconductor switch drive sub-circuit includes:
a second connection switching circuitry electrically connected between the drive power source and the second semiconductor switch (13(b), as connected between 5 and 3), and configured to switch a connection state of the second semiconductor switch (using 13(b));
a fourth capacitor electrically connected between the drive power source and the second connection switching circuitry, and configured to be charged by the drive power source, and to generate a positive voltage to set the second semiconductor switch to an ON state (11(b)); and
a fifth capacitor electrically connected in series between the fourth capacitor and the second connection switching circuitry, and configured to be charged by the fourth capacitor, and to generate a negative voltage to set the second semiconductor switch to an OFF state (12(b), as shown in Figure 5, W1’ to be serially connected between 11(b) and 13(b)), and
wherein the second connection switching circuitry is configured to alternately switch between:
a third connection state forming another positive voltage application closed circuit configured to apply the positive voltage generated by the fourth capacitor to a control terminal of the second semiconductor switch by an electrical connection between a positive terminal of the fourth capacitor and the control terminal of the second semiconductor switch (see Figure 4: W4’); and
a fourth connection state forming another negative voltage application closed circuit configured to apply the negative voltage generated by the fifth capacitor to the control terminal of the second semiconductor switch by an electrical connection between a negative terminal of the fifth capacitor and the control terminal of the second semiconductor switch (see Figure 5: W3’).
Regarding Claim 10, Katsura et al. teaches a power converter comprising:
the semiconductor switch drive circuit according to claim 1 (see rejection of Claim 1); and
the semiconductor switch that is configured to be electrically connected between a supply power source and a load device (2, as connected between 4 and load), to convert source power generated by the supply power source into converted power to be supplied to the load device (see [0020]-[0021]),
wherein the source power is characterized by a first electrical parameter (see [0021]), and
wherein the converted power is characterized by a second electrical parameter that is different from the first electrical parameter (see [0020]).
Regarding Claim 11, Katsura et al. further teaches the power converter, wherein the first electrical parameter associated with the source power corresponds to a direct current (DC) ([0021]), and wherein the second electrical parameter associated with the converted power corresponds to an alternating current (AC) ([0020]).
Regarding Claim 12, Katsura et al. teaches in Figure 1 a semiconductor switch drive circuit comprising:
a first capacitor configured to be charged by a drive power source, and to generate a positive voltage to set a semiconductor switch to an ON state (11(a), as charged by 5);
a second capacitor configured to be charged by the drive power source (12(a), as charged by 5);
a third capacitor configured to be charged by the second capacitor, and to generate a negative voltage to set the semiconductor switch to an OFF state (16(a));
connection switching circuitry connected between the first capacitor and the third capacitor (13(a)),
wherein the connection switching circuitry is configured to alternately switch between a first connection state and a second connection state (see Figures 2 and 3),
wherein in the first connection state, a control terminal of the semiconductor switch is supplied with the positive voltage output from a positive terminal of the first capacitor (see Figure 3), and
wherein in the second connection state, the control terminal of the semiconductor switch is supplied with the negative voltage output from a negative terminal of the third capacitor (see Figure 2); and
transfer restricting circuitry electrically connected between the positive terminal of the first capacitor and a positive terminal of the second capacitor, wherein the transfer restricting circuitry is configured to suppress the transfer of the positive voltage from the first capacitor to the second capacitor (using 8(a)).
Regarding Claim 14, Katsura et al. further teaches the semiconductor switch drive circuit, wherein the transfer restricting circuitry is configured to cause an electric current that is output from the positive terminal of the first capacitor to be substantially maintained through to the connection switching circuitry (using 13(a)).
Regarding Claim 15, Katsura et al. further teaches the semiconductor switch drive circuit,
wherein the second capacitor is electrically connected in parallel with the first capacitor with respect to the drive power source (12(a) is in parallel with 11(a) and charged by 5; 12(b) is in parallel with 11(b) and charged by 5),
wherein the transfer restricting circuitry is electrically connected between the positive terminal of the first capacitor and the drive power source (8(a) is connected between 11(a) and 5; 8(b) is connected between 11(b) and 5), and further electrically connected between the positive terminal of the second capacitor and the drive power source (8(a) is connected between 12(a) and 5; 8(b) is connected between 11(b) and 5),
wherein the positive terminal of the first capacitor is electrically connected to the connection switching circuitry (see Figure 3: W4), and
wherein the negative terminal of the third capacitor is electrically connected to a negative terminal of the second capacitor and to the connection switching circuitry (see Figure 2: W3).
Regarding Claim 18, Katsura et al. further teaches the semiconductor switch drive circuit,
wherein in the first connection state, the connection switching circuitry forms a positive voltage application closed circuit that electrically connects the control terminal of the semiconductor switch with the first capacitor and that disconnects the control terminal from the third capacitor (see Figure 3: W4, W5), and
wherein in the second connection state, the connection switching circuitry forms a negative voltage application closed circuit that electrically connects the control terminal of the semiconductor switch with the third capacitor and that disconnects the control terminal from the first capacitor (see Figure 2: W1, W2, W3).
Regarding Claim 19, the prior art does not disclose, teach or suggest the semiconductor switch drive circuit, comprising:
the drive power source that is configured to supply electric power (5);
a first semiconductor switch drive sub-circuit including the connection switching circuitry, the first capacitor, the second capacitor, the third capacitor, and the transfer restricting circuitry (6(a), which includes connection switching circuitry 13(a), first capacitor 11(a), second capacitor 12(a), third capacitor16(a), and transfer restricting circuitry 8(a)), wherein the first semiconductor switch drive sub-circuit is configured to be supplied with the electric power from the drive power source, and to drive the semiconductor switch which corresponds to a first semiconductor switch, via the connection switching circuitry which corresponds to a first connection switching circuitry (see Figure 3, W4); and
a second semiconductor switch drive sub-circuit configured to be supplied with the electric power from the drive power source (6b), and to drive a second semiconductor switch that is electrically connected in series with the first semiconductor switch (3, which is in series with 2),
wherein the second semiconductor switch drive sub-circuit includes a second connection switching circuitry that is configured to alternately switch the second semiconductor switch between an ON state and an OFF state (13(b)),
wherein the first semiconductor switch drive sub-circuit and the second semiconductor switch drive sub-circuit are configured to convert a direct current generated from a supply power source to an alternating current that is output via the first semiconductor switch and the second semiconductor switch ([0020]).
Allowable Subject Matter
Claims 2-4, 7, 9, 13, 16, 17, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, the prior art does not disclose, teach or suggest the semiconductor switch drive circuit, further comprising:
a first connection point between the positive terminal of the first capacitor and the control terminal of the semiconductor switch;
a second connection point between a positive terminal of the second capacitor and the input terminal of the semiconductor switch; and
a third connection point arranged between the first connection point and a positive terminal of the drive power source, and electrically connected to the positive terminal of the drive power source,
wherein the transfer restricting circuitry includes:
a first conductive portion connecting the first connection point with the third connection point; and
a second conductive portion connecting the second connection point with the third connection point;
in combination with all the other claimed limitations.
Claims 3 and 4 are objected to for depending from Claim 2.
Regarding Claim 7, the prior art does not disclose, teach or suggest the semiconductor switch drive circuit, wherein the transfer restricting circuitry of the first semiconductor switch drive sub-circuit includes:
a first diode configured to direct a first current from the electric power of the drive power source to the positive terminal of the first capacitor; and
a second diode configured to direct a second current from the electric power of the drive power source to the positive terminal of the second capacitor, and
wherein the second semiconductor switch drive sub-circuit includes:
a fourth capacitor that is electrically connected in series with the drive power source via a first conductive path that is free of any diode; and
an additional capacitor that is electrically connected in series with the drive power source via a second conductive path and in parallel with the fourth capacitor with respect to the drive power source, wherein the second conductive path is free of any diode;
in combination with all the other claimed limitations.
Regarding Claim 9, the prior art does not disclose, teach or suggest the semiconductor switch drive circuit, wherein the transfer restricting circuitry is electrically connected between the positive terminal of the first capacitor and a positive terminal of the second capacitor, to suppress the transfer of the positive voltage from the first capacitor to the second capacitor;
in combination with all the other claimed limitations.
Regarding Claim 13, the prior art does not disclose, teach or suggest the semiconductor switch drive circuit, wherein the transfer restricting circuitry is configured to be electrically connected between the positive terminal of the first capacitor and an input terminal of the semiconductor switch to further suppress the transfer of the positive voltage to the input terminal of the semiconductor switch;
in combination with all the other claimed limitations.
Regarding Claim 16, the prior art does not disclose, teach or suggest the semiconductor switch drive circuit, wherein the transfer restricting circuitry includes:
a first conductive portion electrically connected between the drive power source and the positive terminal of the first capacitor to supply a first current from electric power supplied by the drive power source, wherein the first conductive portion includes a first diode configured to direct the first current toward the positive terminal of the first capacitor; and
a second conductive portion connected in parallel to the first conductive portion, between the drive power source and the positive terminal of the second capacitor to supply a second current from the electric power of the drive power source, wherein the second conductive portion includes a second diode configured to direct the second current toward the second capacitor;
in combination with all the other claimed limitations.
Claim 17 is objected to for depending from Claim 16.
Regarding Claim 20, the prior art does not disclose, teach or suggest the semiconductor switch drive circuit, wherein the transfer restricting circuitry of the first semiconductor switch drive sub-circuit includes: a first diode configured to direct a first current from the electric power of the drive power source, to the positive terminal of the first capacitor; and a second diode configured to direct a second current from the electric power of the drive power source, to the positive terminal of the second capacitor, and wherein the second semiconductor switch drive sub-circuit includes: a fourth capacitor that is electrically connected in series with the drive power source via a first conductive path that is free of any diode; and an additional capacitor that is electrically connected in series with the drive power source via a second conductive path and in parallel with the fourth capacitor with respect to the drive power source, wherein the second conductive path is free of any diode;
in combination with all the other claimed limitations.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DIANA J. CHENG/Primary Examiner, Art Unit 2849