CTNF 18/969,372 CTNF 81061 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are pending. This is in response to communications filed on 12/5/24. The IDS filed on 5/15/26 has been considered by the examiner. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 7-9, 10, 16-20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Banik et al (US Patent Application Publication 2021/0004241) . For claim 1, Banik et al teach the following limitations: A method comprising: initializing a system memory ([0042]-[0045] mentions system memory; Fig 1 shows memory includes 106, 124, 126 and other memories) during a boot cycle (Fig 5 and Fig 6 show various memory initialization during boot cycle) of a computing system (Fig 1 shows the computing system) having a parallel processing core communicatively coupled to a general processing core (Fig 1 shows various cores CORE 0 to CORE N; [0021]; [0067] mentions BSP core and AP cores; BSP core is the general purpose core; [0082] – parallel processing by AP) ; storing display data in a memory cache of the parallel processing core (L4 cache 126 shown in Fig 1; [0018] shared cache is used to store display device code used for display; [0033] – 159 is stored in cache); and during the initializing of the system memory (Fig 5; [0065] – display is brought for display by the memory initialization phase 530) , retrieving the stored display data from the memory cache of the parallel processing core ([0047] – enhance a boot process by extending cache memory to enable a multi-core environment; [0060] – multi-core availability and L4 cache as SRAM availability , display initialization runs parallel with other hardware initialization; [0082] – hardware initialization code is spread across all cores over parallel threads) for presentation on a display device of the computing system ([0016] – display bring up; [0018][0033][0065] – display brought up by phase 530). For claim 7, Banik teaches wherein storing the display data in the memory cache of the parallel processing core comprises configuring the memory cache to operate in a system memory emulation mode (Fig 5 – phase 510 – configure L4 cache as SRAM; [0065]). For claim 8, Banik teaches updating the display data stored in the memory cache for presentation on the display device during the initializing of the system memory ([0033] storing display code in cache; [0070][0079] – frame buffer pointer toward cache, framebuffer programmed during SRAM initialization). For claim 9, Banik teaches wherein the display data stored in the memory cache for presentation on the display device comprises one or more of a group that includes a boot cycle progress indicator, diagnostic information, or status information regarding the computing system (Fig 5 and Fig 6 – boot cycle progress indicator “display on” is after SEC; the display is off in SEC 581 stage). For claim 10, Banik et al teach the following limitations: A computing system (Fig 1), comprising: a parallel processing core (core 112 in Fig 1; (Fig 1 shows various cores CORE 0 to CORE N; [0021]; [0067] mentions BSP core and AP cores; BSP core is the general purpose core; [0082] – parallel processing) having a memory cache (L4 cache 126 shown in Fig 1; [0018] shared cache is used to store display device code used for display; [0033] – 159 is stored in cache) ; a general processing core communicatively coupled to the parallel processing core (Fig 1 shows various cores CORE 0 to CORE N; [0021]; [0067] mentions BSP core and AP cores; BSP core is the general purpose core; [0082] – parallel processing by AP) ; and a system memory ([0042]-[0045] mentions system memory; Fig 1 shows memory includes 106, 124, 126 and other memories) ; wherein the computing system is configured to: initialize the system memory during a boot cycle (Fig 5 and Fig 6 show various memory initialization during boot cycle) ; store display data in the memory cache of the parallel processing core (L4 cache 126 shown in Fig 1; [0018] shared cache is used to store display device code used for display; [0033] – 159 is stored in cache) ; and during the initialization of the system memory (Fig 5; [0065] – display is brought for display by the memory initialization phase 530) , retrieve the stored display data from the memory cache ([0047] – enhance a boot process by extending cache memory to enable a multi-core environment; [0060] – multi-core availability and L4 cache as SRAM availability , display initialization runs parallel with other hardware initialization; [0082] – hardware initialization code is spread across all cores over parallel threads) for presentation on a display device that is communicatively coupled to the computing system ([0016] – display bring up; [0018][0033][0065] – display brought up by phase 530; [0016] mentions display panel). . For claim 16, Banik teaches wherein the memory cache of the parallel processing core configured to operate in a system memory emulation mode during the initialization of the system memory (Fig 5 – phase 510 – configure L4 cache as SRAM; [0065]). For claim 17, Banik teaches system configured to update the display data stored in the memory cache for presentation on the display device during the initializing of the system memory ([0033] storing display code in cache; [0070][0079] – frame buffer pointer toward cache, framebuffer programmed during SRAM initialization). For claim 18, Banik teaches wherein the display data stored in the memory cache for presentation on the display device comprises one or more of a group that includes a boot cycle progress indicator, diagnostic information, or status information regarding the computing system (Fig 5 and Fig 6 – boot cycle progress indicator “display on” is after SEC; the display is off in SEC 581 stage). For claim 19, Banik teaches the following limitations: A bootloader processor (processor 102 in Fig 1) configured to, during a first boot cycle (Fig 5 – Fig 7) of a computing system (Fig 8): initialize a system memory of the computing system (Fig 5 and Fig 6 show various memory initialization during boot cycle) ; store display data in a memory cache of a parallel processing core ( cache 126 shown in Fig 1; [0018] shared cache is used to store display device code used for display; [0033] – 159 is stored in cache) , wherein the parallel processing core is communicatively coupled to a general processing core of the computing system (Fig 1 shows various cores CORE 0 to CORE N; [0021]; [0067] mentions BSP core and AP cores; BSP core is the general purpose core; [0082] – parallel processing by AP) ; and during initialization of the system memory (Fig 5; [0065] – display is brought for display by the memory initialization phase 530) , retrieve the stored display data from the memory cache of the parallel processing core ([0047] – enhance a boot process by extending cache memory to enable a multi-core environment; [0060] – multi-core availability and L4 cache as SRAM availability , display initialization runs parallel with other hardware initialization; [0082] – hardware initialization code is spread across all cores over parallel threads) for presentation on a display device communicatively coupled to the computing system ([0016] – display bring up; [0018][0033][0065] – display brought up by phase 530; [0016] mentions display panel) . For claim 20, Banik teaches further configured to initiate an additional boot cycle of the computing system after the presentation of the stored display data ([0015][0038] ACPI off, working S0 mode; thus boot cycle is a recurring process and system goes to boot after power off every time; thus, additional boot cycle occurs after the system turns off) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 2-6, 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Banik et al (US Patent Application Publication 20210004241) in view of Pappu et al (US Patent Application Publication 20230113953) . For claims 2 and 11, Banik teaches memory initialization and memory training wherein initializing the system memory comprises generating memory training data for the system memory ([0082] – parallel initialization include memory initialization; [0051] – DRAM is trained), Although Banik teaches training the DRAM during reset, Banik does not explicitly mention saving the memory training data for future use. Pappu et al teaches that the memory training data is generated during booting and saving to use later ([0057]). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to generate the training data during boot and store the data for later use, since that way subsequent training can be faster as the data is already generated and stored. This operation enhances the performance. For claims 3 and 12, Pappu et al teach that the memory training data is generated during booting and saving in system memory to use later ([0057] [0053][0054][0061]). For claims 4 and 13, Pappu et al teach saving the memory training data comprises saving the memory training data in non-volatile memory of the computing system ([0057][0053][0054][0061]). For claim 5, Pappu et al teach further comprising initiating an additional boot cycle of the computing system after saving the memory training data, wherein the additional boot cycle omits generating memory training data ([0049][0057] [0054] – the previous boot generates memory training data, stored in memory to be used later and next boot cycle use them to retrain). For clam 6, Banik teaches wherein the general processing core is communicatively coupled to a bootloader processor that performs the method (Fig 1; [0082] BSP and AP are coupled together), and wherein the additional boot cycle comprises enabling the general processing core to load and initialize a basic input output system (BIOS) of the computing system (BSP enables BIOS code Fig 2A, Fig 2B; Fig 6 and [0082] – Banik; that is for each boot cycle of the system). For claim 14, Banik et al teach further comprising a bootloader processor communicatively coupled to the general processing core (Fig 1 shows multiple processor core; [0082] mentions boot by multiple cores in parallel; BSP and AP are coupled together). Pappu et al teach the bootloader processor is configured to initiate an additional boot cycle after the system memory initialization, the additional boot cycle omitting generating memory training data ([0049][0057] [0054] – the previous boot generates memory training data, stored in memory to be used later and next boot cycle use them to retrain). For claim 15, Banik teaches wherein the bootloader processor is configured to enable the general processing core to load and initialize a basic input output system (BIOS) of the computing system during the additional boot cycle ( BIOS code Fig 2A, Fig 2B; Fig 6 and [0082] – Banik; that is for each boot cycle of the system; [0082] BSP and AP works together and thus, enable each other). Conclusion PTO-892 cites references that are not relied upon for rejection but relevant to the invention, including: Wang et al that teaches cache providing video data in display before memory initialization ([0020]). Chen et al teach using cache to display on the display panel during booting ([0006]) Xu et al teaching memory training during booting (Fig 4) Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAHMIDA RAHMAN whose telephone number is (571)272-8159. The examiner can normally be reached Monday - Friday 10 AM - 7 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAHMIDA RAHMAN/Primary Examiner, Art Unit 2175 Application/Control Number: 18/969,372 Page 2 Art Unit: 2175 Application/Control Number: 18/969,372 Page 3 Art Unit: 2175 Application/Control Number: 18/969,372 Page 4 Art Unit: 2175 Application/Control Number: 18/969,372 Page 5 Art Unit: 2175 Application/Control Number: 18/969,372 Page 6 Art Unit: 2175 Application/Control Number: 18/969,372 Page 7 Art Unit: 2175 Application/Control Number: 18/969,372 Page 8 Art Unit: 2175 Application/Control Number: 18/969,372 Page 9 Art Unit: 2175
Prosecution Insights