DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kishore (US 10656203 B1) in view of Srinivasan (US 2019/0086474 A1).
In regards to claim 1, KISHORE teaches:
A test circuit comprising: a first input multiplexer configured to receive a first input data signal and a second input data signal; a second input multiplexer configured to receive a first output signal of the first input multiplexer and a third input data signal; (abstract, an apparatus for processor core testing. The apparatus generally includes a high-speed input-output (HSIO) interface, a general purpose input-output (GPIO) interface, a multiplexer having a first input coupled to the GPIO interface, a test controller coupled between the HSIO interface and a second input of the multiplexer, and one or more processor cores coupled to the output of the multiplexer.) a third input multiplexer configured to receive a second output signal of the second input multiplexer and a fourth input data signal; (Claim 19, a third multiplexer having inputs coupled to output of the OR gate and to the output of the voltage monitor, and an output coupled to additional circuitry) and output the received output data signal to at least one channel. (35, a 1 or 0 is generated at the corresponding channel. These channels may include test-data-in (TDI), test mode select (TMS), test reset negative asserted (TRSTN), test clock (TCK), scan input (SI), scan enable (SE), PLL test scan enable (PLL_TEST_SE), sleep clock (SLEEP_CLK), and mode select (MODE) channels for programming respective input of the SOC.)
KISHORE fails to teach:
a test block configured to generate an output data signal by performing a test operation based on an output of the third input multiplexer; and a gating circuit configured to receive the output data signal;
However, SRINIVASAN teaches:
a test block configured to generate an output data signal by performing a test operation based on an output of the third input multiplexer; and a gating circuit configured to receive the output data signal (0018, The output signal 83 from the OR gate 64 is coupled to a second input of a multiplexer 66. The output signal 81 from the voltage monitor 62 is also coupled to a first input of the multiplexer 66.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus for processor core testing of KISHORE with the teaching of SRINIVASAN, which teaches operating an electronic device during test mode operation in order to monitor voltage signals. (SRINIVASAN: 0005, during test mode operation of a duplicated voltage monitor by sensing a functional supply voltage with a voltage monitor)
In regards to claim 2, Kishore in view of Srinivasan teaches the test circuit of claim 1.
KISHORE fails to teach:
wherein the first input multiplexer receives a first control signal, the second input multiplexer receives a second control signal, and the third input multiplexer receives a third control signal, wherein each of the first input multiplexer, the second input multiplexer, and the third input multiplexer is configured to perform a multiplexing operation based on the first control signal, the second control signal, and the third control signal, respectively, and the first control signal, the second control signal, and the third control signal depend on an operation mode of the test circuit.
However, SRINIVASAN teaches:
wherein the first input multiplexer receives a first control signal, the second input multiplexer receives a second control signal, and the third input multiplexer receives a third control signal, wherein each of the first input multiplexer, the second input multiplexer, and the third input multiplexer is configured to perform a multiplexing operation based on the first control signal, the second control signal, and the third control signal, respectively, and the first control signal, the second control signal, and the third control signal depend on an operation mode of the test circuit. (0019, In a normal operation mode, a test mode select signal that controls the multiplexer 66 is at the second logic level, and a test mode signal 85 that controls the multiplexer 60 is at the second logic level.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus for processor core testing of KISHORE with the teaching of SRINIVASAN, which teaches operating an electronic device during test mode operation in order to monitor voltage signals. (SRINIVASAN: 0005, during test mode operation of a duplicated voltage monitor by sensing a functional supply voltage with a voltage monitor)
In regards to claim 3, Kishore in view of Srinivasan teaches the test circuit of claim 1.
KISHORE fails to teach:
wherein each of the first input multiplexer, the second input multiplexer, and the third input multiplexer is configured to perform a multiplexing operation based on a control signal depending on an operation mode, wherein, when the operation mode is a first operation mode, the first input multiplexer outputs the first input data signal as the first output signal, the second input multiplexer outputs the first output signal as the second output signal, and the third input multiplexer outputs the second output signal as the output of the third input multiplexer.
However, SRINIVASAN teaches:
wherein each of the first input multiplexer, the second input multiplexer, and the third input multiplexer is configured to perform a multiplexing operation based on a control signal depending on an operation mode, wherein, when the operation mode is a first operation mode, the first input multiplexer outputs the first input data signal as the first output signal, the second input multiplexer outputs the first output signal as the second output signal, and the third input multiplexer outputs the second output signal as the output of the third input multiplexer. (0012, A first multiplexer has inputs coupled to the test input and the power supply, and an output coupled to an input of the duplicate voltage monitor. The first multiplexer is controlled as a function of a first test selection signal.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus for processor core testing of KISHORE with the teaching of SRINIVASAN, which teaches operating an electronic device during test mode operation in order to monitor voltage signals. (SRINIVASAN: 0005, during test mode operation of a duplicated voltage monitor by sensing a functional supply voltage with a voltage monitor)
In regards to claim 4, Kishore in view of Srinivasan teaches the test circuit of claim 1.
KISHORE fails to teach:
wherein each of the first input multiplexer, the second input multiplexer, and the third input multiplexer is configured to perform a multiplexing operation based on a control signal depending on an operation mode, wherein, when the operation mode is a second operation mode, the first input multiplexer outputs the second input data signal as the first output signal, the second input multiplexer outputs the first output signal as the second output signal, and the third input multiplexer outputs the second output signal as the output of the third input multiplexer.
However, SRINIVASAN teaches:
wherein each of the first input multiplexer, the second input multiplexer, and the third input multiplexer is configured to perform a multiplexing operation based on a control signal depending on an operation mode, wherein, when the operation mode is a second operation mode, the first input multiplexer outputs the second input data signal as the first output signal, the second input multiplexer outputs the first output signal as the second output signal, and the third input multiplexer outputs the second output signal as the output of the third input multiplexer. (0012, A second multiplexer has inputs coupled to the test input and the power supply, and an output coupled to an input of the voltage monitor. The second multiplexer is controlled as a function of a second test selection signal.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus for processor core testing of KISHORE with the teaching of SRINIVASAN, which teaches operating an electronic device during test mode operation in order to monitor voltage signals. (SRINIVASAN: 0005, during test mode operation of a duplicated voltage monitor by sensing a functional supply voltage with a voltage monitor)
In regards to claim 5, Kishore in view of Srinivasan teaches the test circuit of claim 1.
KISHORE fails to teach:
wherein each of the first input multiplexer, the second input multiplexer, and the third input multiplexer is configured to perform a multiplexing operation based on a control signal depending on an operation mode, wherein, when the operation mode is a third operation mode, the second input multiplexer outputs the third input data signal as the second output signal, and the third input multiplexer outputs the second output signal as the output of the third input multiplexer.
However, SRINIVASAN teaches:
wherein each of the first input multiplexer, the second input multiplexer, and the third input multiplexer is configured to perform a multiplexing operation based on a control signal depending on an operation mode, wherein, when the operation mode is a third operation mode, the second input multiplexer outputs the third input data signal as the second output signal, and the third input multiplexer outputs the second output signal as the output of the third input multiplexer. (0019, In a normal operation mode, a test mode select signal that controls the multiplexer 66 is at the second logic level, and a test mode signal 85 that controls the multiplexer 60 is at the second logic level.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus for processor core testing of KISHORE with the teaching of SRINIVASAN, which teaches operating an electronic device during test mode operation in order to monitor voltage signals. (SRINIVASAN: 0005, during test mode operation of a duplicated voltage monitor by sensing a functional supply voltage with a voltage monitor)
In regards to claim 6, Kishore in view of Srinivasan teaches the test circuit of claim 1.
KISHORE fails to teach:
wherein each of the first input multiplexer, the second input multiplexer, and the third input multiplexer is configured to perform a multiplexing operation based on a control signal depending on an operation mode, and wherein, when the operation mode is a fourth operation mode, the third input multiplexer outputs the fourth input data signal as the output of the third input multiplexer.
However, SRINIVASAN teaches:
wherein each of the first input multiplexer, the second input multiplexer, and the third input multiplexer is configured to perform a multiplexing operation based on a control signal depending on an operation mode, and wherein, when the operation mode is a fourth operation mode, the third input multiplexer outputs the fourth input data signal as the output of the third input multiplexer. (0019 & Claim 19, In a normal operation mode, a test mode select signal that controls the multiplexer 66 is at the second logic level, and a test mode signal 85 that controls the multiplexer 60 is at the second logic level. a third multiplexer having inputs coupled to output of the OR gate and to the output of the voltage monitor)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus for processor core testing of KISHORE with the teaching of SRINIVASAN, which teaches operating an electronic device during test mode operation in order to monitor voltage signals. (SRINIVASAN: 0005, during test mode operation of a duplicated voltage monitor by sensing a functional supply voltage with a voltage monitor)
In regards to claim 7, Kishore in view of Srinivasan teaches the test circuit of claim 1.
KISHORE fails to teach:
wherein the gating circuit is connected to a first channel, a second channel, a third channel, and a fourth channel, and is configured to receive the output data signal and output the received output data signal to one of the first channel to the fourth channel.
However, SRINIVASAN teaches:
wherein the gating circuit is connected to a first channel, a second channel, a third channel, and a fourth channel, and is configured to receive the output data signal and output the received output data signal to one of the first channel to the fourth channel. (0012, A logic gate has inputs coupled to the outputs of the first and second multiplexers and performing a logical operation on signals received therefrom.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus for processor core testing of KISHORE with the teaching of SRINIVASAN, which teaches operating an electronic device during test mode operation in order to monitor voltage signals. (SRINIVASAN: 0005, during test mode operation of a duplicated voltage monitor by sensing a functional supply voltage with a voltage monitor)
In regards to claim 8, Kishore in view of Srinivasan teaches:
The test circuit of claim 7, wherein the gating circuit further comprises a first AND gate corresponding to the first channel and configured to receive a first enable signal, a second AND gate corresponding to the second channel and configured to receive a second enable signal, a third AND gate corresponding to the third channel and configured to receive a third enable signal, and a fourth AND gate corresponding to the fourth channel and configured to receive a fourth enable signal, and one of the first enable signal to the fourth enable signal is activated and remaining ones of the first enable signal to the fourth enable signal are deactivated. (38, Each of the AND gates 420, 422, 424 have an input coupled to a valid signal from the FIFOCTL module 304, indicating whether an input scan signal is valid, as will be described in more detail herein, as well as one or more enable signals (e.g., EN[0], EN[18:1], EN[19]), as illustrated.)
In regards to claim 9, Kishore in view of Srinivasan teaches the test circuit and corresponds to claim 1 as analyzed accordingly.
In regards to claim 10, Kishore in view of Srinivasan teaches:
The test circuit of claim 9, wherein each of the first input multiplexer, the second input multiplexer, the third input multiplexer, and the fourth input multiplexer is configured to perform the selection based on the first input enable signal, the second input enable signal, the third input enable signal, and the fourth input enable signal, respectively. (32, Each of the AND gates 420, 422, 424 have an input coupled to a valid signal from the FIFOCTL module 304, indicating whether an input scan signal is valid, as will be described in more detail herein, as well as one or more enable signals (e.g., EN[0], EN[18:1], EN[19]), as illustrated.)
In regards to claim 11, Kishore in view of Srinivasan teaches:
The test circuit of claim 10, wherein one of the first input enable signal to the fourth input enable signal is activated and remaining ones of the first input enable signal to the fourth input enable signal are deactivated. (33, each bit of DIN from bit 0 to bit 62 may be set to enable or disable a separate testing operation.)
In regards to claim 12, Kishore in view of Srinivasan teaches:
The test circuit of claim 9, wherein the gating circuit is connected to a first channel, a second channel, a third channel, and a fourth channel, and is configured to receive the output data signal and output the received output data to one of the first channel to the fourth channel. (34, a pulse may be generated on the corresponding clock channel via the clock generation module 310.)
In regards to claim 13, Kishore in view of Srinivasan teaches:
The test circuit of claim 12, wherein the gating circuit further comprises a first output multiplexer corresponding to the first channel; a second output multiplexer corresponding to the second channel; a third output multiplexer corresponding to the third channel; and a fourth output multiplexer corresponding to the fourth channel. (38, The clock gate circuits 408, 410, 412 provide respective input clocks to respective PDLs 402, 404, 406 if the output of respective AND gates 420, 422, 424 are logic high.)
In regards to claim 14, Kishore in view of Srinivasan teaches the test circuit of claim 13.
KISHORE fails to teach:
wherein the first output multiplexer is configured to gate the output data signal based on a first output enable signal, the second output multiplexer is configured to gate the output data signal based on a second output enable signal, the third output multiplexer is configured to gate the output data signal based on a third output enable signal, and the fourth output multiplexer is configured to gate the output data signal based on a fourth output enable signal.
However, SRINIVASAN teaches:
wherein the first output multiplexer is configured to gate the output data signal based on a first output enable signal, the second output multiplexer is configured to gate the output data signal based on a second output enable signal, the third output multiplexer is configured to gate the output data signal based on a third output enable signal, and the fourth output multiplexer is configured to gate the output data signal based on a fourth output enable signal. (0012 The first multiplexer is controlled as a function of a first test selection signal. The second multiplexer is controlled as a function of a second test selection signal.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus for processor core testing of KISHORE with the teaching of SRINIVASAN, which teaches operating an electronic device during test mode operation in order to monitor voltage signals. (SRINIVASAN: 0005, during test mode operation of a duplicated voltage monitor by sensing a functional supply voltage with a voltage monitor)
In regards to claim 15, Kishore in view of Srinivasan teaches the test circuit of claim 14.
KISHORE fails to teach:
wherein each of the first output multiplexer to the fourth output multiplexer is configured to select a signal based on the first output enable signal to the fourth output enable signal, respectively.
However, SRINIVASAN teaches:
wherein each of the first output multiplexer to the fourth output multiplexer is configured to select a signal based on the first output enable signal to the fourth output enable signal, respectively. (0012, The first multiplexer is controlled as a function of a first test selection signal. The second multiplexer is controlled as a function of a second test selection signal.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus for processor core testing of KISHORE with the teaching of SRINIVASAN, which teaches operating an electronic device during test mode operation in order to monitor voltage signals. (SRINIVASAN: 0005, during test mode operation of a duplicated voltage monitor by sensing a functional supply voltage with a voltage monitor)
In regards to claim 16, Kishore in view of Srinivasan teaches:
The test circuit of claim 15, wherein one of the first output enable signal to the fourth output enable signal is activated and remaining ones of the first output enable signal to the fourth output enable signal are deactivated. (38, The PDLs 402, 404, 406 may be coupled to outputs of clock gate (CG) circuits 408, 410, 412, as illustrated. The clock gate circuits 408, 410, 412 provide respective input clocks to respective PDLs 402, 404, 406 if the output of respective AND gates 420, 422, 424 are logic high;)
In regards to claim 17, KISHORE teaches:
An integrated circuit comprising: a plurality of channels; (14 & 34, The SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversions, and/or wireless data transmissions, and for performing other specialized operations (e.g., decoding high-definition video, video processing, etc.). If DATA[63] indicates that that DIN is a DATA packet, DATA[62:0] are used as access to test-channels.) an input gating circuit including a plurality of input terminals including a first input terminal, each input terminal of the plurality of input terminals connected to a different channel among the plurality of channels, and configured to output a signal received through the first input terminal as an input data signal; (38, The test voltage supply 54 is applied to the test input pad 51 during test operations.) and an output gating circuit including a plurality of output terminals including a first output terminal, each output terminal of the plurality of output terminals connected to a different channel among the plurality of channels, and configured to output the output data signal through the first output terminal. (35, a 1 or 0 is generated at the corresponding channel. These channels may include test-data-in (TDI), test mode select (TMS), test reset negative asserted (TRSTN), test clock (TCK), scan input (SI), scan enable (SE), PLL test scan enable (PLL_TEST_SE), sleep clock (SLEEP_CLK), and mode select (MODE) channels for programming respective input of the SOC.)
KISHORE fails to teach:
at least one intellectual property (IP) block; a test block configured to generate an output data signal by testing the at least one IP block based on the input data signal;
However, SRINIVASAN teaches:
at least one intellectual property (IP) block; (0016, which is illustratively coupled to receive a test voltage 73 from a test voltage supply 54. The test voltage supply 54 is applied to the test input pad 51 during test operations.) a test block configured to generate an output data signal by testing the at least one IP block based on the input data signal; (0018, The output signal 83 from the OR gate 64 is coupled to a second input of a multiplexer 66. The output signal 81 from the voltage monitor 62 is also coupled to a first input of the multiplexer 66.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus for processor core testing of KISHORE with the teaching of SRINIVASAN, which teaches operating an electronic device during test mode operation in order to monitor voltage signals. (SRINIVASAN: 0005, during test mode operation of a duplicated voltage monitor by sensing a functional supply voltage with a voltage monitor)
In regards to claim 18, Kishore in view of Srinivasan teaches:
The integrated circuit of claim 17, wherein the input gating circuit receives a signal through an input terminal other than the first input terminal among the plurality of input terminals based on an input control signal. (34 & 38, a pulse may be generated on the corresponding clock channel via the clock generation module 310. The clock gate circuits 408, 410, 412 provide respective input clocks to respective PDLs 402, 404, 406 if the output of respective AND gates 420, 422, 424 are logic high.)
In regards to claim 19, Kishore in view of Srinivasan teaches:
The integrated circuit of claim 17, wherein the output gating circuit outputs a signal through an output terminal other than the first output terminal among the plurality of output terminals based on an output control signal. (35, a 1 or 0 is generated at the corresponding channel. These channels may include test-data-in (TDI), test mode select (TMS), test reset negative asserted (TRSTN), test clock (TCK), scan input (SI), scan enable (SE), PLL test scan enable (PLL_TEST_SE), sleep clock (SLEEP_CLK), and mode select (MODE) channels for programming respective input of the SOC.)
In regards to claim 20, Kishore in view of Srinivasan teaches:
The integrated circuit of claim 17, wherein, among the plurality of input terminals, input terminals other than the first input terminal are disabled, among the plurality of output terminals, at least one output terminal other than the first output terminal is disabled. (33, each bit of DIN from bit 0 to bit 62 may be set to enable or disable a separate testing operation.)
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
Beal (US 8258811 B2): An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
• Walker (US 8081532 B2): semiconductor device includes a first temperature sensing circuit, a multiplexer, and an output circuit. The first temperature sensing circuit can be configured to provide a first temperature indication based on a first temperature threshold value. The first temperature indication can include a first temperature indication logic level. The multiplexer can include a first multiplexer input configured to receive the first temperature indication, a second multiplexer input configured to receive a data signal, and a third multiplexer input configured to receive a temperature read enable signal. The multiplexer can be configured to provide a first multiplexer output. The output circuit can include a first output terminal. The output circuit can be configured to receive the first multiplexer output. The multiplexer and the output circuit can be configured to provide the first temperature indication to the first output terminal when the temperature read enable is enabled.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to VICTOR PERRY whose telephone number is (571)272-6319. The examiner can
normally be reached Monday - Friday 8:00 - 5:00.
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/ Primary Examiner, Art Unit 2111 4/16/2026
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