DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 12/05/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on 12/05/24.
Figures 4A and 4B should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
Fig. 5 and fig. 8 – broken dashed line with reference number 150 appears to be external voltage regulators, however there is no mention of “150” in the specification
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 10-12 and 19-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Rutkowski (US 20230066436 A1).
Regarding claim 1 and 19, Rutkowski discloses a method and semiconductor device (fig. 1 and 2, PMIC 126) comprising: a voltage regulator (fig. 1 and 2, voltage regulator 128); a semiconductor integrated circuit (IC) chip (par [0058] “components illustrated in the various figures may be integrated on a single IC chip or distributed across multiple IC chips, which are packaged together or separately”) including a load circuit (fig 2, load 206) configured to receive a load current from the voltage regulator (implicitly taught with the direct connection to voltage regulator 128 in fig. 2); and a substrate including an electrical path configured to provide a signal to at least one of the voltage regulator or the semiconductor IC chip (fig. 2, PMIC; it is well known that PMIC’s always contain a substrate, IC chip serving as blocks of semiconductor materials, and electrical paths of conductive materials to move voltage/current), wherein the voltage regulator includes: a capacitor including one end connected to an output node and the other end connected to a ground (fig. 3-1 or 5-1, output capacitor 322 coupled between the output node 314 and the ground node 318); an inductor connecting the output node to an input node (figs. 3, 3-1, and 5-1, inductor 312 connected between first and second supply voltages 304-1 and 304-2 and switching node 504 and output node 314); and a first switch, a second switch, and a third switch, one end of each switch respectively connected to the input node (fig. 5-1, switches 502-1, 502-2, and 502-3 all connected to power supply rails 302-1 and 302-2 and switching node 504) wherein the first switch, the second switch, and the third switch alternately provide a first input voltage, a second input voltage, and a ground voltage to the input node, respectively (figs. 5-1, and figs. 6-1 to 6-3 illustrate examples for one or more buck modes with various charging and discharging operations where each of the multiple switches are depicted in alternating states).
Regarding claim 2, Rutkowski discloses the semiconductor device of claim 1, wherein the substrate includes at least a portion of the inductor, wherein the voltage regulator is an integrated voltage regulator integrated into the semiconductor IC (par [0058] “PCB may include the PMIC 126 or the voltage regulator 128…components illustrated in the various figures may be integrated on a single IC chip or distributed across multiple IC chips, which are packaged together or separately”).
Regarding claim 3, Rutkowski discloses the semiconductor device of claim 1, wherein the first switch, the second switch, and the third switch are sequentially turned on at different time intervals, when any one of the first switch, the second switch, and the third switch is turned on, the remaining switches are turned off (par [0085-0086] describes the alternating of open and close of the switches as depicted in figs 6-1 to 6-4 where the labels “D” and “1-D” indicate that corresponding switches are in inverted states during a given mode (e.g., if one switch is open, the other is closed)).
Regarding claim 4, Rutkowski discloses the semiconductor device of claim 3, wherein the second switch is turned on for a longer time interval than the first switch (fig. 7-1 and pars [0097-0100]; SW1 is closed for ~2.75 cycles and SW2 is closed for ~.25 of a cycle once SW1 closes; par [0900] explains that the first supply voltage 304-1 of the first voltage rail 302-1 is approximately equal to the targeted output voltage 316, and a second supply voltage 304-2 (e.g., of FIG. 3) of the second voltage rail 302-2 continues to be substantially greater than the targeted output voltage 316; this is opposite of the instant applications Vin1 being greater and VIN2 being greater or equal to or less than the output voltage; the operation explained in the disclosure of Rutkowski would be different because of the difference in the supply voltages from the instant application, however the operations of buck mode are anticipated in Rutkowski).
Regarding claim 5, Rutkowski discloses the semiconductor device of claim 3, wherein the first switch provides the first input voltage to the input node by turning on, the second switch provides the second input voltage to the input node by turning on, and the third switch provides the ground voltage to the input node by turning on (fig. 5-1, when each switch is in the on/closed position it supplies voltage to node 504 correlating to the instant applications “Nin” input node; see pars [0079-0080,0085]), wherein the first input voltage is greater than an output voltage of the output node, and the second input voltage is greater than, less than, or equal to the output voltage (par [0089] the first supply voltage 304-1 of the first voltage rail 302-1 is approximately equal to the targeted output voltage 316, and a second supply voltage 304-2 (e.g., of FIG. 3) of the second voltage rail 302-2 continues to be substantially greater than the targeted output voltage 316; note: this is opposite from the naming convention of the instant applications S1/S2 VIN1/VIN2, see fig 5-1, VR1/VR2 and SW1/SW2; SW3 is connected to ground).
Regarding claim 6, Rutkowski discloses the semiconductor device of claim 1, wherein the first input voltage is greater than the second input voltage (Rutkowski’s SW2/VR2 is substantially greater than VR1/SW1 in fig 5-1 par [0089], note: this is opposite of what is taught in the instant application however operations of buck mode are anticipated in Rutkowski).
Regarding claim 7, Rutkowski discloses the semiconductor device of claim 5, wherein the inductor operates in a first charging step by turning on the first switch, in a second charging step by turning on the second switch, in a discharging step by turning on the third switch, and in the second charging step after the first charging step (figs. 6-1 and 6-2 and par [0086] a thick solid line represents a current flow for a charging operation, and a thick short-dashed line represents a current flow for a discharging operation, note: VR1/SW1 corresponds to instant applications VIN2/S2 and the bucking modes can, however, also be implemented with a buck converter that lacks the fourth and fifth switches 502-4 and 502-5 (e.g., using the buck converter 402-1 of FIGS. 5-1) see par [0085]; see pars [0089-0091] for buck mode operations).
Regarding claim 8, Rutkowski discloses the semiconductor device of claim 5, wherein the inductor operates in a charging step by turning on the first switch, in a first discharging step by turning on the second switch, in a second discharging step by turning on the third switch, and in a second discharging step after the first discharging step (pars [0085-0091] describe charging and discharging related to switches SW1-SW3 and optionally SW4-SW5 in 3 modes of buck operations).
Regarding claim 10, Rutkowski discloses the semiconductor device of claim 1, further comprising: a controller (fig. 8, controller 800) configured to generate switch driving signals which respectively control the first switch, the second switch, and the third switch (fig. 8, control signals 820 for switches 502), wherein the controller stops or operates the second switch based on a mode control signal (fig. 8, FSM 812, par [0128] produce multiple switch control signals 820 …can open or close the first, second, and third switches 502-1, 502-2, and 502-3 for one or more bucking modes).
Regarding claim 11, Rutkowski discloses the semiconductor device of claim 10, wherein the controller operates the second switch in response to a first mode indicated by the mode control signal and stops an operation of the second switch in response to a second mode indicated by the mode control signal (fig. 9, par [0133] selectively coupling a first voltage rail or a second voltage rail but not both in response to the switching control signals from the FSM 812 in the control circuit 800 to change or establish open/closed states of each of the switches to control the voltage regulator 128).
Regarding claim 12, Rutkowski discloses the semiconductor device of claim 1, wherein the voltage regulator further includes a controller configured to generate switch driving signals which respectively control the first switch, the second switch, and the third switch, wherein the controller controls a time interval in which the second switch is turned on based on a target voltage to be provided to the output node (fig. 7-1, pars [0090,0097-0098, 0113] the controller controls the duty cycle of the individual switches in order to control the output voltage based on the target voltage and each mode is selectively chosen to charge or discharge accordingly).
Regarding claim 20, it is the method version of claims 2 and 5 and is rejected for the same reasons listed above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Rutkowski (US 20230066436 A1) and further in view of Burkhart et al. (US 20240291371 A1) hereinafter Burkhart.
Regarding claim 9, Rutkowski discloses the semiconductor device of claim 1. Rutkowski fails to disclose wherein the voltage regulator is composed of a plurality of voltage regulators sharing one capacitor, wherein each of the plurality of voltage regulators generates load currents having different phases.
Burkhart discloses the voltage regulator (fig 3, multi-frequency voltage regulator 310) is composed of a plurality of voltage regulators sharing one capacitor (fig 3, first and second converters 312/314), wherein each of the plurality of voltage regulators generates load currents having different phases (par [0034] “multiple phases can allow a DC/DC converter to operate with higher bandwidth and/or transient response for the same inductance per phase and/or switching frequency”; par [0034] “multi-phase converter”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Rutkowski and incorporate the use of two voltage regulators as separate inputs to the voltage regulator as taught by Burkhart. The advantage of this design is to provide two regulated inputs of different frequencies to achieve efficiency and regulation accuracy.
Regarding claim 13, Rutkowski discloses an electronic device (fig. 1, electronic device 102) comprising: a power management device (fig 1, PMIC), wherein the IVR includes: a plurality of switches configured to alternately provide the first input voltage, the second input voltage, and a ground voltage to an inductor (fig. 5-1, switches 502-1, 502-2, and 502-3 connected to power supply rails 302-1 and 302-2 and ground 318 and switching node 504 to inductor 312); the inductor configured to alternately receive the first input voltage, the second input voltage, and the ground voltage, and to provide the load current to the output node (fig. 5-1; par [0066] “the control circuitry 308 opens and closes one or more switches of the multiple switches 310 to selectively couple the energy storage unit 312 to the first voltage rail 302-1, the second voltage rail 302-2, or the ground node 318”); and a capacitor configured to connect the output node to a ground (fig. 3-1 or 5-1, output capacitor 322 coupled between the output node 314 and the ground node 318).
Rutkowski discloses dual inputs to the 3-level converter however, Rutkowski fails to disclose separate voltage regulators to provide dual inputs to the 3-level converter.
Burkhart discloses multi-frequency voltage regulator and 3-level buck converter as a variation of buck converter 100 where voltage vx can be switched to either V.sub.IN, V.sub.IN/2, or GND such as in the instant application. Burkhart is also concerned with design space, efficiency, and removing the high quality flying capacitor (par [0027-0028]). Burkhart discloses a first voltage regulator (figs. 3 and 4, first converter 312/412) configured to receive a battery voltage (figs. 3 and 4, input voltage 320/420A) and to generate a first input voltage which is regulated (figs. 3 and 4, output voltage 322/422; par [0038] “each of the voltage converter circuits (e.g., first voltage converter circuit 312 and second voltage converter circuit 314) can received input voltage 320 and in conjunction produce output voltage 322”) and a second voltage regulator (figs. 3 and 4, second converter 314/414) configured to receive the battery voltage (figs. 3 and 4, input voltage 320/420B) and to generate a second input voltage which is regulated (figs. 3 and 4, output voltage 322/422; par [0038]); and a system-on-chip (SOC) (fig. 5, device package 500; par [0053] “systems on a chip (SoCs)”) including an integrated voltage regulator (IVR) (fig. 5, Multi-frequency IVR 510) configured to generate a load current based on the first input voltage and the second input voltage (par [0044] “Multi-frequency IVR 510 can include a control circuit for regulating the supply voltage to the load (e.g., die 530) using first voltage regulator circuit 512 and/or second voltage regulator circuit 514”), and a load circuit configured to receive the load current through an output node (fig 5, 530; par [0043] “Die 530 generally represents a load of multi-frequency IVR 510”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Rutkowski and incorporate the use of two voltage regulators as separate inputs to the voltage regulator as taught by Burkhart. The advantage of this design is to provide two regulated inputs of different frequencies to achieve efficiency and regulation accuracy.
Regarding claim 14, Rutkowski and Burkhart disclose the electronic device of claim 13, wherein the first voltage regulator and the second voltage regulator generate the first input voltage and the second input voltage (Rutkowski’s voltage regulator 500-1 of fig. 5-1 with first voltage rail 302-1, the second voltage rail 302-2, and ground node 318 modified with Burkharts dual voltage regulators to produce input voltages based on the battery voltage input), respectively, based on the battery voltage and the ground voltage.
Regarding claim 15, Rutkowski and Burkhart disclose the electronic device of claim 14, wherein the first voltage regulator includes a first inductor, and the second voltage regulator includes a second inductor, wherein the first inductor and the second inductor operate in two steps (Burkhart’s fig 1A buck converter circuit undergoes continuous charging and discharging cycles based on the state of the MOSFET switches), and the inductor operates in three steps (Rutkowski’s fig. 5-1, 3-level buck converter operate in those three primary steps as part of a switching regulator cycle. Charging Step: When either SW1 or SW2 is closed and SW3 is open, the inductor is connected to a voltage rail VR1 or VR2. Current flows through it, storing energy in its magnetic field. Discharging Step: When the high-side switches are opened and SW3 is closed, the inductor's stored energy is released to the Load 206 and C.out 322. The inductor maintains current flow as its magnetic field collapses. Neutral Step: where all switches are open and the inductor current has reached zero. In this "idle" state, it is neither storing nor releasing energy).
Regarding claim 16, Rutkowski and Burkhart disclose the electronic device of claim 15, wherein the first inductor and the second inductor operate in a charging step and a discharging step, wherein the inductor: operates in a first charging step, a second charging step, and a discharging step, operates in a charging step, a first discharging step, and a second discharging step, or operates in a charging step, a neutral step, and a discharging step (Burkhart’s fig 1A buck converter circuit undergoes continuous charging and discharging cycles based on the state of the MOSFET switches; Rutkowski’s fig. 5-1, 3-level buck converter operate in those three primary steps as part of a switching regulator cycle. Charging Step: When either SW1 or SW2 is closed and SW3 is open, the inductor is connected to a voltage rail VR1 or VR2. Current flows through it, storing energy in its magnetic field. Discharging Step: When the high-side switches are opened and SW3 is closed, the inductor's stored energy is released to the Load 206 and C.out 322. The inductor maintains current flow as its magnetic field collapses. Neutral Step: where all switches are open and the inductor current has reached zero. In this "idle" state, it is neither storing nor releasing energy).
Regarding claim 17, Rutkowski and Burkhart disclose the electronic device of claim 13, wherein the plurality of switches include a first switch, a second switch, and a third switch, wherein the first switch, the second switch, and the third switch are sequentially turned on at different time intervals, when any one of the first switch, the second switch, and the third switch is turned on, the remaining switches are turned off (Rutkowski figs 5-1 and 6-1; par [0085-0086] describes the alternating of open and close of the switches as depicted in figs 6-1 to 6-4 where the labels “D” and “1-D” indicate that corresponding switches are in inverted states during a given mode (e.g., if one switch is open, the other is closed)).
Regarding claim 18, Rutkowski and Burkhart disclose the electronic device of claim 17, wherein the first input voltage is greater than the second input voltage (Rutkowski’s SW2/VR2 is substantially greater than VR1/SW1 in fig 5-1 par [0089], note: this is opposite of what is taught in the instant application however operations of buck mode are anticipated in Rutkowski).
Conclusion
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838 /THIENVU V TRAN/Supervisory Patent Examiner, Art Unit 2838
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