DETAILED ACTION
This office action is in response to the application filed on 12/5/24.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Inventorship
This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of 35 U.S.C. 103(c) and potential 35 U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103(a).
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7, 8, 10 and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leonard (US20090121549).
Regarding Claim 1, Leonard discloses a method for controlling an inverter (Figure 1, inverter 10; Paragraphs 12-23), wherein the inverter comprises a plurality of boost circuits (Figure 1, each boost converter 26 comprising an inductor 32, a switch 28 and a diode 33; Paragraphs 12-23), a direct current bus and an inversion circuit (Figure 1, inversion circuit 37; Paragraphs 12-23), an output terminal of each of the plurality of boost circuits is connected to the direct current bus (Figure 1; Paragraphs 12-23), the inversion circuit obtains a direct current from the direct current bus and converts the direct current to an alternating current for output (Figure 1, the output of the inverter 10 is connected to the AC grid 14; Paragraphs 12-23), wherein the method comprises: determining a maximum voltage among voltages at input terminals of the plurality of boost circuits (Paragraph 44 discloses that the boost circuit having the greatest Vmpp is disabled. It is therefore implicit to consider that the method comprises determining a maximum voltage among voltages at input terminals of the plurality of boost circuits) and a minimum voltage for grid-connection required by the inverter for grid-connection (Paragraphs 47-48); stopping boosting a first boost circuit in the inverter in a case that the maximum voltage is greater than or equal to the minimum voltage for grid-connection (Paragraph 43); wherein a voltage at an input terminal of the first boost circuit is greater than or equal to the minimum voltage for grid-connection, and the first boost circuit comprises a boost circuit, among the plurality of boost circuits, which corresponds to the maximum voltage (Paragraph 43); and controlling a voltage at an output terminal of a second boost circuit to be increased to the maximum voltage, wherein the second boost circuit comprises the plurality of boost circuits in the inverter other than the first boost circuit (Paragraph 43).
Regarding Claim 2, Leonard discloses (fig. 1) controlling voltages of output terminals of the plurality of boost circuits comprised in the inverter to be increased to the minimum voltage for grid-connection, in a case that the maximum voltage is less than the minimum voltage for grid-connection (¶43 discloses that for those PV arrays having Vmpp below the reduced DC link voltage, their respective boost circuits continue to increase their voltage).
Regarding Claim 3, Leonard discloses (fig. 1) the first boost circuit is the boost circuit corresponding to the maximum voltage (¶43-44).
Regarding Claim 7, Leonard discloses (fig. 1) the stopping boosting the first boost circuit in the inverter comprises: controlling a switching device in the first boost circuit to be turned off; the controlling the voltage at the output terminal of the second boost circuit to be increased to the maximum voltage comprises: controlling a switching device in the second boost circuit to be turned on to increase the voltage at the output terminal of the second boost circuit to the maximum voltage (¶43).
Regarding Claim 8, Leonard discloses (fig. 1) An inverter (Figure 1, inverter 10; Paragraphs 12-23), comprising: a plurality of boost circuits (Figure 1, each boost converter 26 comprising an inductor 32, a switch 28 and a diode 33; Paragraphs 12-23), and input terminals of the plurality of the boost circuits are connected to direct current sources, output terminals of the plurality of boost circuits are connected to a direct current bus, an output terminal of the inverter is connected to a power grid (14) to operate in a gird-connected state, wherein the inverter implements a method for controlling the inverter, wherein the method comprises: determining a maximum voltage among voltages at input terminals of the plurality of boost circuits and a minimum voltage for grid-connection required by the inverter for grid-connection; stopping boosting a first boost circuit in the inverter in a case that the maximum voltage is greater than or equal to the minimum voltage for grid-connection (Paragraph 44 discloses that the boost circuit having the greatest Vmpp is disabled. It is therefore implicit to consider that the method comprises determining a maximum voltage among voltages at input terminals of the plurality of boost circuits); wherein a voltage at an input terminal of the first boost circuit is greater than or equal to the minimum voltage for grid-connection, and the first boost circuit comprises a boost circuit, among the plurality of boost circuits, which corresponds to the maximum voltage; and controlling a voltage at an output terminal of a second boost circuit to be increased to the maximum voltage, wherein the second boost circuit comprises the plurality of boost circuits in the inverter other than the first boost circuit (Paragraph 43).
Regarding Claim 10, Leonard discloses (fig. 1) the method further comprises: controlling voltages of output terminals of the plurality of boost circuits comprised in the inverter to be increased to the minimum voltage for grid-connection, in a case that the maximum voltage is less than the minimum voltage for grid-connection (¶43 discloses that for those PV arrays having Vmpp below the reduced DC link voltage, their respective boost circuits continue to increase their voltage).
Regarding Claim 14, Leonard discloses (fig. 1) the stopping boosting the first boost circuit in the inverter comprises: controlling a switching device in the first boost circuit to be turned off; the controlling the voltage at the output terminal of the second boost circuit to be increased to the maximum voltage comprises: controlling a switching device in the second boost circuit to be turned on to increase the voltage at the output terminal of the second boost circuit to the maximum voltage (¶43).
Regarding Claim 15, Leonard discloses (fig. 1) A device for controlling an inverter (Figure 1, inverter 10; Paragraphs 12-23), wherein the inverter comprises a plurality of boost circuits (Figure 1, each boost converter 26 comprising an inductor 32, a switch 28 and a diode 33; Paragraphs 12-23), a direct current bus and an inversion circuit; output terminals of the plurality of boost circuits are connected to the direct current bus, and the inversion circuit obtains a direct current from the direct current bus and converts the direct current to an alternating current for output, the device comprises: a determination unit, configured to determine a maximum voltage among voltages at input terminals of the plurality of boost circuits and a minimum voltage for grid-connection required by the inverter for grid-connection (Paragraph 44 discloses that the boost circuit having the greatest Vmpp is disabled. It is therefore implicit to consider that the method comprises determining a maximum voltage among voltages at input terminals of the plurality of boost circuits); a regulation unit, configured to stop boosting a first boost circuit in the inverter in a case that the maximum voltage is greater than or equal to the minimum voltage for grid-connection; wherein a voltage at an input terminal of the first boost circuit is greater than or equal to the minimum voltage for grid-connection, and the first boost circuit comprises a boost circuit, among the plurality of boost circuits, which corresponds to the maximum voltage; and a processing unit, configured to control a voltage at an output terminal of a second boost circuit to be increased to the maximum voltage, wherein the second boost circuit comprises the plurality of boost circuits in the inverter other than the first boost circuit (¶43).
Regarding Claim 16, Leonard discloses a photovoltaic system (fig. 1), comprising: photovoltaic strings PV (12s); an inverter comprising boost circuits (19), an inversion circuit (37) and a direct current bus (36); wherein output terminals of the photovoltaic strings PVs are connected to input terminals of the boost circuits, output terminals of the boost circuits are connected to the direct current bus, an output terminal of the direct current bus is connected to the inversion circuit, an output terminal of the inversion circuit is connected to the power grid, and the power grid is connected to a load; the inverter implements the method for controlling the inverter according to claim 1 (fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 9 and 13 are rejected under 35 U.S.C. 103(a) as being unpatentable over Leonard in view of Adest et al. (US20080164766, hereinafter Adest).
Regarding Claims 6, 9 and 13, Leonard does not disclose controlling a bypass circuit of the first boost circuit to be turned on to short-circuit the first boost circuit; wherein each of the plurality of boost circuits is connected to a bypass circuit in parallel, and the bypass circuit is conductive from the input terminal of the boost circuit to the output terminal of the boost circuit in a unidirectional direction; the controlling the voltage at the output terminal of the second boost circuit to be increased to the maximum voltage comprises: controlling a bypass circuit of the second boost circuit to be turned off to increase the voltage at the output terminal of the second boost circuit to the maximum voltage
Adest discloses controlling a bypass circuit of the first boost circuit to be turned on to short-circuit the first boost circuit; wherein each of the plurality of boost circuits is connected to a bypass circuit in parallel, and the bypass circuit is conductive from the input terminal of the boost circuit to the output terminal of the boost circuit in a unidirectional direction (fig. 7, ¶68).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Leonard to include boost bypass as disclosed in Adest to improve reliability of system due to isolated boost failure.
Allowable Subject Matter
Claims 4, 5, 11 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior art fails to disclose: “...the voltage at the input terminal is greater than or equal to a first threshold; wherein the first threshold is a larger one between the minimum voltage for grid-connection and the maximum voltage minus a first voltage difference, and the first voltage difference is the maximum voltage multiplied by a minimum boosting ratio minus the maximum voltage, wherein the minimum boosting ratio corresponds to the boost circuit corresponding to the maximum voltage.” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 5, the prior art fails to disclose: “...the minimum voltage for grid-connection is obtained from multiplying a voltage of a power grid by 1.414 plus a first value, and the first value ranges from 0 to 20V.” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 11, the prior art fails to disclose: “...the first boost circuit is a boost circuit, among the plurality of boost circuits, of which the voltage at the input terminal is greater than or equal to a first threshold; wherein the first threshold is a larger one between the minimum voltage for grid-connection and the maximum voltage minus a first voltage difference, and the first voltage difference is the maximum voltage multiplied by a minimum boosting ratio minus the maximum voltage, wherein the minimum boosting ratio corresponds to the boost circuit corresponding to the maximum voltage..” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 12, the prior art fails to disclose: “...the minimum voltage for grid-connection is obtained from multiplying a voltage of a power grid by 1.414 plus a first value, and the first value ranges from 0 to 20V.” in combination with the additionally claimed features, as are claimed by the Applicant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 10505437, Tsai; Tsung-Han et al. discloses a power converting device and ground impedance value detecting method.
US 11264947, Adest; Meir et al. discloses testing of a photovoltaic panel.
US 8018748, Leonard; John Andrew discloses a method and system to convert direct current (DC) to alternating current (AC) using a photovoltaic inverter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE J MOODY whose telephone number is (571)272-5242. The examiner can normally be reached on M-F 10 AM - 4 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KYLE J MOODY/
Primary Examiner, Art Unit 2838
Prosecution Insights