Prosecution Insights
Last updated: October 27, 2026
Application No. 18/969,731

LIGHT EMITTING DIODE DISPLAY DEVICE

Non-Final OA §102
Filed
Dec 05, 2024
Priority
Dec 19, 2022 — RE 10-2022-0177897 +1 more
Examiner
BRIGGS, NATHANAEL R
Art Unit
2871
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
841 granted / 1102 resolved
+8.3% vs TC avg
Moderate +11% lift
Without
With
+11.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
17 currently pending
Career history
1126
Total Applications
across all art units

Statute-Specific Performance

§103
58.9%
+18.9% vs TC avg
§102
32.4%
-7.6% vs TC avg
§112
6.2%
-33.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1102 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3-8 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kimura et al. (US 2012/0194749). Regarding claim 1, Kimura discloses a light emitting diode display device (see figures 11A-11B, for instance) comprising: a light emitting diode (including elements 1114 and 1110 at least) over a substrate (1101); an optical element (1306) including a liquid crystal molecule (1322) randomly distributed (see figure 11B) therein and configured to change a path of light emitted from the light emitting diode (1110); a first planarization layer (1109) including a groove (contact hole accommodating 1111c to connect to 1117c); the light emitting diode (including portion of element 1111c in the contact hole) in the groove (see fig. 11A); and a second planarization layer (1108) over the first planarization layer (1109), wherein the second planarization layer (1108) covers a side surface and an upper surface of the light emitting diode (see 1108 covering top and sides of 1110). Regarding claim 3, Kimura discloses the light emitting diode display device according to claim 1, further comprising a bank (1103) provided on (with intervening layers provided therebetween) the first planarization layer (1109). Regarding claim 4, Kimura discloses the light emitting diode display device according to claim 3, wherein the bank (1103) includes an opening area (including 1104) corresponding to a light emitting area through which light emitted from the light emitting diode (1110) is emitted to outside. Regarding claim 5, Kimura discloses the light emitting diode display device according to claim 4, wherein the optical element (1306) has an area equal to or larger than that of the light emitting area (1104) and is disposed to at least partially overlap the light emitting area (see figure 11A). Regarding claim 6, Kimura discloses the light emitting diode display device according to claim 3, further comprising a third planarization layer (see intervening layer between 1105 and 1103 in figure 11A) provided on the bank (1103). Regarding claim 7, Kimura discloses the light emitting diode display device according to claim 6, wherein the light emitting diode comprises: a first semiconductor layer (1117c); an active layer (1116b) over one side of the first semiconductor layer; a second semiconductor layer (1117d) over the active layer; a first electrode (1111c) over the second semiconductor layer; and a second electrode (1111d) over the other side of the first semiconductor layer; and light emitting diode display device further comprises: a first connection electrode (1122) over the second planarization layer and configured to electrically connect the first electrode, and a second connection electrode (portion of 1111d between top surface of 1109 and 1117d) over the second planarization layer and configured to electrically connect the second electrode (see figure 11A). Regarding claim 8, Kimura discloses the light emitting diode display device according to claim 7, wherein the third planarization layer (intervening layer between 1103 and 1105, see fig. 11A) is on the first connection electrode and the second connection electrode (since the layer overlaps in plan view both elements). Regarding claim 17, Kimura discloses the light emitting diode display device according to claim 3, wherein the bank (1103) includes a light absorbing material ([0081]). Allowable Subject Matter Claims 2, 9-16 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHANAEL R BRIGGS whose telephone number is (571)272-8992. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth can be reached at (571)-272-9791. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATHANAEL R BRIGGS/Primary Examiner, Art Unit 2871 9/24/2026
Read full office action

Prosecution Timeline

Dec 05, 2024
Application Filed
Sep 28, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
88%
With Interview (+11.3%)
2y 7m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1102 resolved cases by this examiner. Grant probability derived from career allowance rate.

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