DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/05/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to for the following reasons:
The reference number “235” in Fig. 2 crosses with an arrow line, which is not in compliance with 37 CFR 1.84(p)(3)
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the partitioned storage areas for each row of each of the memory banks described in claim 3, 10, and 19 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Examiner notes that while Figs. 2 and 3 show separate rows in the memory banks for transmission paths of memory data, PIM data, and instruction, claims 3, 10, and 19 indicate that each row is partitioned into separate storage areas, which is not shown in the drawings.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“control logic configured to generate a selection signal” in claims 1 and 8
“receiving, by control logic of the PIM device, a memory command” in claim 15
“generating, by the control logic, a selection signal” in claim 15
“executing, by the control logic, the memory command” in claim 15
“control logic that generates the selection signal” in claim 22
Since the specification does not disclose the specific structure of the control logic for performing the associated functions, a 112(a) and 112(b) rejection appears below.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Objections
Claims 4 and 11 are objected to because of the following informalities:
Claim 4 line 3- “the memory data in each of the memory banks” should be “the data in each of the memory banks” to be consistent with claims 1, which describes that the memory banks store data, not “memory” data.
similar clarifications should be made for “the memory data” in claim 11 line 3
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the selection circuit” in lines 7-8. It is unclear which selection circuit this refers to as line 2 introduces a selection circuit in each of the PEs. For purposes of examination this will be interpreted as a selection circuit in any one of the PEs.
Claim 1 recites “the path to a memory bank” in line 8. There is insufficient antecedent basis for this limitation as the claim does not previously describe a path to a memory bank. For purposes of examination this will be interpreted as any path to a memory bank.
Claim 1 recites “the memory bank” in line 9. It is unclear where this refers to the memory bank introduced in line 8 or a different one of the memory banks introduced in line 6. For purposes of examination this will be interpreted as referring to the memory bank introduced in line 6. Examiner suggests adding a descriptor to the memory bank introduced in line 8 and references to it, i.e., a/the first memory bank, to clarify this issue.
Claim 2 recites “the selection circuit” in line 1. It is unclear which selection circuit this refers to as claim 1 line 2 introduces a selection circuit in each of the PEs. For purposes of examination this will be interpreted as a selection circuit in any one of the PEs.
Claim 2 recites “the path through which data of an activated row is to be fetched…” in line 2. There is insufficient antecedent basis for this limitation as the claim does not previously describe a path through which data of an activated row is to be fetched. For purposes of examination this will be interpreted as any path through which data of an activated row is to be fetched.
Claim 3 recites “for each row of each of the memory banks” in line 1. There is insufficient antecedent basis for this limitation as the claim does not introduce each memory bank as having rows. For purposes of examination, this will be interpreted as each memory bank having rows.
Claim 3 recites “for each row of each of the memory banks, a storage area corresponding to the memory data, a storage area corresponding to the PIM data, and a storage area corresponding to the instruction for the internal processor are partitioned off from each other.” However, Figs. 2 and 3 shows separate rows in the memory banks for transmission paths of memory data, PIM data, and instruction. Thus, while this limitation may be clear on its face, it is unclear when read in view of the disclosure. For purposes of examination, this limitation will be interpreted as the storage areas being separate from each other.
Claim 8 recites “the path to the memory bank” in line 11. There is insufficient antecedent basis for this limitation as the claim does not previously describe a path to a memory bank. For purposes of examination this will be interpreted as any path to a memory bank.
Claim 8 recites “the selection circuit” in lines 10-11. It is unclear which selection circuit this refers to as lines 6-7 introduces a selection circuit in each of the PEs. For purposes of examination this will be interpreted as a selection circuit in any one of the PEs.
Claim 8 recites “the memory bank” in line 11. It is unclear where this refers to the memory bank introduced in line 4 or a different one of the memory banks introduced in line 3. For purposes of examination this will be interpreted as referring to the memory bank introduced in line 4. Examiner suggests adding a descriptor to the memory bank introduced in line 4 and references to it, i.e., a/the first memory bank, to clarify this issue.
Claim 9 recites “the selection circuit” in line 1. It is unclear which selection circuit this refers to as claim 8 lines 6-7 introduces a selection circuit in each of the PEs. For purposes of examination this will be interpreted as a selection circuit in any one of the PEs.
Claim 9 recites “the path through which data of an activated row is to be fetched…” in line 2. There is insufficient antecedent basis for this limitation as the claim does not previously describe a path through which data of an activated row is to be fetched. For purposes of examination this will be interpreted as any path through which data of an activated row is to be fetched.
Claim 10 recites “for each row of each of the memory banks” in line 1. There is insufficient antecedent basis for this limitation as the claim does not introduce each memory bank as having rows. For purposes of examination, this will be interpreted as each memory bank having rows.
Claim 10 recites “for each row of each of the memory banks, a storage area corresponding to the memory data, a storage area corresponding to the PIM data, and a storage area corresponding to the instruction for the internal processor are partitioned off from each other.” However, Figs. 2 and 3 shows separate rows in the memory banks for transmission paths of memory data, PIM data, and instruction. Thus, while this limitation may be clear on its face, it is unclear when read in view of the disclosure. For purposes of examination, this limitation will be interpreted as the storage areas having separate rows from each other.
Claim 11 recites “the memory bank” in line 3. It is unclear where this refers to the memory bank introduced in claim 8 line 4 or a different one of the memory banks introduced in claim 8 line 3. For purposes of examination this will be interpreted as referring to the memory bank introduced in claim 8 line 4. Examiner suggests adding a descriptor to the memory bank introduced in claim 8 line 4 and references to it, i.e., a/the first memory bank, to clarify this issue.
Claim 18 recites “the memory bank” in line 3. It is unclear where this refers to the memory bank introduced in claim 15 line 9 or a different one of the memory banks introduced in claim 15 lines 9-10. For purposes of examination this will be interpreted as referring to the memory bank introduced in claim 15 line 9. Examiner suggests adding a descriptor to the memory bank introduced in claim 15 line 9 and references to it, i.e., a/the first memory bank, to clarify this issue.
Claim 19 recites “for each row of each of the memory banks” in line 1. There is insufficient antecedent basis for this limitation as the claim does not introduce each memory bank as having rows. For purposes of examination, this will be interpreted as each memory bank having rows.
Claim 19 recites “for each row of each of the memory banks, a storage area corresponding to the memory data, a storage area corresponding to the PIM data, and a storage area corresponding to the instruction for the internal processor are partitioned off from each other.” However, Figs. 2 and 3 shows separate rows in the memory banks for transmission paths of memory data, PIM data, and instruction. Thus, while this limitation may be clear on its face, it is unclear when read in view of the disclosure. For purposes of examination, this limitation will be interpreted as the storage areas having separate rows from each other.
Claim 20 recites “the memory bank” in line 2 and line 3. It is unclear where this refers to the memory bank introduced in claim 15 line 9 or a different one of the memory banks introduced in claim 15 lines 9-10. For purposes of examination this will be interpreted as referring to the memory bank introduced in claim 15 line 9. Examiner suggests adding a descriptor to the memory bank introduced in claim 15 line 9 and references to it, i.e., a/the first memory bank, to clarify this issue.
The following limitations in the claims invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
“control logic configured to generate a selection signal” in claims 1 and 8
“receiving, by control logic of the PIM device, a memory command” in claim 15
“generating, by the control logic, a selection signal” in claim 15
“executing, by the control logic, the memory command” in claim 15
“control logic that generates the selection signal” in claim 22
However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification does not disclose the specific structure of the control logic for generating a selection signal (claims 1, 8, 15, and 22), or the specific structure of the control logic for receiving and executing a memory command (claim 15). Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims dependent on a rejected base claim are further rejected based on their dependence.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 and 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The following limitations in the claim invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
“control logic configured to generate a selection signal” in claims 1 and 8
“receiving, by control logic of the PIM device, a memory command” in claim 15
“generating, by the control logic, a selection signal” in claim 15
“executing, by the control logic, the memory command” in claim 15
“control logic that generates the selection signal” in claim 22
Since these limitations invoke 112(f), the specification is required to disclose the specific structure of the control logic for performing these functions. However, the specification does not disclose the specific structure of the control logic for generating a selection signal (claims 1, 8, 15, and 22), or the specific structure of the control logic for receiving and executing a memory command (claim 15). Therefore, these claims are rejected under 112(a).
Claims dependent on a rejected base claim are further rejected based on their dependence.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over a first embodiment of Lee US 2020/0293319 in view of a second embodiment of Lee.
Regarding claim 1, Lee, in a first embodiment, teaches:
1. A processing-in-memory (PIM) device comprising:
processing elements (PEs) (Fig. 1, processing elements 221),
memory banks configured to store data corresponding to the PEs ([0043]: each of the processing elements corresponds to one bank, i.e., the banks store data corresponding to the PEs);
a command decoder configured to decode a memory command for the memory bank and control logic ([0031]: the command decoder 231 decodes a command/address (for bank in which data access is to be performed) from the memory controller (i.e., a memory command) to generate a decoding result and control logic performs an operation in accordance with the decoding result (i.e., the memory command is decoded for control logic).
The first embodiment of Lee does not teach:
wherein each of the PEs comprises a selection circuit configured to select a path from among a transmission path of memory data, a transmission path of PIM data for a multiply-accumulate (MAC) operation, and a transmission path of an instruction for an internal processor;
a control logic configured to generate a selection signal configured to cause the selection circuit to select the path to a memory bank among the memory banks;
However, a second embodiment of Lee teaches:
a selection circuit configured to select a path from among a transmission path of memory data, a transmission path of PIM data for a multiply-accumulate (MAC) operation, and a transmission path of an instruction for an internal processor ([0109]-[0111]: the route selector 823 (i.e., a selection circuit) may select a path/route from among route a, which provides data from the bank to the host (i.e., a transmission path of memory data), route b, which provides data from the bank to the PIM circuit (i.e., a transmission path of PIM data, which can be for a MAC operation as the PIM circuit supports multiplication and addition operations (i.e., the transmission path for the multiplication and addition operations would be capable of also transmitting data for the intended use of a MAC operation), see [0074]), and route f, which provides an operation processing result (of an operation/instruction processed by/for the internal processor of the PIM) from the PIM circuit to the host (i.e., a transmission path of an instruction for an internal processor));
a control logic configured to generate a selection signal configured to cause the selection circuit to select the path to a memory bank among the memory banks ([0107] discloses that the route selector 823 may be controlled based on operation of a processing controller/control logic, any signal generated by the processing controller to control the route selector to select a path to the memory bank is a selection signal, see also Fig. 12 showing the route selector 823 selecting routes/paths to the memory bank 821);
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the PEs of the first embodiment of Lee to include the selection circuit and control logic of the second embodiment of Lee. One of ordinary skill in the art would have been motivated to make this modification to efficiently connect the memory banks and their corresponding PEs and the host (as opposed to having dedicated paths/ports for each connection), which would reduce overhead and improve flexibility.
Regarding claim 2, the first embodiment of Lee in view of the second embodiment of Lee teaches:
2. The PIM device of claim 1, wherein the selection circuit is configured to:
determine the path through which data of an activated row is to be fetched from each of the memory banks according to the selection signal ([0109]: in the combination, the selection circuit of a processing element may select route a (from the memory bank to the host) or route b (from the memory bank to the PIM), which determines the path through with data is fetched from each corresponding memory bank (according to a selection signal from a processing controller/control logic, see [0107])).
Regarding claim 3, the first embodiment of Lee in view of the second embodiment of Lee teaches:
3. The PIM device of claim 1, wherein, for each row of each of the memory banks, a storage area corresponding to the memory data, a storage area corresponding to the PIM data, and a storage area corresponding to the instruction for the internal processor are partitioned off from each other ([0109] discloses that data (i.e., the memory data) may be provided from the bank to the host through route a when the command/address corresponds to a read request the bank and that data (i.e., PIM data) may be provided from the bank to the PIM circuit when the command/address corresponds to an operation processing request, which indicates that the memory data and PIM data are stored at separate addresses (i.e., the storage areas are partitioned off from each other); further the instructions are stored in instruction memory 224, which is partitioned off/separate from the storage area storing the memory data and PIM data in the memory banks, see [0046] and Fig. 2).
Regarding claim 4, the first embodiment of Lee in view of the second embodiment of Lee teaches:
4. The PIM device of claim 1, wherein the control logic comprises:
a register configured to store row information of at least one of a PIM area for a PIM operation or a storage area of the memory data in each of the memory banks according to the memory command ([0090] and Fig. 9: address register 623 provides information to the row decoder 612 in each of the memory banks, which indicates that the address register stores row information of a storage area of the memory data in each of the memory banks, according to the memory command CMD/ADD; the address register and the selection signal generation logic of the combination are collectively control logic).
Regarding claim 5, the first embodiment of Lee in view of the second embodiment of Lee teaches:
5. The PIM device of claim 1, wherein each of the PEs comprises at least one of:
the internal processor ([0035] discloses that the processing elements may be processors, which indicates that each PE comprises an internal processor);
a MAC operation circuit configured to perform the MAC operation; or
an instruction memory configured to store the instruction for the internal processor (this limitation is not required under BRI).
Regarding claim 6, the first embodiment of Lee in view of the second embodiment of Lee teaches:
6. The PIM device of claim 5, wherein the instruction memory comprises:
a register configured to store at least one of the memory command or the instruction for the internal processor, for reuse of the memory command or decoding of the instruction for the internal processor (this limitation is not required under BRI since it follows from there being an instruction memory, which is not required under BRI).
Regarding claim 8, Lee teaches:
8. A processing-in-memory (PIM) device comprising:
processing elements (PEs) (Fig. 1, processing elements 221);
memory banks configured to store data corresponding to the PEs ([0043]: each of the processing elements corresponds to one bank, i.e., the banks store data corresponding to the PEs); and
a command decoder configured to decode a memory command for a memory bank among the memory banks ([0031]: the command decoder 231 decodes a command/address (for bank in which data access is to be performed) from the memory controller (i.e., a memory command) to generate a decoding result),
The first embodiment of Lee does not teach:
wherein each of the PEs comprises:
a selection circuit configured to select a path from among a transmission path of memory data, a transmission path of PIM data for a multiply-accumulate (MAC) operation, and a transmission path of an instruction for an internal processor; and
control logic configured to generate a selection signal configured to cause the selection circuit to select the path to the memory bank.
However, a second embodiment of Lee teaches:
a selection circuit configured to select a path from among a transmission path of memory data, a transmission path of PIM data for a multiply-accumulate (MAC) operation, and a transmission path of an instruction for an internal processor ([0109]-[0111]: the route selector 823 (i.e., a selection circuit) may select a path/route from among route a, which provides data from the bank to the host (i.e., a transmission path of memory data), route b, which provides data from the bank to the PIM circuit (i.e., a transmission path of PIM data, which can be for a MAC operation as the PIM circuit supports multiplication and addition operations, see [0074]), and route f, which provides an operation processing result (of an operation/instruction processed by/for the internal processor of the PIM) from the PIM circuit to the host (i.e., a transmission path of an instruction for an internal processor)); and
control logic configured to generate a selection signal configured to cause the selection circuit to select the path to the memory bank ([0107] discloses that the route selector 823 may be controlled based on operation of a processing controller/control logic, any signal generated by the processing controller to control the route selector to select a path to the memory bank is a selection signal, see also Fig. 12 showing the route selector 823 selecting routes/paths to the memory bank 821).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the PEs of the first embodiment of Lee to include the selection circuit and control logic of the second embodiment of Lee. One of ordinary skill in the art would have been motivated to make this modification to efficiently connect the memory banks and their corresponding PEs and the host (as opposed to having dedicated paths/ports for each connection), which would reduce overhead and improve flexibility.
Regarding claim 9, the first embodiment of Lee in view of the second embodiment of Lee teaches:
9. The PIM device of claim 8, wherein the selection circuit is configured to:
determine the path through which data of an activated row is to be fetched from the memory bank, in response to the selection signal ([0109]: in the combination, the selection circuit of a processing element may select route a (from the memory bank to the host) or route b (from the memory bank to the PIM), which determines the path through with data is fetched from each corresponding memory bank (according to a selection signal from a processing controller/control logic, see [0107])).
Regarding claim 10, the first embodiment of Lee in view of the second embodiment of Lee teaches:
10. The PIM device of claim 8, wherein, for each row of each of the memory banks, a storage area corresponding to the memory data, a storage area corresponding to the PIM data, and a storage area corresponding to the instruction for the internal processor are partitioned off from each other ([0109] discloses that data (i.e., the memory data) may be provided from the bank to the host through route a when the command/address corresponds to a read request the bank and that data (i.e., PIM data) may be provided from the bank to the PIM circuit when the command/address corresponds to an operation processing request, which indicates that the memory data and PIM data are stored at separate addresses (i.e., the storage areas are partitioned off from each other); further the instructions are stored in instruction memory 224, which is partitioned off/separate from the storage area storing the memory data and PIM data in the memory banks, see [0046] and Fig. 2).
Regarding claim 11, the first embodiment of Lee in view of the second embodiment of Lee teaches:
11. The PIM device of claim 8, wherein the control logic comprises:
a register configured to store row information of at least one of a PIM area for a PIM operation or a storage area of the memory data in the memory bank, in response to the memory command ([0090] and Fig. 9: address register 623 provides information to the row decoder 612 in each of the memory banks, which indicates that the address register stores row information of a storage area of the memory data in each of the memory banks, according to the memory command CMD/ADD; the address register and the selection signal generation logic of the combination are collectively control logic).
Regarding claim 12, the first embodiment of Lee in view of the second embodiment of Lee teaches:
12. The PIM device of claim 8, wherein each of the PEs comprises:
the internal processor ([0035] discloses that the processing elements may be processors, which indicates that each PE comprises an internal processor);
a MAC operation circuit configured to perform the MAC operation; or
an instruction memory configured to store the instruction for the internal processor (this limitation is not required under BRI).
Regarding claim 13, the first embodiment of Lee in view of the second embodiment of Lee teaches:
13. The PIM device of claim 12, wherein the instruction memory comprises:
a register configured to store at least one of the memory command or the instruction for the internal processor, for reuse of the memory command or decoding of the instruction for the internal processor (this limitation is not required under BRI since it follows from there being an instruction memory, which is not required under BRI).
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over a first embodiment of Lee US 2020/0293319 in view of a second embodiment of Lee and Cadambi US 2011/0119467.
Regarding claim 7, the first embodiment of Lee in view of the second embodiment of Lee teaches
7. The PIM device of claim 1, wherein an instruction memory is configured to store a PIM binary comprising at least one of a set of instructions or a plurality of memory commands, which are written by a host device and executed in the PIM device ([0046 and [0052]: instruction memory 224 stores a set of instructions provided by the host an executed by the PEs of the PIM device, the set of instructions stored in the instruction memory is a PIM binary).
Lee does not teach:
wherein each of the memory banks is configured to store a PIM binary comprising at least one of a set of instructions or a plurality of memory commands, which are written by a host device and executed in the PIM device.
However, Cadambi teaches a separate instruction memory bank for each core (analogous to the processing elements of Lee) that is written by a host, see [0036].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory banks of Lee to store instructions for each corresponding PE as suggested by Cadambi. One of ordinary skill in the art would have been motivated to make this modification to improve storage efficiency since storing instructions in the memory banks would be more efficient than requiring a separate instruction memory for the instructions.
Regarding claim 14, the first embodiment of Lee in view of the second embodiment of Lee teaches:
14. The PIM device of claim 8, wherein an instruction memory is configured to store a PIM binary comprising at least one of a set of instructions or a plurality of memory commands, which are written by a host device and executed in the PIM device ([0046 and [0052]: instruction memory 224 stores a set of instructions provided by the host an executed by the PEs of the PIM device, the set of instructions stored in the instruction memory is a PIM binary).
Lee does not teach:
wherein each of the memory banks is configured to store a PIM binary comprising at least one of a set of instructions or a plurality of memory commands, which are written by a host device and executed in the PIM device.
However, Cadambi teaches a separate instruction memory bank for each core (analogous to the processing elements of Lee) that is written by a host, see [0036].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory banks of Lee to store instructions for each corresponding PE as suggested by Cadambi. One of ordinary skill in the art would have been motivated to make this modification to improve storage efficiency since storing instructions in the memory banks would be more efficient than requiring a separate instruction memory for the instructions.
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lee US 2020/0293319, Cadambi US 2011/0119467, and Sumbul US 2020/0034148
Regarding claim 21, Lee teaches:
21. A processing-in-memory (PIM) device comprising:
a memory bank comprising a first region for storing memory data, a second region for storing PIM data ([0109] discloses that the bank 821 may provide data (i.e., memory data) to the host through route a and may provide data to the PIM through route b, the region of the bank that stores the data provided through route a is a first region and the region that stores the data provided through route b is a second region);
an internal processor (Fig. 12 PIM circuit 822);
a selection circuit connecting one of i) the first region to a first path to enable a host device to access the memory data ([0109] describes the route selector switching state to provide data read from the bank to the host through route a, which includes connecting the region of the bank storing the memory data to route a to enable the host to access the data), ii) the second region to a second path to enable the logic circuit to perform the MAC operation on the PIM data, and iii) the third region to a third path to enable the internal processor to execute the instruction, in response to receipt of a selection signal ([0107] discloses that the route selector 823 may be controlled based on operation of a processing controller/control logic, any signal generated by the processing controller to control the route selector to select a path to the memory bank is a selection signal, see also Fig. 12 showing the route selector 823 selecting routes/paths to the memory bank 821).
Lee does not teach:
the memory bank comprising a third region storing an instruction;
a logic circuit configured to perform a multiply-accumulate (MAC) operation;
However, Cadambi teaches storing instructions in an instruction memory bank for each core (analogous to the processing elements of Lee), see [0036].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory banks of Lee to store instructions as suggested by Cadambi such that the combination would include a third region of a memory bank storing an instruction. One of ordinary skill in the art would have been motivated to make this modification to improve storage efficiency since storing instructions in the memory banks would be more efficient than requiring a separate instruction memory for the instructions.
The combination of Lee and Cadambi does not teach:
a logic circuit configured to perform a multiply-accumulate (MAC) operation;
However, Sumbul teaches MAC units capable of performing dot product/MAC operations, see [0026].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify PIM device of Lee to include a MAC unit as taught by Sumbul. One of ordinary skill in the art would have been motivated to make this modification to enable performing MAC operations, which would improve the number of operations supported by the device.
Regarding claim 22, Lee in view of Cadambi and Sumbul teaches:
22. The PIM device of claim 21, further comprising control logic that generates the selection signal in response to receipt of a read command or a write command (Lee [0107] discloses that the route selector 823 may be controlled based on operation of a processing controller/control logic, any signal generated by the processing controller to control the route selector to select a path to the memory bank is a selection signal, see also [0109] describing that the data from the bank may be provided to the host on route a when the command corresponds to a reading request (i.e., in response to receipt of a read command)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee US 2020/0293319.
Regarding claim 15, Lee teaches:
15. An operating method of a processing-in-memory (PIM) device (Fig. 1, 200), the method comprising:
receiving, by control logic of the PIM device, a memory command from a host device when the host device executes a host program (since this limitation is contingent on the host device executing a host program, it is a contingent limitation that is not required under BRI of a method claim, see MPEP 2111.04 (II));
generating, by the control logic, a selection signal for a path to at least one processing element (PE) according to a row address of the memory command (this limitation is not required under BRI since it follows from there being a memory command, which is not required under BRI);
opening, by a selection circuit of the PIM device, the path among a transmission path of memory data, a transmission path of PIM data for a multiply-accumulate (MAC) operation, and a transmission path of an instruction for an internal processor to a memory bank among a plurality memory banks according to the selection signal (this limitation is not required under BRI since it follows from there being a selection signal, which is not required under BRI); and
executing, by the control logic, the memory command by fetching data through the opened path (this limitation is not required under BRI since it follows from there being a memory command, which is not required under BRI).
Regarding claim 16, Lee teaches:
16. The method of claim 15, wherein the generating of the selection signal for the path to the at least one PE (this limitation is not required under BRI since generating the selection signal follows from there being a memory command, which is not required under BRI) comprises:
transmitting a data address of an operand for executing the memory command to a command decoder; and
transmitting, by the command decoder, the row address of the memory command corresponding to the data address of the operand to the control logic by parsing the memory command.
Regarding claim 17, Lee teaches:
17. The method of claim 15, wherein, when the control logic is present outside the at least one PE (since this limitation is contingent on the control logic being present outside the at least one PE, it is a contingent limitation that is not required under BRI of a method claim, see MPEP 2111.04 (II); further, this limitation follows from there being at least one PE, which is not required under BRI), the opening of the path comprises:
opening, by the selection circuit, the path in each of the memory banks according to the selection signal.
Regarding claim 18, Lee teaches:
18. The method of claim 15, wherein, when the control logic is present in each of the at least one PE (since this limitation is contingent on the control logic being present in each of the at least one PE, it is a contingent limitation that is not required under BRI of a method claim, see MPEP 2111.04 (II); further, this limitation follows from there being at least one PE, which is not required under BRI), the opening of the path comprises:
opening, by the selection circuit, the path in the memory bank, in response to receiving the selection signal.
Regarding claim 19, Lee teaches:
19. The method of claim 15, wherein, for each row of the memory banks, a storage area corresponding to the memory data, a storage area corresponding to the PIM data, and a storage area corresponding to the instruction for the internal processor are partitioned off from each other (this limitation is not required under BRI since it follows from there being memory banks, which is not required under BRI).
Regarding claim 20, Lee teaches:
20. The method of claim 15, further comprising:
writing, by the host device, a PIM binary into the memory bank of the PIM device (this limitation is not required under BRI since it follows from there being the memory bank, which is not required under BRI); and
writing, by the host device, row information of the memory bank into the control logic of the PIM device (this limitation is not required under BRI since it follows from there being the memory bank, which is not required under BRI).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2013/0046955 teaches computation elements in a register file directly connected to subarrays of the register file, see Abstract and Fig. 2
US 2023/0025068 teaches transferring data between at least one of a plurality of CIM PEs and at least one of a plurality of NPU PEs via a bus, see Abstract
US 2024/0143541 teaches a CIM module that stores weights of a matrix and performs a vector-matrix multiply, see Abstract
US 2012/0124248 teaches a common bus interconnecting different processing units and a main memory or cache, see [0012] and Fig. 1
US 2024/0403053 teaches a processing-in-memory device comprising a memory bank for receiving a request from a memory controller, a PIM engine for processing a PIM instruction, and a PIM control unit that identifies the PIM instruction corresponding to the request, see Abstract
US 2023/0393849 teaches offloading tasks to a PIM device including an agent configured to receive a request from a host processor, determine at least one PIM command and memory page associated with the host processor, and issue the PIM command to the PIM device for execution, see Abstract
US 2024/0103763 teaches receiving a first and second stream of commands which cause a processing in memory component to perform operations that access a first and second bank respectively.
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/KASIM ALLI/Examiner, Art Unit 2183 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
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