DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rathore et al. US Patent Application Publication No. 2023/0367507 (herein after referred to as Rathore).
Regarding claim 1, Rathore describes a control device configured to control an information storage device (Controller 220 and Flash Memory 230 of Flash Storage Device 210. Fig. 2. Controller 220 includes any electronic circuits and/or optical circuits that are able to perform functions. For example, controller 220 may perform any function described herein that is attributed to flash storage device 210. In this regard, controller 220 comprises any system, component, or device that is able to control the operations of flash storage device 210… (page 4, paragraph [0038])) that is configured to store a plurality of bits of information in one cell (The defined storage capacity is based on the type of flash cells in the blocks (e.g., single level cell (SLC), multi-level cell (MLC), triple level cell (TLC) or quad level cell (QLC) along with the number of blocks per die and the number of des used in the flash storage device (page 1, paragraph [0001]). …blocks 238, 239 are selectable between multi-bit mode (e.g., MLC, TLC, QLC) and a single-bit mode (e.g., SLC mode) for storing data blocks (page 4, paragraph [0042])), the control device comprising an execution unit (Processor 221. Fig. 2. Processor 221 includes any electronic circuits and/or optical circuits that are able to perform functions. For example, processor 221 may perform any functionality described herein for controller 220… (page 4, paragraph [0038])) configured to switch the information storage device to a second mode (During operation, controller 220 may identify one or more triggers 224, described in more detail below, which directs controller 220 to convert or switch one or more of blocks 238, 239 from multi-bit mode to single-bit mode (page 4, paragraph [0043])), on condition that a count of times that information has been stored in the information storage device is more than a predetermined count of times, when the information storage device is in a first mode (In another example, method 400 further includes determining that a number of P/E cycles of the one or more blocks is greater than a threshold number of P/E cycles based, at least in part, on determining the trigger event has occurred. For instance, controller 220 may track P/E cycles for one or more blocks 238, 239, and triggers 224 may include a threshold number of P/E cycles which directs controller 220, when the number of tracked P/E cycles exceeds a threshold number of P/E cycles, to switch one or more of blocks 238, 239 from multi-bit mode to single-bit mode (page 6, paragraph [0059])), wherein: the first mode is a mode in which multiple bits of information are stored in one cell; and the second mode is a mode in which one bit of information is stored in one cell (The defined storage capacity is based on the type of flash cells in the blocks (e.g., single level cell (SLC), multi-level cell (MLC), triple level cell (TLC) or quad level cell (QLC) along with the number of blocks per die and the number of des used in the flash storage device (page 1, paragraph [0001]). …switch one or more of blocks 238, 239 from multi-bit mode to single-bit mode (page 6, paragraph [0059])). Rathore does not specifically state that a count of times that information is storable in the information storage device is smaller than a predetermined count of times.
Rathore discloses that the flash cells have an endurance (e.g., the number of program/erase (P/E) cycles) of the flash cells that depend on the type of flash cells in the blocks (page 1, paragraph [0001]). The endurance of the flash cells in SLC mode is significantly higher (e.g., >100,000 program/erase (P/E) cycles) as compared to the endurance of the flash cells in their native multi-bit mode. For example, QLC flash cells may have an endurance of only about 1,000 P/E cycles. However, even after 1,000 P/E cycles, switching QLC flash blocks to SLC mode may still enable at least another 90,000 P/E cycles (page 1, paragraph [0005]). Rathore also mentions that the trigger event may be based on a number of P/E cycles for the blocks in flash memory of the flash storage device (page 2, paragraph [0022]). The endurance of a flash memory may be looked at in two ways that are mathematically equivalent. The total number of P/E cycles executed and the number of P/E cycles remaining. Therefore, while Rathore specifically discloses that the trigger condition may occur when the number of P/E cycles exceeds a threshold, it is also mathematically equivalent to describe that trigger as the number of remaining P/E cycles falling below a threshold [count of times that information is storable in the information storage device is smaller than a predetermined count of times].
Regarding claim 7, Rathore describes the control device according to claim 1 (see above), wherein: the information storage device includes a plurality of regions for storing information; and the execution unit is configured to switch storage modes of the regions individually (The defined storage capacity is based on the type of flash cells in the blocks (e.g., single level cell (SLC), multi-level cell (MLC), triple level cell (TLC) or quad level cell (QLC) along with the number of blocks per die and the number of des used in the flash storage device (page 1, paragraph [0001]). Generally, in flash architectures, a block represents the smallest unit that may be erased in a single erase operation, and a flash page may represent the smallest unit that may be programmed (i.e., written to) or read in a single write or read operation. Each flash page may include thousands or tens of thousands of bits, with each bit implemented by a flash memory cell. Some flash devices support dynamically switching a flash block from multi-bit mode to SLC mode (also referred to herein as single-bit mode), which reduces the storage capability for the flash pages in the block, but increases the endurance and performance of the memory cells in the block (page 2, paragraph [0018]). …until a trigger event is identified that directs the flash storage device to convert one or more of its flash blocks from multi-bit mode to SLC mode… (page 2, paragraph [0022])).
Regarding claim 11, Rathore describes a control method for controlling an information storage device (Controller 220 and Flash Memory 230 of Flash Storage Device 210. Fig. 2. Controller 220 includes any electronic circuits and/or optical circuits that are able to perform functions. For example, controller 220 may perform any function described herein that is attributed to flash storage device 210. In this regard, controller 220 comprises any system, component, or device that is able to control the operations of flash storage device 210… (page 4, paragraph [0038])) that is configured to store a plurality of bits of information in one cell (The defined storage capacity is based on the type of flash cells in the blocks (e.g., single level cell (SLC), multi-level cell (MLC), triple level cell (TLC) or quad level cell (QLC) along with the number of blocks per die and the number of des used in the flash storage device (page 1, paragraph [0001]). …blocks 238, 239 are selectable between multi-bit mode (e.g., MLC, TLC, QLC) and a single-bit mode (e.g., SLC mode) for storing data blocks (page 4, paragraph [0042])), the control method being executed by a computer (In this example, system 200 includes a host 202 (e.g., a computer system, a mobile phone) that issues I/O commands to flash storage device 210 (page 4, paragraph [0037]). …For example, controller 220 may perform any function described herein that is attributed to flash storage device 210 (page 4, paragraph [0038]). …processor 221 may perform any functionality described herein for controller 220 (page 4, paragraph [0038])) and comprising switching the information storage device to a second mode (During operation, controller 220 may identify one or more triggers 224, described in more detail below, which directs controller 220 to convert or switch one or more of blocks 238, 239 from multi-bit mode to single-bit mode (page 4, paragraph [0043])) on condition that a count of times that information has been stored in the information storage device is more than a predetermined count of times, when the information storage device is in a first mode (In another example, method 400 further includes determining that a number of P/E cycles of the one or more blocks is greater than a threshold number of P/E cycles based, at least in part, on determining the trigger event has occurred. For instance, controller 220 may track P/E cycles for one or more blocks 238, 239, and triggers 224 may include a threshold number of P/E cycles which directs controller 220, when the number of tracked P/E cycles exceeds a threshold number of P/E cycles, to switch one or more of blocks 238, 239 from multi-bit mode to single-bit mode (page 6, paragraph [0059])), wherein: the first mode is a mode in which multiple bits of information are stored in one cell; and the second mode is a mode in which one bit of information is stored in one cell (The defined storage capacity is based on the type of flash cells in the blocks (e.g., single level cell (SLC), multi-level cell (MLC), triple level cell (TLC) or quad level cell (QLC) along with the number of blocks per die and the number of des used in the flash storage device (page 1, paragraph [0001]). …switch one or more of blocks 238, 239 from multi-bit mode to single-bit mode (page 6, paragraph [0059])). Rathore does not specifically state that a count of times that information is storable in the information storage device is smaller than a predetermined count of times.
Rathore discloses that the flash cells have an endurance (e.g., the number of program/erase (P/E) cycles) of the flash cells that depend on the type of flash cells in the blocks (page 1, paragraph [0001]). The endurance of the flash cells in SLC mode is significantly higher (e.g., >100,000 program/erase (P/E) cycles) as compared to the endurance of the flash cells in their native multi-bit mode. For example, QLC flash cells may have an endurance of only about 1,000 P/E cycles. However, even after 1,000 P/E cycles, switching QLC flash blocks to SLC mode may still enable at least another 90,000 P/E cycles (page 1, paragraph [0005]). Rathore also mentions that the trigger event may be based on a number of P/E cycles for the blocks in flash memory of the flash storage device (page 2, paragraph [0022]). The endurance of a flash memory may be looked at in two ways that are mathematically equivalent. The total number of P/E cycles executed and the number of P/E cycles remaining. Therefore, while Rathore specifically discloses that the trigger condition may occur when the number of P/E cycles exceeds a threshold, it is also mathematically equivalent to describe that trigger as the number of remaining P/E cycles falling below a threshold [count of times that information is storable in the information storage device is smaller than a predetermined count of times].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Rathore in view of Kurita et al. US Patent Application Publication No. 2021/0405900 (herein after referred to as Kurita).
Regarding claim 2, Rathore describes the control device according to claim 1 (see above), wherein the execution unit is configured to switch the information storage device to the second mode, on condition that the count of times that information is storable in the information storage device is smaller than the predetermined count of times (In another example, method 400 further includes determining that a number of P/E cycles of the one or more blocks is greater than a threshold number of P/E cycles based, at least in part, on determining the trigger event has occurred. For instance, controller 220 may track P/E cycles for one or more blocks 238, 239, and triggers 224 may include a threshold number of P/E cycles which directs controller 220, when the number of tracked P/E cycles exceeds a threshold number of P/E cycles, to switch one or more of blocks 238, 239 from multi-bit mode to single-bit mode (page 6, paragraph [0059]). Also in view of threshold reasoning above), when the information storage device is in the first mode. Rathore does not specifically disclose the conditions include also a remaining capacity of the information storage device that is available is no smaller than a predetermined capacity.
Kurita describes a storage device with a controller configured to select a first write mode to write n-bit data and another mode in response to received instructions. Specifically, Fig. 6 shows that in response to a SLC write enable command the controller determines whether free block pool includes sufficient number of free blocks (S128 of Fig. 6). A sufficient number of free blocks would clearly anticipate “remaining capacity of the information storage device that is available is no smaller than a predetermined capacity”.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Kurita teachings in the Rathore system. Skilled artisan would have been motivated to incorporate the method of determining sufficient available free blocks as taught by Kurita in the Rathore system for effectively ensuring that there is enough capacity to write data in a less dense format. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as Flash Storage devices with MLC/SLC modes. This close relation between both of the references highly suggests an expectation of success.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Rathore in view of Kanno US Patent Application Publication No. 2019/0004964 (herein after referred to as Kanno).
Regarding claim 8, Rathore describes an information processing device comprising: an information storage device configured to store a plurality of bits of information in one cell (Flash Memory 230 of Flash Storage Device 210. Fig. 2. The defined storage capacity is based on the type of flash cells in the blocks (e.g., single level cell (SLC), multi-level cell (MLC), triple level cell (TLC) or quad level cell (QLC) along with the number of blocks per die and the number of des used in the flash storage device (page 1, paragraph [0001]). …blocks 238, 239 are selectable between multi-bit mode (e.g., MLC, TLC, QLC) and a single-bit mode (e.g., SLC mode) for storing data blocks (page 4, paragraph [0042])); and a control device configured to control the information storage device (Controller 220 of Flash Storage Device 210. Fig. 2. Controller 220 includes any electronic circuits and/or optical circuits that are able to perform functions. For example, controller 220 may perform any function described herein that is attributed to flash storage device 210. In this regard, controller 220 comprises any system, component, or device that is able to control the operations of flash storage device 210… (page 4, paragraph [0038])), wherein: the control device includes an execution unit and a storage unit (Processor 221. Fig. 2. Processor 221 includes any electronic circuits and/or optical circuits that are able to perform functions. For example, processor 221 may perform any functionality described herein for controller 220… (page 4, paragraph [0038]). Flash Memory 230 of Flash Storage Device 210. Fig. 2); the execution unit is configured to switch a storage mode of the information storage device to a second mode (During operation, controller 220 may identify one or more triggers 224, described in more detail below, which directs controller 220 to convert or switch one or more of blocks 238, 239 from multi-bit mode to single-bit mode (page 4, paragraph [0043])), on condition that a count of times that information is storable in the information storage device is more than a predetermined count of times, when the information storage device is in a first mode (In another example, method 400 further includes determining that a number of P/E cycles of the one or more blocks is greater than a threshold number of P/E cycles based, at least in part, on determining the trigger event has occurred. For instance, controller 220 may track P/E cycles for one or more blocks 238, 239, and triggers 224 may include a threshold number of P/E cycles which directs controller 220, when the number of tracked P/E cycles exceeds a threshold number of P/E cycles, to switch one or more of blocks 238, 239 from multi-bit mode to single-bit mode (page 6, paragraph [0059])); the first mode is a mode in which multiple bits of information are stored in one cell; and the second mode is a mode in which one bit of information is stored in one cell (The defined storage capacity is based on the type of flash cells in the blocks (e.g., single level cell (SLC), multi-level cell (MLC), triple level cell (TLC) or quad level cell (QLC) along with the number of blocks per die and the number of des used in the flash storage device (page 1, paragraph [0001]). …switch one or more of blocks 238, 239 from multi-bit mode to single-bit mode (page 6, paragraph [0059])). Rathore does not specifically state that a count of times that information is storable in the information storage device is smaller than a predetermined count of times. Furthermore, Rathore does not specifically disclose the storage unit is configured to store an operating system and an application that runs on the operating system; store information in the information storage device in conjunction with execution of the application running on the operating system, nor when the storage mode of the information storage device is a first mode at a time of updating the operating system
Rathore discloses that the flash cells have an endurance (e.g., the number of program/erase (P/E) cycles) of the flash cells that depend on the type of flash cells in the blocks (page 1, paragraph [0001]). The endurance of the flash cells in SLC mode is significantly higher (e.g., >100,000 program/erase (P/E) cycles) as compared to the endurance of the flash cells in their native multi-bit mode. For example, QLC flash cells may have an endurance of only about 1,000 P/E cycles. However, even after 1,000 P/E cycles, switching QLC flash blocks to SLC mode may still enable at least another 90,000 P/E cycles (page 1, paragraph [0005]). Rathore also mentions that the trigger event may be based on a number of P/E cycles for the blocks in flash memory of the flash storage device (page 2, paragraph [0022]). The endurance of a flash memory may be looked at in two ways that are mathematically equivalent. The total number of P/E cycles executed and the number of P/E cycles remaining. Therefore, while Rathore specifically discloses that the trigger condition may occur when the number of P/E cycles exceeds a threshold, it is also mathematically equivalent to describe that trigger as the number of remaining P/E cycles falling below a threshold [count of times that information is storable in the information storage device is smaller than a predetermined count of times].
Kanno describes a memory system for controlling nonvolatile memory. Specifically, the SSD 3 writes original data, for example, virtual machine image A (the binary image of OS #1 and the binary images of APLs #1 to #3), to region #1. In this case, the install images of the operating system (OS) #1 and application programs (APLs) #1 to #3 may be copied from a disk to region #1. Alternatively, the operation for installing operating system (OS) #1 and application programs (APLs) #1 to #3 into region #1 may be performed (page 6, paragraph [0124]). While virtual machine MV2 is in an operating state, the server 100 (virtual machine VM2) transmits a large number of write requests (write commands) each specifying an LBA in region #32 to the SSD 3 to, for example, newly write user data, rewrite the user data or update operating system (OS) #1 (page 8, paragraph [0142]). When the SSD 3 comprises a built-in MLC/TLC-NAND flash memory in which each memory cell is capable of storing data of a plurality of bits, each MLC/TLC block allocated to region #1 from the MLC/TLC-NAND flash memory may be set to an SLC mode, and each MLC/TLC block allocated to region #31 (or region #32) from the MLC/TLC-NAND flash memory may be set to an MLC/TLC mode. Regarding the MLC/TLC blocks set to an SLC mode, the SSD 3 writes data (here, the binary image of an operating system, etc.,) to the MLC/TLC blocks in a first write mode for writing data of 1 bit per memory cell. In other words, the SSD 3 writes data to region #1, using the first write mode for writing data of 1 bit per memory cell. For example, in the first write mode, only lower page data may be written to the group of memory cells connected to the same word line. Regarding the MLC/TLC blocks set to an MLC/TLC mode, the SSD 3 writes data to the MLC/TLC blocks in a second write mode for writing data of a plurality of bits per memory cell. In other words, the SSD 3 writes data to region #31 or region #32, using the second write mode for writing data of a plurality of bits per memory cell. For example, in the second write mode, lower page data and upper page data may be written to the group of memory cells connected to the same word line (MLC mode). Further, lower page data, middle page data and upper page data may be written to the group of memory cells connected to the same word line (TLC mode) (page 10, paragraphs [0179] – [0181]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Kanno teachings in the Rathore system. Skilled artisan would have been motivated to incorporate the method of storing an operating system and application programs in MLC/SLC capable storage for effectively providing reconfigurable storage on which to store conventional computer data and programs. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as Flash Storage devices with MLC/SLC modes. This close relation between both of the references highly suggests an expectation of success.
Allowable Subject Matter
Claims 3 – 6 and 9 – 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 3 describes, “The control device according to claim 2, wherein the execution unit is configured to delete predetermined information stored in the information storage device, on condition that the count of times that information is storable in the information storage device is smaller than the predetermined count of times and also the remaining capacity of the information storage device that is available is smaller than the predetermined capacity, when the information storage device is in the first mode.” Claim 5 describes, “The control device according to claim 2, wherein the execution unit is configured to output, to an output device, first information indicating a request to delete information stored in the information storage device, on condition that the count of times that information is storable in the information storage device is smaller than the predetermined count of times and also the remaining capacity of the information storage device that is available is smaller than the predetermined capacity, when the information storage device is in the first mode.” Claim 9 describes, “The information processing device according to claim 8, wherein: the information processing device is installed in a vehicle; the operating system is a first operating system, and a region of the information processing device that stores information in conjunction with execution of a first application running on the first operating system is a first region; the first application is a program that performs control different from traveling control of the vehicle; and the execution unit is configured to switch the first region to the second mode, on condition that a count of times that information is storable in the first region of the information storage device is smaller than a predetermined count of times, when the first region is in the first mode at a time of updating the first operating system.” Samuels et al. US Patent Application Publication No. 2016/0062663 describes that in accordance with a detected amelioration trigger, perform an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, including: deleting from the storage device discardable data that is used by a host and reducing declared capacity of the non-volatile memory of the storage device. However, Samuels does not specifically disclose “deleting predetermined information stored in the information storage device, on condition that the count of times that information is storable in the information storage device is smaller than the predetermined count of times and also the remaining capacity of the information storage device that is available is smaller than the predetermined capacity, when the information storage device is in the first mode” nor “outputting a request to delete information stored in the information storage device, on condition that the count of times that information is storable in the information storage device is smaller than the predetermined count of times and also the remaining capacity of the information storage device that is available is smaller than the predetermined capacity, when the information storage device is in the first mode.” Bert US Patent Application Publication No. 2022/0300174 describes the storage system can be managed by code executed as part of a kernel, a device driver, an application, other portion of a host operating system, or a combination thereof. However, Bert does not specifically describe “wherein: the information processing device is installed in a vehicle; the operating system is a first operating system, and a region of the information processing device that stores information in conjunction with execution of a first application running on the first operating system is a first region; the first application is a program that performs control different from traveling control of the vehicle; and the execution unit is configured to switch the first region to the second mode, on condition that a count of times that information is storable in the first region of the information storage device is smaller than a predetermined count of times, when the first region is in the first mode at a time of updating the first operating system.” Cerafogli et al. US Patent Application Publication No. 2023/0367496 describes updating a first storage state (e.g., an MLC storage state) to a second storage state (e.g., an SLC storage state), which may allow a memory system to repurpose blocks nearing their end of life which may increase the sustainability of the memory system. However, Cerafogli does not specifically teach or suggest all of the limitations presented in the identified claims. He et al. US Patent No. 11556479 describes that a cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio of the block. However, He does not specifically teach or suggest all of the limitations presented in the identified claims. Kankani et al. US Patent Application Publication No. 2016/0342344 describes that in some embodiments, a trigger condition is detected by comparing a wear metric such as P/E cycle counts to a previously determined value, e.g., a threshold value. However, Kankani does not specifically teach or suggest all of the limitations presented in the identified claims.
Conclusion
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/RALPH A VERDERAMO III/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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March 21, 2026
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