Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Raffo et al. US publication no.: US 2025/0309754 A1 in view of Zhang et al. US publication no.: US 2015/0372678 A1.
Regarding claim 1, Raffo et al. teach, A gate driver circuit (gate driver system 200, figure 2a) comprising: a high-side sensor (comparator 236, diode; threshold input Vth1; ,figure 2a; paragraph 99, where the inverter output is compared to a voltage threshold Vth1 indicates that the voltage of the inverter is determined and compared to a threshold) that asserts a high-side detection signal when a potential difference between two nodes of a high-side transistor (high transistor 206, figure 2A) constituting an inverter circuit (See figure 2a, paragraphs 51-52) crosses a first threshold level; a high-side driver configured to be capable of supplying a high voltage or a low voltage between a gate and a source of the high-side transistor and have a controllable driving capability (see high side gate driver 212 and logic unit 214; figure 2a; paragraph 55); and a control circuit (logic unit 214, figure 2a) that causes the high-side driver to generate the high voltage when a control signal instructs turning-on of the high-side transistor, and changes the driving capability of the high-side driver in response to an assertion of the high-side detection signal (see figure 2f; paragraph 104 and 89, where it is explained that the switching of the transistors is dependent upon the signal from the comparator),
Raffo et al. teach a system in which the abnormality is determined based on a comparison of the voltage with a threshold and a corresponding control is performed but is silent on specifcifically teaching: wherein the control circuit determines that abnormality has occurred when the assertion of the high-side detection signal does not occur within a first predetermined time.
However, Zhang et al. is in the same field of art and teach: wherein the control circuit determines that abnormality has occurred when the assertion of the high-side detection signal does not occur within a first predetermined time (see paragraphs 22 and 32; figure 4, step 420; where it is explained that an “ON” signal is initiated but the results of the comparison is “masked” and it goes on for a predetermined time util the end of “miler plateau” where at step 450 the action is taken)
Essentially, Zhang et al. teach a similar function of a waiting period prior to determining an abnormality and one could’ve easily configured and achieve the results the claim requires with the teaching of Zhang et al. as presented in figure 1-4.
Therefore, in view of Zhang et a.’s teachings, it would’ve been obvious to one with the ordinary skills in the art, before the effective filing date of the invention, with the apparatus as taught by Raffo et al. to include; wherein the control circuit determines that abnormality has occurred when the assertion of the high-side detection signal does not occur within a first predetermined time, for the purpose of enhancing safety measures.
Regarding claim 2, Raffo et al. teach, the gate driver circuit of claim 1, wherein the high-side sensor monitors a drain-source voltage of the high-side transistor (see figure 2a and 2f where the comparator configured to receive measurement value of the phase-node voltage VDES_H).
Regarding claim 4, The gate driver circuit of claim 1, wherein the first predetermined time is longer than a turn-on time of the high-side transistor in a normal state.
Zhang et al. teach in paragraphs 22 and 32; figure 4, step 420; where it is explained that an “ON” signal is initiated but the results of the comparison is “masked” and it goes on for a predetermined time util the end of “miler plateau” where at step 450 the action is taken but is silent on specifically teaching: wherein the first predetermined time is longer than a turn-on time of the high-side transistor in a normal state.
However, selecting the time to be long longer than a turn-on time of the high-side transistor in a normal state could’ve been easily configured by one with the ordinary skills the art to achieve the desired results.
Therefore, in view of Zhang et a.’s teachings, it would’ve been obvious to one with the ordinary skills in the art, before the effective filing date of the invention, with the apparatus as taught by Raffo et al. to include; selecting the time to be long longer than a turn-on time of the high-side transistor in a normal state could’ve been easily configured by one with the ordinary skills the art to achieve the desired results, for the purpose of enhancing safety measures.
Regarding claim 6, The gate driver circuit of claim 1, further comprising: a low-side sensor that asserts a low-side detection signal when a potential difference between two nodes of a low-side transistor constituting the inverter circuit crosses a second threshold level(comparator 238, diode; threshold input Vth2; ,figure 2a; paragraph 99, where the inverter output is compared to a voltage threshold Vth1 indicates that the voltage of the inverter is determined and compared to a threshold);
and a low-side driver(see low side gate driver 210 and logic unit 214; figure 2a; paragraph 55); configured to be capable of supplying a high voltage or a low voltage between a gate and a source of the low-side transistor and have a controllable driving capability, wherein the control circuit (logic unit 214, figure 2a) causes the low-side driver to generate the high voltage when the control signal instructs turning-on of the low-side transistor, and changes the driving capability of the low-side driver in response to an assertion of the low-side detection signal (see figure 2f; paragraph 104 and 89, where it is explained that the switching of the transistors is dependent upon the signal from the comparator).
Raffo et al. is silent on specifically teaching: wherein the control circuit determines that abnormality has occurred when the assertion of the low-side detection signal does not occur within a second predetermined time
However, Zhang et al. is in the same field of art and teach wherein the control circuit determines that abnormality has occurred when the assertion of the low-side detection signal does not occur within a second predetermined time (see paragraphs 22 and 32; figure 4, step 420; where it is explained that an “ON” signal is initiated but the results of the comparison is “masked” and it goes on for a predetermined time util the end of “miler plateau” where at step 450 the action is taken)
Essentially, Zhang et al. teach a similar function of a waiting period prior to determining an abnormality and one could’ve easily configured and achieve the results the claim requires with the teaching of Zhang et al. as presented in figure 1-4.
Therefore, in view of Zhang et a.’s teachings, it would’ve been obvious to one with the ordinary skills in the art, before the effective filing date of the invention, with the apparatus as taught by Raffo et al. to include; wherein the control circuit determines that abnormality has occurred when the assertion of the low-side detection signal does not occur within a second predetermined time , for the purpose of enhancing safety measures.
Regarding claim 8, Raffo et al. teach, the gate driver circuit of claim 1, which is integrally integrated on a single semiconductor substrate (see paragraph 41).
Regarding claim 9, Raffo et al. teach, A motor drive device comprising: an inverter circuit including a high-side transistor and a low-side transistor; and the gate driver circuit of claim 1, which drives the high-side transistor and the low-side transistor (see figure 1 and 2a and rejection of claim 1 above; where a motor drive system is disclosed which includes an inverter with low and high-side drive system).
Regarding claim 10, Raffo et al. teach, An electronic apparatus comprising: a motor; and the motor drive device of claim 9, which drives the motor (see figure 1 and 2a and rejection of claim 1 above).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liao et al. US publication no.: US 2022/0239224 A1.
Regarding claim 3, Raffo et al. as modified is silent on specifically teaching, the gate driver circuit of claim 1, wherein the high-side sensor monitors a gate-source voltage of the high-side transistor.
Liao et al. teach: wherein the high-side sensor monitors a gate-source voltage of the high-side transistor (see claim 1).
Therefore, in view of Liao et al. teachings, it would’ve been obvious to one with the ordinary skills in the art, before the effective filing date of the invention, with the apparatus as taught by Raffo et al. as modfied to include; wherein the high-side sensor monitors a gate-source voltage of the high-side transistor, for the purpose of enhancing safety measures.
Allowable Subject Matter
Claims 5 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ZOHEB S IMTIAZ/Primary Examiner , Art Unit 2837
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