DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The application has not been checked to the extent necessary to determine the presence of all possible typographical and grammatical errors. Applicant’s cooperation is requested in correcting any errors of which he/she may become aware in the application.
The Information Disclosure Statements filed 12/05/2024 has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 24, 26 and 29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 24 recites on line 3 the limitation “the sub DACs””. This term is not clear because only one sub DAC has been mentioned in independent claim 16. Clarification and correction are required.
Claim 26 recites on line 1 the limitation “the circuits”. The term “the circuits” is not clear because there is no prior mention of any circuit in independent claim 16. Clarification and correction are required.
Claim 29 recites on lines 1-2 the limitation “wherein at first the coarse delay is set to come…”. The term “at first” is not clear because there is no sequence mentioned or suggested. Clarification and correction are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-17, 23, 25, 27, 29 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s provided prior art of figure (1) in view of Kahmen (EP-4336683 A1).
Regarding claim 16, Applicant’s provided prior art in figure (1) teaches a continuous-time analog-to-digital converter circuit, comprising: an input to which an analog input signal Vin (t) can be applied; an analog delay element (10a) being interconnected between the input and a first summation node (20); an ADC-DAC path (11a-12a) interconnected between the input and the first summation node (20), the ADC-DAC path configured to digitize the analog input signal through ADC (11a) and to reconvert the digitized analog input signal back to analog through DAC (12a) and to subtract the reconverted signal at the first summation node (20), the ADC-DAC path comprising: a switch (S1) interconnected between the input (1) and a sub ADC (11a), the switch configured to sample the analog input with a specified sampling rate fs; a sub DAC (12a) interconnected between the sub ADC (11a) and the first summation node (20), wherein delays of the analog delay element and the ADC-DAC path are matched by means of a delay control element, wherein an output at the first summation node (20) is filtered by a filter element (30), wherein an output of the filter element (30) is sampled by the specified sampling rate (fs); and a backend ADC (41) connected to a second summation node (42) and configured to digitize the sampled output of the filter element (30); wherein the ADC-DAC path is operative to match its delay to the delay of the analog delay element.
The prior art of figure (1) does not specifically suggest matching the ADC-DAC delay to the delay element. However, this limitation is inherent because delay matching is necessary in an analog-to-digital converter having multiple delay elements, to prevent time misalignment errors.
Applicant’s provided prior art of figure (1) does not specifically teach a delay control element to control delay matching. However, as evidenced by Kahmen, the use of a delay control element for delay matching is well-known in the art (See abstract). Kahmen teaches a delay control component to control multiple delays in a circuit (See abstract). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kahmen into the converter system of Applicant’s provided prior art to realize a new system having improved performance and reliability because this would substantially increase the number of available coarse-delay amount options (See paragraph [0023]).
Regarding claim 27, Applicant’s provided prior art in figure (1) teaches a continuous-time analog-to-digital converter circuit, comprising: an input to which an analog input signal Vin (t) can be applied; an analog delay element (10a) being interconnected between the input and a first summation node (20); an ADC-DAC path (11a-12a) interconnected between the input and the first summation node (20), the ADC-DAC path configured to digitize the analog input signal through ADC (11a) and to reconvert the digitized analog input signal back to analog through DAC (12a) and to subtract the reconverted signal at the first summation node (20), the ADC-DAC path comprising: a switch (S1) interconnected between the input (1) and a sub ADC (11a), the switch configured to sample the analog input with a specified sampling rate fs; a sub DAC (12a) interconnected between the sub ADC (11a) and the first summation node (20), wherein delays of the analog delay element and the ADC-DAC path are matched by means of a delay control element, wherein an output at the first summation node (20) is filtered by a filter element (30), wherein an output of the filter element (30) is sampled by the specified sampling rate (fs); and a backend ADC (41) connected to a second summation node (42) and configured to digitize the sampled output of the filter element (30); wherein the ADC-DAC path is operative to match its delay to the delay of the analog delay element. The prior art of figure (1) does not specifically suggest matching the ADC-DAC path delay to the delay element. However, this limitation is inherent because delay matching is necessary in an analog-to-digital converter having multiple delay elements, to prevent time misalignment errors.
Applicant’s provided prior art of figure (1) does not specifically teach a delay control element to control delay matching, wherein the delay of the ADC-DAC path is controlled by means of a coarse delay control and a fine delay control. However, as evidenced by Kahmen, the use of a delay control element for delay matching is well-known in the art (See abstract). Kahmen teaches a delay control component to control multiple delays in a circuit (See abstract), wherein the delay is controlled by means of a coarse delay control and a fine delay control (See abstract). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kahmen into the converter system of Applicant’s provided prior art to realize a new system having improved performance and reliability because this would substantially increase the number of available coarse-delay amount options (See paragraph [0023]).
Regarding claims 17 and 25, Applicant’s provided prior art in figure (1) in com bination with Kahmen teaches a continuous-time analog-to-digital converter circuit (See paragraph [0018] of Applicant’s specification) wherein delay is controlled by means of a coarse delay control and a fine delay control (See abstract of Kahmen).
Regarding claim 23, Applicant’s provided prior art in figure (1) in com bination with Kahmen teaches a continuous-time analog-to-digital converter circuit wherein the fine delay control is implemented by means of a delay control logic of the delay control device, the delay control logic being inherent in the delay control device as it is needed to operate the control device.
Regarding claims 29 and 31, Applicant’s provided prior art in figure (1) in combination with Kahmen teaches a method for calibrating a continuous-time analog-to-digital converter circuit wherein the coarse delay can set to come as close as possible to the delay of the analog delay element because the coarse delay includes a plurality of selectable coarse-group delay amounts including a group-delay amount of zero (See paragraph [0008]. The combination does not specifically teach storing data with respect to the matching procedure. However, this limitation is obvious because the step of storing data for further processing in an analog-to-digital converter is well-known.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 28 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Applicant’s provided prior art of figure (1).
Regarding claim 28, Applicant’s provided prior art in figure (1) teaches a method for calibrating a continuous-time analog-to-digital converter circuit, comprising: applying an analog input signal Vin (t) to an input; digitizing the analog input signal through ADC (11a) and reconverting the digitized analog input signal back to analog through DAC (12a) and subtract the reconverted signal at a first summation node (20); sampling the analog input with a specified sampling rate (fs); filtering an output at the first summation node by a filter element (30) and sampling of an output of the filter element by the specified sampling rate (fs); digitizing the sampled output of the filter element through back-end ADC (41). The prior art of figure (1) does not specifically suggest matching the ADC-DAC delay to the delay of the delay element. However, this limitation is inherent because delay matching is necessary in an analog-to-digital converter having multiple delay elements, to prevent time misalignment errors.
Allowable Subject Matter
Claims 18-22 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH J LAUTURE whose telephone number is (571)272-1805. The examiner can normally be reached 9:30 AM-6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at 5712722105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSEPH J LAUTURE/Primary Examiner, Art Unit 2845
Prosecution Insights