Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
This Office action is in response to Applicant's communication filed March 31, 2026 in response to the Office action dated January 7,2026.
Claims 1, 8, and 15 have been amended. Claims 1-20 are pending in this application.
NOTE:
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art reference and any interpretations of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3-9, 11-16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Horspool et. al. U.S. Patent Pub No. 2025/0110888 (hereinafter Horspool) in view of Volpe et. al. US Patent No. 10,733,110 (hereinafter Volpe).
Regarding Claim 1, Horspool teaches a memory sub-system comprising: a memory device(Fig.1, Para14-16); an ultra-high endurance storage(Fig.1, Para15-17 "The SSD 100 includes, for example, a controller 120 and a flash memory 180 as non-volatile memory (e.g., a NAND type flash memory"); and a processing device, operatively coupled with the memory device and the ultra-high endurance storage (Fig.1; Para15-17), to perform operations comprising: identifying a power loss event associated with the memory sub-system (Fig.2, 5; Para4-5 "The controller may be configured to detem1ine whether a power failure occurs" Para46-47,50-55); in response to the power loss event, identifying a set of data corresponding to one or more in-flight operations associated with the memory device (Fig.2, 5; Para4-5; 30-32, 34-35 "in response to determining that the power failure occurs, remaining in-flight write data can be transferred from the write buffer to NANO buffers ( e.g., first buffer, second buffer) in parallel with a flush operation of other NANO buffers" Para46, Para50-55);
causing the set of data corresponding to the one or more in-flight operations to be stored in the ultra-high endurance storage class memory device (Fig.2, 5; Para34-35 “"in response to determining that the power failure occurs, remaining in-flight write data can be transferred from the write buffer to NANO buffers ( e.g., first buffer, second buffer) in parallel with a flush operation of other NANO buffers" Para46-47 "The pSLC mode is significantly faster to program the data than other modes (e.g., MLC, TLC, or QLC mode), thereby reducing the energy used to store the host in-flight data in the NAND array 380" Para,50-55).
However, Horspool fails to teach but Volpe teaches storage class memory device; and causing execution of a data recovery operation using the set of data corresponding to the one or more in-flight operations to be stored in the ultra-high endurance storage class memory device (Fig.1,2; C3L35-65 "In a case where the data is lost in the DRAM device due to power failure or power off, the data stored in the DRAM can be restored back based on the copy of the data stored in the SCM device, when the power is back on").
Horspool and Volpe are analogous art because they are from the same field of endeavor. They both relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Horspool, and incorporating the SCM, as taught by Volpe.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize more efficient approach of data management, as suggested by Vole (C3L12-60).
Regarding claim 2, the combination of Horspool and Volpe teaches all the limitations of the base claims as outlined above.
Further, Horspool teaches the operations further comprising: following the power loss event, determining that a condition is satisfied; and in response to determining that the condition is satisfied, terminating a writing of at least a portion of the set of data from the ultra-high endurance storage class memory device to the memory device(Fig.2, 5; Para4-5; 30-32, 34-35,50-55 ).
Regarding claim 4, the combination of Horspool and Volpe teaches all the limitations of the base claims as outlined above.
Further, Horspool teaches wherein prior to the power loss event, the set of data corresponding to the one or more in-flight operations is written to the ultra-high endurance storage class memory device and the memory device concurrently(Fig.2, 5; Para4-5; 30-32, 34-35,50-55 ).
Regarding claim 5, the combination of Horspool and Volpe teaches all the limitations of the base claims as outlined above.
Further, Horspool teaches the operations further comprising, in response to the power loss event, terminating a writing of at least a portion of the set of data corresponding to the one or more in-flight operations to the memory device(Fig.2, 5; Para4-5; 30-32, 34-35,50-55 ).
Regarding claim 6, the combination of Horspool and Volpe teaches all the limitations of the base claims as outlined above.
Further, Horspool teaches wherein prior to the power loss event, the set of data corresponding to the one or more in-flight operations is written to the memory device(Fig.2, 5; Para4-5; 30-32, 34-35,50-55 ).
Regarding claim 7, the combination of Horspool and Volpe teaches all the limitations of the base claims as outlined above.
Further, Horspool teaches the operations further comprising, in response to the power loss event: terminating a first writing of at least a portion of the set of data corresponding to the one or more in-flight operations to the memory device; and initiating a second writing of the at least the portion of the set of data corresponding to the one or more in-flight operations to the ultra-high endurance storage class memory device(Fig.2, 5; Para4-5; 30-32, 34-35,50-55).
Regarding claims 8,9, 11-14, 15, 16, 18-20, the combination of Horspool and Volpe teaches these claims according to the reasoning set forth in claim 1, 2, 4-7.
Allowable Subject Matter
Claims 3, 10, and 17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record, including the reference(s) cited below, neither anticipates, nor renders obvious the recited combination as a whole; including at least the limitations of : “wherein the condition is satisfied if a programming time associated with programming the at least the portion of the set of data is greater than a threshold programming time.”
Response to Arguments
Applicants arguments, see page 7-9, filed March 31, 2026, with respect to claims 1, 8, and 15 have been fully considered and they are not persuasive.
Applicant argued Horspool fails to teach “causing the set of data corresponding to the one or more in-flight operations to be stored in the ultra-high endurance storage class memory device.” The Examiner respectfully disagrees. Horspool teaches transferring, i.e. storing the inflight data from write buffer to NAND array after a power failure event (Fig.2, 5; Para22-23;34-35 ;Para46-47; Para,50-55 “in response to determining that the power failure occurs, the controller may configure the device to program data stored in at least one of the first data buffer (e.g., P-buffer 384) or the second data buffer (e.g., A-buffer 386) to the NVM in a second mode (e.g., pSLC mode)” NVM e.g. the NAND memory corresponds to ultra-high endurance storage). The claim does not further define ultra-high endurance storage and does not state in-flight data is stored in ultra-high endurance storage before the power loss event.
Volpe further teaches causing execution of a data recovery operation using the set of data corresponding to the one or more in-flight operations to be stored in the ultra-high endurance storage class memory device (Fig.1,2; C3L35-65 "In a case where the data is lost in the DRAM device due to power failure or power off, the data stored in the DRAM can be restored back based on the copy of the data stored in the SCM device, when the power is back on").
Therefore, the combination of Horspool and Volpe renders these claims unpatentable.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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TASNIMA . MATIN
Primary Examiner
Art Unit 2135
/TASNIMA MATIN/Primary Examiner, Art Unit 2135
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