Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 10, 11, and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishioka (US 10,930,363 B1). Nishioka teaches A test circuit, comprising: a plurality of conductive paths (Fig. 1, 32); a test control circuit configured to sequentially receive serially input test control signals in response to a test clock signal, and generate and output a plurality of test enable signals in one-to-one correspondence with the plurality of conductive paths, wherein each of the plurality of test enable signals indicates whether a corresponding one of the plurality of conductive paths performs defect detection as a target conductive path in each defect detection (Column 4, lines 34-67); a power control circuit electrically connected to each of the plurality of conductive paths and the test control circuit, separately, and configured to control, when the test enable signal is in a valid state, a corresponding conductive path as the target conductive path to sequentially perform charging and discharging operations (Column 7 lines 12-48); and a defect detection circuit electrically connected to a first end of each of the plurality of conductive paths and the test control circuit, separately, and configured to detect level changes of the plurality of conductive paths separately to generate a plurality of detection identification signals in one-to-one correspondence with the plurality of conductive paths (Column 7 lines 49-67)and generate and output a plurality of detection results in one-to-one correspondence with the plurality of conductive paths based on one-to-one comparison results between the plurality of detection identification signals and the plurality of test enable signals (Column 8 lines 1-14).
With reference to claim 2, Nishioka further teaches the test control circuit is further configured to regenerate and output a plurality of test enable signals after shift-transmitting the test control signals based on the test clock signal after each defect detection is completed; wherein the test control circuit is further configured to serially output the plurality of detection results output by the defect detection circuit as test result signals in sequence based on the test clock signal after all the plurality of conductive paths serve as target conductive paths to complete defect detection (Column 8, lines 1-14).
With reference to claim 3, Nishioka further teaches the test control circuit is further configured to receive a result readout identification signal, read all the plurality of detection results output by the defect detection circuit based on the test clock signal when the result readout identification signal indicates that the test control circuit is in a test result readout phase, and serially output the read plurality of detection results as the test result signals in sequence based on the test clock signal when the result readout identification signal indicates that the test control circuit is in a data transmission phase; wherein the test control circuit is further configured to reset the plurality of test enable signals in response to a first reset signal after all the plurality of detection results are output (Column 7 lines 12-48).
With reference to claim 4, Nishioka further teaches the test control circuit comprises a plurality of test control sub-circuits cascaded, the plurality of test control sub-circuits being in one-to-one correspondence with the plurality of conductive paths; and a first input end of a test control sub-circuit of a first stage receives the test control signals, an output end of a test control sub-circuit of each stage is electrically connected to a first input end of a control sub-circuit of a next stage, a second input end of the test control sub-circuit of each stage receives a corresponding one of the plurality of detection results, a clock end of the test control sub-circuit of each stage receives the test clock signal, a control end of the test control sub-circuit of each stage receives the result readout identification signal, a reset end of the test control sub-circuit of each stage receives the first reset signal, an output end of the test control sub-circuit of each stage outputs a corresponding one of the plurality of test enable signals or a corresponding one of the plurality of detection results, and an output end of a test control sub-circuit of a last stage is further configured to serially output the plurality of detection results as the test result signals in sequence (Column 3 lines 9-31). With reference to claim 5, Nishioka further teaches each of the plurality of test control sub-circuits comprises: a selector, wherein a first input end of the selector serves as the first input end of the test control sub-circuit, a second input end of the selector serves as the second input end of the test control sub-circuit to receive the corresponding one of the plurality of detection results, and a control end of the selector serves as the control end of the test control sub-circuit to receive the readout identification signal; and a first D flip-flop, wherein an input end of the first D flip-flop is electrically connected to an output end of the selector, a clock end of the first D flip-flop serves as the control end of the test control sub-circuit to receive the test clock signal, an output end of the first D flip-flop serves as the output end of the test control sub-circuit to output the plurality of test enable signals, and a reset end of the first D flip-flop receives the first reset signal (Fig. 5, Column 4 line 46-Column 5 line 2).
With reference to claim 6, Nishioka further teaches the defect detection circuit is further configured to receive a detection result latch signal and latch each of the plurality of detection results in response to the detection result latch signal after each defect detection is completed; wherein the defect detection circuit is further configured to latch, based on a current comparison result between each detection identification signal and a corresponding test enable signal, each of the plurality of detection results kept or updated in response to the received detection result latch signal after any of the plurality of conductive paths sequentially performs the charging and discharging operations as the target conductive path, wherein when the detection identification signal is different from the corresponding test enable signal, the corresponding detection result is kept or updated to be a first level, and when the detection identification signal is the same as the corresponding test enable signal, the corresponding detection result is kept unchanged; and the detection result being the first level indicates that the corresponding conductive path has a defect, and the detection result being a second level indicates that the corresponding conductive path has no defect, wherein the first level is opposite to the second level (Column 7, line 49-67, Column 8 lines 15-32).
With reference to claim 10, Nishioka further teaches the power control circuit comprises: a first power control circuit electrically connected to the first end of each of the plurality of conductive paths and the test control circuit, separately, and configured to control a first end of the target conductive path to be electrically connected to the power supply voltage or a grounding voltage when the test enable signal is in the valid state; and a second power control circuit electrically connected to a second end of each of the plurality of conductive paths, separately, and configured to control the second end of the conductive path to be electrically connected to the grounding voltage or the power supply voltage (Figs. 6 and 7, Column 7 lines 40-47). With reference to claim 11, Nishioka further teaches the plurality of conductive paths are divided into a plurality of conductive path groups arranged in arrays, each of the plurality of conductive path groups comprises l×m conductive paths arranged in an array, and l and m are both positive integers greater than or equal to 2; and controlling, in response to each of the plurality of test enable signals in the valid state, the corresponding one of the plurality of conductive paths as the target conductive path to perform defect detection comprises: using one conductive path in each of the plurality of conductive path groups as the target conductive path in response to the plurality of test enable signals, and controlling the first end of each of the target conductive paths to be electrically connected to the power supply voltage to perform the charging operation; and controlling a second end of a selected conductive path to be electrically connected to the grounding voltage in response to a test region selection signal to perform the discharging operation, wherein the test region selection signal comprises a plurality of test region selection sub-signals in one-to-one correspondence with a plurality of position regions, each of the plurality of test region selection sub-signals indicates whether conductive paths in a corresponding one of the plurality of position regions are selected; and each of the plurality of position regions comprises at least one conductive path group (Fig. 5, Column 7 line 12-48).
With reference to claim 16, Nishioka further teaches a clock shielding circuit connected to the test control circuit and configured to receive an initial clock signal, generate and output the test clock signal based on the initial clock signal when none of the plurality of conductive paths performs defect detection, and output no test clock signal when any of the plurality of conductive paths performs defect detection (Column 5 lines 38-54).
With reference to claim 17, Nishioka teaches A test method for a stacked chip structure, comprising: sequentially receiving serially input test control signals in response to a test clock signal, and generating and outputting a plurality of test enable signals in one-to-one correspondence with a plurality of conductive paths (Column 4, lines 34-67); controlling, in response to each of the plurality of test enable signals in a valid state, a corresponding one of the plurality of conductive paths as a target conductive path to perform defect detection (Column 5 lines 38-47); detecting level changes of the plurality of conductive paths, separately, during each defect detection to generate a plurality of detection identification signals in one-to-one correspondence with the plurality of conductive paths (Column 7 lines 12-48); generating a plurality of detection results in one-to-one correspondence with the plurality of conductive paths based on comparison results between the plurality of detection identification signals and the corresponding plurality of test enable signals (Column 7 lines 49-67); and latching the plurality of detection results in response to a detection result latch signal after each defect detection is completed (Column 8 lines 1-14).
With reference to claim 18, Nishioka further teaches serially outputting the plurality of detection results latched by a defect detection circuit as test result signals in sequence based on the test clock signal after all the plurality of conductive paths serve as the target conductive paths to complete defect detection or after each round of defect test is completed; wherein serially outputting the plurality of detection results latched as the test result signals in sequence based on the test clock signal after all the plurality of conductive paths serve as the target conductive paths to complete defect detection or after each round of defect test is completed comprises: after all the plurality of conductive paths serve as the target conductive paths to complete defect detection, reading all the latched plurality of detection results in response to the test clock signal when a result readout identification signal indicates a test result readout phase, and serially outputting the read plurality of detection results as the test result signals in sequence in response to the test clock signal when the result readout identification signal indicates a data transmission phase (Column 3 lines 9-31).
With reference to claim 19, Nishioka further teaches latching the plurality of detection results in response to the detection result latch signal comprises: keeping or updating, based on a current comparison result between each detection identification signal and a corresponding test enable signal, each of the plurality of detection results in response to the received detection result latch signal after any of the plurality of conductive paths serves as the target conductive path to perform defect detection, wherein when the detection identification signal is different from the corresponding test enable signal, the corresponding detection result is kept or updated to be a high level, and when the detection identification signal is the same as the corresponding test enable signal, the corresponding detection result is kept unchanged; and the detection result being the high level indicates that the corresponding conductive path has a defect, and the detection result being a low level indicates that the corresponding conductive path has no defect; wherein controlling, in response to each of the plurality of test enable signals in the valid state, the corresponding one of the plurality of conductive paths as the target conductive path to sequentially perform defect detection comprises: controlling, in response to the test enable signal in the valid state, a first end of the target conductive path to be electrically connected to a power supply voltage to perform a charging operation; and controlling a second end of the target conductive path and a second end of a conductive path adjacent to the target conductive path to be electrically connected to a grounding voltage, separately, to perform a discharging operation after the charging operation is completed (Column 7, line 49-67, Column 8 lines 15-32).
With reference to claim 20, Nishioka further teaches the plurality of conductive paths are divided into a plurality of conductive path groups arranged in arrays, each of the plurality of conductive path groups comprises l×m conductive paths arranged in an array, and l and m are both positive integers greater than or equal to 2; and controlling, in response to each of the plurality of test enable signals in the valid state, the corresponding one of the plurality of conductive paths as the target conductive path to perform defect detection comprises: using one conductive path in each of the plurality of conductive path groups as the target conductive path in response to the plurality of test enable signals, and controlling the first end of each of the target conductive paths to be electrically connected to the power supply voltage to perform the charging operation; and controlling a second end of a selected conductive path to be electrically connected to the grounding voltage in response to a test region selection signal to perform the discharging operation, wherein the test region selection signal comprises a plurality of test region selection sub-signals in one-to-one correspondence with a plurality of position regions, each of the plurality of test region selection sub-signals indicates whether conductive paths in a corresponding one of the plurality of position regions are selected; and each of the plurality of position regions comprises at least one conductive path group (Fig. 5, Column 7 line 12-48).
Allowable Subject Matter
Claims 7-9 and 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose or suggest the claimed "defect detection circuit comprises a plurality of defect detection sub-circuits, the plurality of defect detection sub-circuits being in one-to-one correspondence with the plurality of conductive paths; and each of the plurality of defect detection sub-circuits comprises: a test signal detection sub-circuit electrically connected to a first end of a corresponding one of the plurality of conductive paths and configured to detect a level change of the conductive path to generate and output the detection identification signal; and a test result latch sub-circuit electrically connected to the test signal detection sub-circuit and the test control circuit and configured to generate the detection result based on the comparison result between the detection identification signal and the corresponding test enable signal, and latch the detection result in response to the detection result latch signal" in combination with the remaining claim elements as set forth in claims 7-9, 14 and 15.
The prior art does not disclose or suggest the claimed “the first power control circuit comprises a plurality of first power supply control sub-circuits, the second power control circuit comprises a plurality of second power supply control sub-circuits, and the plurality of first power supply control sub-circuits and the plurality of second power supply control sub-circuits are in one-to-one correspondence with the plurality of conductive paths, separately” in combination with the remaining claim elements as set forth in claims 12-13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al. (US 11,646,097 B2) teach a stacked memory device and test method thereof.
Chong et al. (US 11,054,461 B1) teach test circuits f or testing a die stack.
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/GREGORY H CURRAN/Primary Examiner, Art Unit 2852
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