Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 13-16 are nonelected. Claims 1-12 and 17-20 are currently under review.
Election/Restrictions
Applicant’s election without traverse of Species III (fig. 15) directed to claims 1-12 and 17-20 in the reply filed on November 17, 2025 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 5, 2024 is being considered by the examiner.
Claim Objections
Claim 4 is objected to because of the following informalities: typographic errors. Appropriate correction is required. The following is suggested:
Claim 4, line 4: “an electrode pattern configured to penetrate the first planarization layer and to be connected”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (Pub. No.: US 2017/0338295 A1) hereinafter referred to as Lee.
With respect to Claim 1, Lee discloses a display panel (fig. 1; ¶37), comprising: a substrate (figs. 1 & 14, item 101; ¶37); a driving element (fig. 5, T1; fig. 14, item D_TR; ¶72; ¶169) disposed on the substrate; a first switch element (fig. 14, item P_TR; ¶170) disposed on the substrate; a driving voltage wire (fig. 14, item 410a) electrically connected to the first switch element (¶177, “the power source wire 410 may be electrically connected to the first electrode 102d via the pixel transistor P_JR”); and a compensation electrode layer (fig. 14, item 410b) electrically connected to the driving voltage wire (¶173, “the power source wire 410 may have a double-layered structure which includes a first conductive layer 410a and a second conductive layer 410b electrically connected to the first conductive layer 410a… When the power source wire 410 is in a double-layered structure, resistance of the wire may be reduced. thereby preventing screen degradation caused by RC delay” – therefore item 410b is a compensation electrode layer), wherein the driving voltage wire and the compensation electrode layer are disposed in different layers (fig. 14, see item 410a and 410b).
With respect to Claim 2, claim 1 is incorporated, Lee discloses further comprising: a first planarization layer (fig. 14, item 105 functions as a first planarization layer) disposed on the driving element and the first switch element (¶170, “A second insulating layer 105 (for example, a first interlayer insulating layer) is between the gate electrode 102b and the source and drain electrodes 102c”; ¶172, “The second insulating layer 105 is between the gate electrode 110b and the source and drain electrode 110c” –item 105 is disposed the driving element and the first switch element since item 105 is disposed on the gate electrodes); and a second planarization layer (fig. 14, item 106 functions as a second planarization layer) disposed on the driving voltage wire (¶174, “The third insulating layer 106 is between the first conductive layer 410a and the second conductive layer 410b”), wherein the compensation electrode layer (fig. 14, item 410b: compensation electrode layer) is disposed on the second planarization layer.
With respect to Claim 3, claim 2 is incorporated, Lee discloses further comprising: a third planarization layer (fig. 14, item 107 functions as a third planarization layer; ¶170) disposed on the compensation electrode layer (fig. 14, item 107 is seen disposed on item 410b).
With respect to Claim 17, Lee discloses a display device (fig. 1, item 100: display device; ¶37), comprising: a display panel (fig. 1, item AA; ¶37); a data driver (fig. 1, item 130; ¶46) configured to drive the display panel; and a gate driver (fig. 1, item 110; ¶42) configured to drive the display panel, wherein the display panel includes: a substrate (fig. 1, item 101; ¶38); a driving element (fig. 5, T1; fig. 14, item D_TR; ¶72; ¶169) disposed on the substrate; a first switch element (fig. 14, item P_TR; ¶170) disposed on the substrate; a driving voltage wire (fig. 14, item 410a) electrically connected to the first switch element (¶177, “the power source wire 410 may be electrically connected to the first electrode 102d via the pixel transistor P_JR”); and a compensation electrode layer (fig. 14, item 410b) electrically connected to the driving voltage wire (¶173, “the power source wire 410 may have a double-layered structure which includes a first conductive layer 410a and a second conductive layer 410b electrically connected to the first conductive layer 410a… When the power source wire 410 is in a double-layered structure, resistance of the wire may be reduced. thereby preventing screen degradation caused by RC delay” – therefore item 410b is a compensation electrode layer), and wherein the driving voltage wire and the compensation electrode layer are disposed in different layers (fig. 14, see item 410a and 410b).
With respect to Claim 18, claim 17 is incorporated, Lee discloses wherein the display panel further includes: a first planarization layer (fig. 14, item 105 functions as a first planarization layer) disposed on the driving element and the first switch element (¶170, “A second insulating layer 105 (for example, a first interlayer insulating layer) is between the gate electrode 102b and the source and drain electrodes 102c”; ¶172, “The second insulating layer 105 is between the gate electrode 110b and the source and drain electrode 110c” –item 105 is disposed the driving element and the first switch element since item 105 is disposed on the gate electrodes); and a second planarization layer (fig. 14, item 106 functions as a second planarization layer) disposed on the driving voltage wire (¶174, “The third insulating layer 106 is between the first conductive layer 410a and the second conductive layer 410b”), and wherein the compensation electrode layer (fig. 14, item 410b: compensation electrode layer) is disposed on the second planarization layer.
Allowable Subject Matter
Claims 4-12 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to Claims 4 and 19, the closest prior art is Park et al. (KR20220050117A) hereinafter referred to as Park. Park teaches a pixel in figure 9 comprising a driving voltage wire (fig. 9, item 231), a source electrode of a transistor (fig. 9, item 213), and a connecting electrode portion (fig. 9, item 240). None of the prior art teaches an electrode pattern configured to penetrate the first planarization layer and to be connect to a source-drain electrode pattern of the driving element, wherein the driving voltage wire is configured to penetrate the first planarization layer and to be connected to the metal pattern including all the base limitations.
With respect to claim 11, none of the prior art teaches wherein the compensation electrode layer is disposed to overlap the driving element and the first switch element.
Conclusion
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/DONNA V Bocar/ Examiner, Art Unit 2621