Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 4, 11, 17-18, and 20 are amended. Claims 13-16 are withdrawn. Claim 19 is cancelled. Claim 21 is newly added. Claims 1-12, 17-18, and 20-21 are currently under review.
Response to Arguments
Applicant’s arguments, see pages 10-12, filed April 15, 2026, with respect to the rejection(s) of claim(s) 1-3 and 17-18 under Lee have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lim et al. (Pub. No.: US 2025/0160148).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lim et al. (Pub. No.: US 2025/0160148 A1) hereinafter referred to as Lim.
With respect to Claim 1, Lim discloses a display panel (fig. 2; ¶73-74), comprising: a substrate (figs. 3 and 15-16, item 110; ¶84); a driving element (figs. 5 and 15, item T1) disposed on the substrate; a first switch element (figs. 5 and 16, item T5) disposed on the substrate; a driving voltage wire (figs. 5 and 16, item VDL) electrically connected to the first switch element (fig. 5, via item PC2); and a compensation electrode layer (figs. 6 and 15-16, item MASL comprising items MASL1 and MASL2) electrically connected to the driving voltage wire (¶147, “The mesh auxiliary lines MASL may include first mesh auxiliary lines MASL1 connected (e.g., electrically connected) to the first power lines VDL, and second mesh auxiliary lines MASL2 connected (e.g., electrically connected) to the second power lines VRFL”) and having a mesh shape (fig. 6), wherein the driving voltage wire and the compensation electrode layer are disposed in different layers (figs. 15-16; ¶137; ¶147).
With respect to Claim 2, claim 1 is incorporated, Lim discloses further comprising: a first planarization layer (figs. 15-16, item 125; ¶197, an interlayer insulating layer can also serve as a planarization layer) disposed on the driving element and the first switch element (figs. 15-16); and a second planarization layer (figs. 15-16, item 126; ¶197) disposed on the driving voltage wire, wherein the compensation electrode layer is disposed on the second planarization layer (figs. 15-16).
With respect to Claim 3, claim 2 is incorporated, Lim discloses further comprising: a third planarization layer (figs. 15-16, item 127; ¶197) disposed on the compensation electrode layer (figs. 15-16).
With respect to Claim 4, claim 3 is incorporated, Lim discloses further comprising: a metal pattern (figs. 12-14,item ACE2; ¶217, “The first power line VDL may extend in the first direction DR1 and may overlap the capacitor electrode CAE. As a result, the second pixel capacitor (e.g., PC2 in FIG. 5) may be provided by an overlapping area between the capacitor electrode CAE and the first power line VDL”; ¶226, “the second auxiliary connection electrode ACE2 may be connected (e.g., electrically connected) to the capacitor electrode CAE through a third auxiliary connection hole ACCH3, and may be connected (e.g., electrically connected) to the second electrode D5 of the fifth transistor T5 through a fourth auxiliary connection hole ACCH4”) connected between the first switch element (figs. 5 and 12, item T5) and the driving voltage wire (figs. 5 and 14, item VDL, via the capacitor); and an electrode pattern (fig. 15, item VDCE) configured to penetrate the first planarization layer (fig. 15, item 125) and to be connected to a source-drain electrode pattern of the driving element (fig. 5, via connections thru item T6), wherein the driving voltage wire is configured to penetrate the first planarization layer and to be connected to the metal pattern (figs. 14, items ACE2, VDCE, VDL).
With respect to Claim 5, claim 4 is incorporated, Lim discloses wherein the compensation electrode layer (fig. 15, item MASL1; fig. 16, items MASL1 and MASL2) is configured to penetrate the second planarization layer (fig. 15, item 126 via MCH11 and fig. 16, item 126 via MCH2) and to be electrically connected to the driving voltage wire (fig. 15, item VDL; fig. 16, item VRFL).
With respect to Claim 11, Lim discloses a display panel (fig. 2; ¶73-74), comprising: a substrate (figs. 3 and 15-16, item 110; ¶84); a driving element (figs. 5 and 15, item T1) disposed on the substrate; a first switch element (figs. 5 and 16, item T5) disposed on the substrate; a driving voltage wire (figs. 5 and 16, item VDL) electrically connected to the first switch element (fig. 5, via item PC2); and a compensation electrode layer (figs. 6 and 15-16, item MASL comprising items MASL1 and MASL2) electrically connected to the driving voltage wire (¶147, “The mesh auxiliary lines MASL may include first mesh auxiliary lines MASL1 connected (e.g., electrically connected) to the first power lines VDL, and second mesh auxiliary lines MASL2 connected (e.g., electrically connected) to the second power lines VRFL”), wherein the driving voltage wire and the compensation electrode layer are disposed in different layers (figs. 15-16; ¶137; ¶147), and wherein the compensation electrode layer is disposed to overlap the driving element and the first switch element (figs. 15-16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17-18 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lim in view of Ka et al. (Pub. No.: US 2017/0287937 A1) hereinafter referred to as Ka.
With respect to Claim 17, Lim teaches a display device (fig. 1; ¶72-73), comprising: a display panel (fig. 2; ¶73-74); a data driver (figs. 3 and 6, item 200; ¶163) configured to drive the display panel; and scan write lines, scan write signals, and gate control signals are configured to drive the display panel, wherein the display panel includes: a substrate (figs. 3 and 15-16, item 110; ¶84); a driving element (figs. 5 and 15, item T1) disposed on the substrate; a first switch element (figs. 5 and 16, item T5) disposed on the substrate; a first planarization layer (figs. 15-16, item 125; ¶197, an interlayer insulating layer can also serve as a planarization layer) disposed on the driving element and the first switch element (figs. 15-16); a driving voltage wire (figs. 5 and 16, item VDL) electrically connected to the first switch element (fig. 5, via item PC2); a metal pattern (figs. 12-14,item ACE2; ¶217, “The first power line VDL may extend in the first direction DR1 and may overlap the capacitor electrode CAE. As a result, the second pixel capacitor (e.g., PC2 in FIG. 5) may be provided by an overlapping area between the capacitor electrode CAE and the first power line VDL”; ¶226, “the second auxiliary connection electrode ACE2 may be connected (e.g., electrically connected) to the capacitor electrode CAE through a third auxiliary connection hole ACCH3, and may be connected (e.g., electrically connected) to the second electrode D5 of the fifth transistor T5 through a fourth auxiliary connection hole ACCH4”) connected between the first switch element (figs. 5 and 12, item T5) and the driving voltage wire (figs. 5 and 14, item VDL, via the capacitor); an electrode pattern (fig. 15, item VDCE) configured to penetrate the first planarization layer (fig. 15, item 125) and to be connected to a source-drain electrode pattern of the driving element (fig. 5, via connections thru item T6); and a compensation electrode layer (figs. 6 and 15-16, item MASL comprising items MASL1 and MASL2) electrically connected to the driving voltage wire (¶147, “The mesh auxiliary lines MASL may include first mesh auxiliary lines MASL1 connected (e.g., electrically connected) to the first power lines VDL, and second mesh auxiliary lines MASL2 connected (e.g., electrically connected) to the second power lines VRFL”), wherein the driving voltage wire and the compensation electrode layer are disposed in different layers (figs. 15-16; ¶137; ¶147), and wherein the driving voltage wire is configured to penetrate the first planarization layer and to be connected to the metal pattern (figs. 14, items ACE2, VDCE, VDL).
Lim does not explicitly indicate a gate driver configured to drive the display panel.
Ka teaches a display device (fig. 1; ¶53), comprising: a display panel (fig. 1, item 300; ¶53); a data driver (figs. 1-2, item 400; ¶55) configured to drive the display panel; and gate drivers (fig. 1, item 500a and 500b; ¶55) configured to drive the display panel.
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display device of Lim, such that a gate driver is configured to drive the display panel, as taught by Ka so as to provide common means to provide scan write lines, scan write signals, and gate control signals to the display device.
With respect to Claim 18, claim 17 is incorporated, Lim teaches wherein the display panel further includes: a second planarization layer (figs. 15-16, item 126; ¶197) disposed on the driving voltage wire, and wherein the compensation electrode layer is disposed on the second planarization layer (figs. 15-16).
With respect to Claim 20, claim 18 is incorporated, Lim teaches wherein the compensation electrode layer (fig. 15, item MASL1; fig. 16, items MASL1 and MASL2) is configured to penetrate the second planarization layer (fig. 15, item 126 via MCH11 and fig. 16, item 126 via MCH2) and to be electrically connected to the driving voltage wire (fig. 15, item VDL; fig. 16, item VRFL).
With respect to Claim 21, claim 17 is incorporated, Lim teaches the compensation electrode layer has a mesh shape and includes at least one aperture region (fig. 6; ¶147).
Allowable Subject Matter
Claims 6-10 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 6, none of the prior art teaches further comprising: an anode electrode connected to the electrode pattern; an emission layer disposed on the anode electrode; a cathode electrode disposed on the emissive layer; and a connecting electrode portion disposed in the same layer as the compensation electrode layer and configured to connect the electrode pattern and the anode electrode.
Conclusion
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/DONNA V Bocar/ Primary Examiner, Art Unit 2621
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