DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed March 27, 2026 has been entered. Claims 1-20 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-5, 8-12, and 15-18 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Kan et al. (US 2018/0373428).
Regarding claim 1, Kan et al. disclose:
A memory sub-system comprising:
a memory device configured as primary memory (FIG. 5 Low performance & endurance media 504; [0032] main memory section 504; [0034] the lower performance/lower endurance solid state non-volatile media of main memory section 504 may be QLC NAND flash memory having greater than 1500 microsecond programming time and an endurance level of less than or equal to about 300 (e.g., 100 to 300) cumulative total P/E cycles);
an ultra-high endurance storage class memory device ([0008] any type of memory media that may be segregated into separate high endurance (or high performance/high endurance) and low endurance (or low performance/low endurance) portions) comprising a portion allocated as a host data buffer (FIG. 5 High performance & endurance media 502; [0032] input buffer section 502; [0034] the higher performance/higher endurance solid state non-volatile media of input buffer section 502 may be SLC NAND flash memory having 200 to 300 microsecond programming time and an endurance level of greater than or equal to about 30,000 (e.g., 30,000 to 100,000) cumulative total P/E cycles); and
a processing device, operatively coupled with the memory device and the ultra-high endurance storage class memory device ([0030] a nonvolatile memory (e.g., Flash) controller 206 (e.g., any suitable programmable integrated circuit such as microprocessor, microcontroller, ASIC, FPGA, etc.)…to control reads to and writes from the memory elements 210 of array 208 as well an LBA counter 222 that may be used together with mapping table 220 to manage migration (e.g., eviction) of data from an input data buffer section to a main memory section of the NAND memory device as will be described further herein), to perform operations comprising:
receiving host data to be stored in the memory device (FIG. 5 Data input 592);
causing the host data to be stored in the host data buffer of the ultra-high endurance storage class memory device during a buffer tenure ([0032] LBA input data 592 is provided under the control of memory controller 206 to higher performance/higher endurance solid state non-volatile media of input buffer section 502 of memory device 182 that is positioned in the data-receiving front of memory device 187);
causing a first portion of the host data stored in the host data buffer to be overwritten during the buffer tenure (FIGs. 1 and 2; [0006]-[0007]; FIGs. 6 and 7; [0037]; invalidating data results in overwriting of the data); and
in response to determining that a second portion of the host data satisfied a buffer tenure requirement (FIG. 9 step 904 Filter valid data with less than high frequency data threshold; [0040] in step 904, memory controller 206 applies a predefined high frequency data threshold (e.g., such as 3 sigma LBA update frequency distribution) to filter out all valid data (e.g., pages) having an LBA update frequency distribution that is greater than or equal to 3 sigma LBA update frequency distribution so that only valid data parts (e.g., pages) having a LBA update frequency distribution that is less than 3 sigma LBA update frequency distribution are classified as low frequency LBA update data for eviction to lower performance/lower endurance memory media of main memory section 604, while all valid data parts (e.g., pages) having a LBA update frequency distribution that is greater than or equal to 3 sigma LBA update frequency distribution are classified as high frequency LBA update data for retention in higher performance/higher endurance memory media of input buffer section 602), causing the second portion of the host data to be written from the host data buffer to the primary memory of the memory device (FIG. 9 step 908 Evict data to low endurance media).
Kan et al. do not appear to explicitly teach “a memory device” and an ultra-high endurance storage class memory. However, Kan et al. teach at paragraph [0009] “although NAND flash memory media examples are described herein in which endurance and performance levels vary correspondingly, the disclosed methods and systems may be implemented handle data migration (e.g., eviction) from any relatively higher endurance solid state memory media to a relatively lower endurance solid state memory media, regardless of any relative difference in performance between the two types of memory.” Therefore, based on the teachings of Kan et al., it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to use a low-endurance memory media and a high-endurance memory media that are separate from each other. Separate memory media would not result in a patentable significance and amounts to an obvious design choice.
Regarding claim 2, Kan et al. disclose:
The memory sub-system of claim 1, wherein the second portion of the host data comprises valid data that is not overwritten during the buffer tenure (FIG. 9 step 910 Leave the valid data with high frequency in the high endurance media).
Regarding claim 3, Kan et al. disclose:
The memory sub-system of claim 1, the operations further comprising allocating the host data buffer having a first size ([0036] input buffer section 602 is smaller in capacity than main memory section 604. In this regard, relative size difference between input buffer section 602 and main memory section 604 may varied as desired to fit a given application, but in one embodiment data capacity of input buffer section 602 may be about one third the data capacity of main memory section 604, although in other embodiments data capacity of input buffer section 602 may be less than one third the data capacity of main memory section 604 or may be greater than the data capacity of main memory section 604).
Regarding claim 4, Kan et al. disclose:
The memory sub-system of claim 1, the operations further comprising determining an amount of host data overwritten during the buffer tenure ([0040] step 902 where memory controller identifies all data blocks 610 in input buffer 602 that contain valid data together with a threshold amount of invalid data, e.g., such as data block 610b of FIG. 6).
Regarding claim 5, Kan et al. disclose:
The memory sub-system of claim 4, the operations further comprising comparing the amount of host data overwritten during the buffer tenure to a threshold level ([0040] step 902 where memory controller identifies all data blocks 610 in input buffer 602 that contain valid data together with a threshold amount of invalid data, e.g., such as data block 610b of FIG. 6).
Claims 8-12 and 15-18 recite limitations that are substantially similar to the limitations of claims 1-5. Therefore, claims 8-12 and 15-18 are rejected under the same reasoning as claims 1-
Allowable Subject Matter
Claims 6-7, 13-14, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims as discussed in the Non-Final Rejection mailed January 16, 2026.
Response to Arguments
Applicant's arguments filed March 27, 2026 have been fully considered but they are not persuasive.
Applicant argues that Kan et al. does not disclose the limitation “causing the host data to be stored in the host data buffer of the ultra-high endurance storage class memory device during a buffer tenure” (Remarks page 7). The examiner respectfully disagrees. The claimed buffer tenure is not defined in the claims and no specific definition is provided in the specification. While the claims are read in light of the specification, limitations from the specification are not brought into the claims when interpreting claim limitations. Based on the broadest reasonable interpretation of a buffer tenure (i.e., the period that a buffer is receiving and evicting data), Kan et al. discloses the claim limitation as discussed above. Therefore, the 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Kan et al. is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
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/TRACY A WARREN/ Primary Examiner, Art Unit 2137
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