Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to communications filed on 12/5/24.
Claims 1-15 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 11 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raman (US Patent 10082847; cited in IDS) in view of North et al (US Patent Application Publication 2023/0230194)
For claim 1, Raman teaches the following limitations: An electronic device (Fig 1- Fig 4) comprising: one or more processors comprising processing circuitry; and memory comprising one or more storage medium storing instructions that, when executed by the one or more processors (line 18, col 10 through line 16, col 11 mention that computer readable medium storing instructions for use by an instruction execution system such as a processor containing system), cause the electronic device to: measure a (lines 5-20 of col 2; temperature of the PCD is monitored; lines 64, col 3 through line 6, col 4 mention about sensor and thermistor to measure the temperature; various 157 in Fig 1 measures temperature); monitor a load of hardware (lines 45-48 of col 9 mentions detect electrical current limitations) and an occurrence of one or more preset events (whether temperature exceeded a threshold value; lines 9-15 of col 6); determine a proportional-integral-differential (PID) level of the electronic device (line 30, col 7 through line 67, col 7 mention the PID controller dynamics; the constants are set to provide stable output; the constants and other parameters define the level of the PID controller) to control heat generation based on the (Fig 2A shows that temperature is controlled based on sensed temperature in 206; col 6 describes how the temperature is controlled; Fig 2B step 305 to step 330 mentions temperature control by the PID controller); set each of a first minimum clock (lines 1-5 of col 7 mention DCVS algorithm to dynamically set the frequency in block 227; the DCVS provides ranges on clock frequency values, including a minimum and maximum value) of a first limit clock (235 in Fig 2A is the first limit clock for the CPU; lines 35-45 of col 6 and lines 7-18 of col 7 mention the CPU frequency adjustment) of a central processing unit (CPU) (lines 20-25 of col 4, 35-42 of col 4, line 58, col 5 through line 20, col 6 – adjusts clock frequency of CPU) and a second minimum clock of a second limit clock of a graphics processing unit (GPU) (Fig 4 shows the PID control for two components 301A and 301B; lines 50-55 of col 9 mention that components can be CPU and GPU; lines 20-25 of col 4; lines 1-8 of col 6; GPU is controlled similarly as CPU), based on the PID level (lines 55-55 of col 8; lines 1-10 of col 9; lines 30-67 of col 7 – the PID level determines the ideal operating frequency) and the load (CL situation is mentioned in lines 43-48 of col 9; lines 59-65 of col 1; DCVS mentioned in 1-6 of col 7 and other places; such load variation affects the thermal mitigation algorithms, which further determines the loop control of Fig 2A and Fig 4); and determine, such that the (Fig 2B, temperature is monitored corresponding to threshold and lines 48-51 of col 7 mention that the setpoint is reached quickly), the first limit clock to be greater than or equal to the first minimum clock and the second limit clock to be greater than or equal to the second minimum clock (the DCVS clock frequency shown in 227 is the desired frequency lines 10-18 of col 7, which is intended to be reached quickly lines 50-52 of col 7; lines 1-10 of col 10; Fig 4 shows the control of two components – CPU and GPU).
Raman does not explicitly mention measuring surface temperature. Raman uses off-chip thermistors for temperature measurement (lines 1-6 of col 4). Therefore, it is likely that the thermistors measure surface temperature. For further clarification, North et al mention that the surface temperature is monitored and throttled (Fig 3 and Fig 4).
It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to use a surface temperature sensor to monitor the surface temperature and throttle the components to reduce surface temperature since that will enhance reliability of the system. Temperature control is an essential task to improve reliability because overheating causes damage to the components of the information handling system.
For claim 2, Raman teaches wherein the one or more processors are configured to execute the instructions to cause the electronic device to determine, based on an occurrence of at least one event of the one or more preset events being monitored (whether temperature exceeded a threshold value; lines 9-15 of col 6), the PID level to be a highest level (Fig 3 shows one PID controller is effective based on threshold being met; thus the PID controller being the highest level) among a first level indicated by the at least one event (the first level is when temperature is less than setpoint shown in Fig 2A) and a second level corresponding to the surface temperature (the first level is when temperature is more than setpoint shown in Fig 2A, which is corresponds to the temperature).
For claim 11, Raman teaches the following limitations: A method performed by a processor (line 18, col 10 through line 16, col 11 mention that computer readable medium storing instructions for use by an instruction execution system such as a processor containing system), comprising: measuring a temperature of an electronic device (lines 5-20 of col 2; temperature of the PCD is monitored; lines 64, col 3 through line 6, col 4 mention about sensor and thermistor to measure the temperature; various 157 in Fig 1 measures temperature); monitoring a load of hardware (lines 45-48 of col 9 mentions detect electrical current limitations) and an occurrence of one or more preset events (whether temperature exceeded a threshold value; lines 9-15 of col 6); determining a proportional-integral-differential (PID) level of the electronic device (line 30, col 7 through line 67, col 7 mention the PID controller dynamics; the constants are set to provide stable output; the constants and other parameters define the level of the PID controller) to control heat generation based on the (Fig 2A shows that temperature is controlled based on sensed temperature in 206; col 6 describes how the temperature is controlled; Fig 2B step 305 to step 330 mentions temperature control by the PID controller); setting each of a first minimum clock (lines 1-5 of col 7 mention DCVS algorithm to dynamically set the frequency in block 227; the DCVS provides ranges on clock frequency values, including a minimum and maximum value) of a first limit clock (235 in Fig 2A is the first limit clock for the CPU; lines 35-45 of col 6 and lines 7-18 of col 7 mention the CPU frequency adjustment) of a central processing unit (CPU) (lines 20-25 of col 4, 35-42 of col 4, line 58, col 5 through line 20, col 6 – adjusts clock frequency of CPU) and a second minimum clock of a second limit clock of a graphics processing unit (GPU) (Fig 4 shows the PID control for two components 301A and 301B; lines 50-55 of col 9 mention that components can be CPU and GPU; lines 20-25 of col 4; lines 1-8 of col 6; GPU is controlled similarly as CPU), based on the PID level (lines 55-55 of col 8; lines 1-10 of col 9; lines 30-67 of col 7 – the PID level determines the ideal operating frequency) and the load (CL situation is mentioned in lines 43-48 of col 9; lines 59-65 of col 1; DCVS mentioned in 1-6 of col 7 and other places; such load variation affects the thermal mitigation algorithms, which further determines the loop control of Fig 2A and Fig 4); and determining, such that the (Fig 2B, temperature is monitored corresponding to threshold and lines 48-51 of col 7 mention that the setpoint is reached quickly), the first limit clock to be greater than or equal to the first minimum clock and the second limit clock to be greater than or equal to the second minimum clock (the DCVS clock frequency shown in 227 is the desired frequency lines 10-18 of col 7, which is intended to be reached quickly lines 50-52 of col 7; lines 1-10 of col 10; Fig 4 shows the control of two components – CPU and GPU).
Raman does not explicitly mention measuring surface temperature. Raman uses off-chip thermistors for temperature measurement (lines 1-6 of col 4). Therefore, it is likely that the thermistors measure surface temperature. For further clarification, North et al mention that the surface temperature is monitored and throttled (Fig 3 and Fig 4).
It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to use a surface temperature sensor to monitor the surface temperature and throttle the components to reduce surface temperature since that will enhance reliability of the system. Temperature control is an essential task to improve reliability because overheating causes damage to the components of the information handling system.
For claim 15, Raman teaches the following limitations: A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, (line 18, col 10 through line 16, col 11 mention that computer readable medium storing instructions for use by an instruction execution system such as a processor containing system), cause the processor to: measure a (lines 5-20 of col 2; temperature of the PCD is monitored; lines 64, col 3 through line 6, col 4 mention about sensor and thermistor to measure the temperature; various 157 in Fig 1 measures temperature); monitor a load of hardware (lines 45-48 of col 9 mentions detect electrical current limitations) and an occurrence of one or more preset events (whether temperature exceeded a threshold value; lines 9-15 of col 6); determine a proportional-integral-differential (PID) level of the electronic device (line 30, col 7 through line 67, col 7 mention the PID controller dynamics; the constants are set to provide stable output; the constants and other parameters define the level of the PID controller) to control heat generation based on the (Fig 2A shows that temperature is controlled based on sensed temperature in 206; col 6 describes how the temperature is controlled; Fig 2B step 305 to step 330 mentions temperature control by the PID controller); set each of a first minimum clock (lines 1-5 of col 7 mention DCVS algorithm to dynamically set the frequency in block 227; the DCVS provides ranges on clock frequency values, including a minimum and maximum value) of a first limit clock (235 in Fig 2A is the first limit clock for the CPU; lines 35-45 of col 6 and lines 7-18 of col 7 mention the CPU frequency adjustment) of a central processing unit (CPU) (lines 20-25 of col 4, 35-42 of col 4, line 58, col 5 through line 20, col 6 – adjusts clock frequency of CPU) and a second minimum clock of a second limit clock of a graphics processing unit (GPU) (Fig 4 shows the PID control for two components 301A and 301B; lines 50-55 of col 9 mention that components can be CPU and GPU; lines 20-25 of col 4; lines 1-8 of col 6; GPU is controlled similarly as CPU), based on the PID level (lines 55-55 of col 8; lines 1-10 of col 9; lines 30-67 of col 7 – the PID level determines the ideal operating frequency) and the load (CL situation is mentioned in lines 43-48 of col 9; lines 59-65 of col 1; DCVS mentioned in 1-6 of col 7 and other places; such load variation affects the thermal mitigation algorithms, which further determines the loop control of Fig 2A and Fig 4); and determine, such that the converges to a first target temperature corresponding to the PID level (Fig 2B, temperature is monitored corresponding to threshold and lines 48-51 of col 7 mention that the setpoint is reached quickly), the first limit clock to be greater than or equal to the first minimum clock and the second limit clock to be greater than or equal to the second minimum clock (the DCVS clock frequency shown in 227 is the desired frequency lines 10-18 of col 7, which is intended to be reached quickly lines 50-52 of col 7; lines 1-10 of col 10; Fig 4 shows the control of two components – CPU and GPU).
Raman does not explicitly mention measuring surface temperature. Raman uses off-chip thermistors for temperature measurement (lines 1-6 of col 4). Therefore, it is likely that the thermistors measure surface temperature. For further clarification, North et al mention that the surface temperature is monitored and throttled (Fig 3 and Fig 4).
It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to use a surface temperature sensor to monitor the surface temperature and throttle the components to reduce surface temperature since that will enhance reliability of the system. Temperature control is an essential task to improve reliability because overheating causes damage to the components of the information handling system.
Claim(s) 4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raman (US Patent 10082847) in view of North et al (US Patent Application Publication 2023/0230194) in view of Maiya (US Patent Application Publication 20160225348).
For claims 4 and 13, Raman teaches wherein the one or more processors are configured to execute the instructions to cause the electronic device to: determine, for the PID level, the first minimum clock; and determine, for the PID level, the second minimum clock (lines 1-7 of col 7 mention the DCVS algorithm to control clock frequency, which includes determining the range of clock frequency including minimum clock frequency) Raman in view of North does not mention a first average operating clock of the CPU in a first minimum clock range of the first limit clock and a second average operating clock of the GPU in a second minimum clock range of the first limit clock. Maiya et al teaches determining clock based on average over a range ([0125]). Maiya performs determining minimum clock ([0067]). Maiya is configured to use DCVS and uses averaging technique to determine clock rate based on determined clock rates. Thus, with the teachings of Maiya, the minimum clock range can be selected to perform averaging to determine the minimum clock rate. It would have been obvious for one ordinary skill in the art before the effective date of the invention to determine the minimum clock based on averaging the minimum clock range, since the minimum clock is needed to minimize power consumption and averaging is an effective way to determine the minimum clock.
Allowable Subject Matter
Claims 3, 5-10, 12, 14 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/FAHMIDA RAHMAN/Primary Examiner, Art Unit 2175
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