Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The examiner respectfully disagrees that Tabei does not teach storing, as telemetry data, device context data . . . This is claimed so broadly with no description in the claims of the data, other than that it is associated with the failure, that Tabei’s various saving of information noted below are sufficient to teach this aspect. The other newly added aspects are taught, as detailed below, by the newly added references.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tabei (US 20080010506 A1).
As to claim 8, Tabei teaches a method for managing a failure condition at a host, the method comprising:
detecting, in a device, a presence of a host panic capability register exhibiting support for host panic situation awareness (see paragraph 0075 disclosing writing error information into shared memory and reading it to notify the error; the examiner is interpreting this as indicating that the presence of the shared memory has been detected since CPUs write and read the memory and that is how the error notification is made);
preconfiguring a host panic control register of the device, wherein the preconfiguring comprises writing, in the host panic control register, a host panic table comprising addresses and corresponding data/value pairs, and wherein each entry of the host panic table indicates a host critical failure event (see the table in Fig. 5 noting an error tyle and address and paragraphs 0075 0076, disclosing writing error information into a memory); and based on an occurrence of the host critical failure event, issuing, to the device, at least one input/output (I/O) read/write command to store, as telemetry data in the device, device context information that is associated with the host critical failure event (see Fig. 5 and paragraphs 0075 0076, disclosing writing error information into a memory and also writing error information into a register; also see paragraph 0075, disclosing a read; also see paragraphs 0042 0059, 70, and 80, disclosing storing fault information and memory dumps; the examiner interprets this involves some form of write command).
As to claim 10, the reference(s) teach(es) claim 8 as detailed above. It/they further teach(es) the host critical failure event comprises at least one of an improper driver event, a thrashing event, a corrupt registry event, a virus event, a Trojan Horse event, a slow system performance event, a failure to boot event, a compatibility error event, a power problem event, an overheating event, a motherboard failure event, a faulty random access memory (RAM) event, a faulty storage event (see paragraph 0017 and 0041, disclosing a multi-bit error has continuously occurred in the CPU cache), or a faulty processor event (see paragraph 0017 and 0041, disclosing a multi-bit error has continuously occurred in the CPU cache).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 25, and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tabei in view of Gohain (US 20250328413 A1).
As to claim 1, Tabei teaches a method for managing a failure condition at a host, the method comprising:
detecting an occurrence of a host critical failure event at the host (see Figs. 4-7 and paragraphs 0074-0084, disclosing detecting an error in a CPU);
configuring at least one panic bit of a host panic control register of a device, based on the detecting of the occurrence of the host critical failure event (see Fig. 5 and paragraphs 0075 0076, disclosing writing error information into a memory and also writing error information into a register; the examiner interprets this involves at least one bit.); and
issuing, to the device, at least one input/output (I/O) read/write command (see Fig. 5 and paragraphs 0075 0076, disclosing writing error information into a memory and also writing error information into a register; also see paragraph 0075, disclosing a read; also see paragraphs 0042, 0059, 70, and 80, disclosing storing fault information and memory dumps; the examiner interprets this involves some form of write command).
The references do not explicitly teach the device is a peripheral component interconnect express (PCIe) device.
However, Gohain teaches a memory device that can be PCIe (see paragraph 0031).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine the references with the use of a PCIe device because it enables a host to read and write data to a memory system (see paragraph 0031).
As to claim 2, the reference(s) teach(es) claim 1 as detailed above. It/they further teaches determining a presence of a host panic capability register (see paragraph 0075 disclosing writing error information into shared memory and reading it to notify the error; the examiner is interpreting this as indicating that the presence of the shared memory has been detected since CPUs write and read the memory and that is how the error notification is made). It/they do not explicitly teach(es) this is done during initialization of the device.
However, the examiner takes official notice of initialization procedures such as a boot is known in the art.
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to determine the presence of the shared memory early on such as during a boot/initialization because it allow for reading and writing to the shared memory such as is done in Tabei.
As to claim 3, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) the at least one panic bit indicates an event type of the host critical failure event (see Fig. 5 of Tabei, disclosing an error type).
As to claim 4, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) the host critical failure event comprises at least one of an improper driver event, a thrashing event, a corrupt registry event, a virus event, a Trojan Horse event, a slow system performance event, a failure to boot event, a compatibility error event, a power problem event, an overheating event, a motherboard failure event, a faulty random access memory (RAM) event, a faulty storage event (see paragraph 0017 and 0041, disclosing a multi-bit error has continuously occurred in the CPU cache, or a faulty processor event (see paragraph 0017 and 0041, disclosing a multi-bit error has continuously occurred in the CPU cache).
As to claim 25, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) the at least one I/O read/write command causes the PCIe device to save, as telemetry data in the PCIe device, device context information that is associated with the host critical failure event (see Fig. 5 and paragraphs 0075 0076, disclosing writing error information into a memory and also writing error information into a register; also see paragraphs 0042, 0059, 70, and 80, disclosing storing fault information and memory dumps; the examiner interprets this involves some form of write command).
As to claim 28, Tabei teaches the method of claim 8 as detailed above. Tabei does not explicitly teach the device is a peripheral component interconnect express (PCIe) device.
However, Gohain teaches a memory device that can be PCIe (see paragraph 0031).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine the references with the use of a PCIe device because it enables a host to read and write data to a memory system (see paragraph 0031).
Claim(s) 5-7, 26, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tabei in view of Maseiwicz (US 5784390 A).
As to claim 5, Tabei teaches a method for managing a device internal context during a host failure condition at a device, the method comprising:
detecting a host critical failure event by monitoring status of a host panic control register (see Fig. 5 and paragraphs 0075 0076, disclosing writing error information into a memory and also writing error information into a register to notify of a failure event);
receiving, from a host, at least one input/output (I/O) read/write command (see Fig. 5 and paragraphs 0075 0076, disclosing writing error information into a memory and also writing error information into a register; also see paragraph 0075, disclosing a read; also see paragraphs 0042 0059, 70, and 80, disclosing storing fault information and memory dumps; the examiner interprets this involves some form of write command); and
storing, in a memory, device context information based on the at least one I/O read/write command (see Fig. 5 and paragraphs 0075 0076, disclosing writing error information into a memory and also writing error information into a register; also see paragraph 0075, disclosing a read; also see paragraphs 0042,0059, 70, and 80, disclosing storing fault information and memory dumps).
Tabei does not explicitly teach initiating, by the device, an 1/0 throttling mechanism for the at least one I/0 read/write command.
However, Masiewicz teaches that a memory device can throttle a data transfer from a host (see col. 12, lines 60-67).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Tabei with the teachings of Maseiwicz because it enables storage devices to handle situations where they cannot input data as fast as a host can provide it (see col. 12, lines 60-67)).
As to claim 6, the reference(s) teach(es) claim 5 as detailed above. It/they further teaches initializing a host panic capability register to indicate that the device supports host panic situation awareness. (see paragraph 0075 disclosing writing error information into shared memory and reading it to notify the error; the examiner is interpreting this as indicating that the shared memory has been initialized since CPUs write and read the memory and that is how the error notification is made). It/they further teach receiving, through the host panic control register, information regarding occurrences of host critical failure events (see paragraph 0075, disclosing writing error information into shared memory to notify the error to the second CPU). It/they do not explicitly teach(es) the initialization is done during initialization of the device.
However, the examiner takes official notice of initialization procedures such as a boot is known in the art.
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to determine the presence of the shared memory early on such as during a boot/initialization because it allow for reading and writing to the shared memory such as is done in Tabei.
As to claim 7, the reference(s) teach(es) claim 6 as detailed above. It/they further teach(es) the receiving of the information regarding the occurrences of the host critical failure events comprises: reading at least one panic bit of the host panic control register that has been configured by the host (see Fig. 5 and paragraphs 0075 0076, disclosing writing error information into a memory and also writing error information into a register and reading that information; the examiner interprets this involves at least one bit.).
As to claim 26, the references teach claim 5 as detailed above. Tabei further teaches the device context information is stored as telemetry data in the memory, and wherein the memory is in the device (see Fig. 5 and paragraphs 0075 0076, disclosing writing error information into a memory and also writing error information; also see paragraphs 0042 0059, 70, and 80, disclosing storing fault information and memory dumps).
As to claim 27, the references teach claim 5 as detailed above. Maseiwicz further teaches stopping, by the device, the 1/O throttling mechanism after the device context information is saved in the memory (see col. 12, lines 60-67 and col. 13 and Fig. 5, showing the ending of a transfer and deassertion of DMA Ack; the examiner interprets that the device will no longer use this to throttle because the transfer is completed with the deassertion of DMA REQ).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tabei.
As to claim 9, the reference(s) teach(es) claim 8 as detailed above. It/ they further teaches detecting of the presence of the host panic capability register comprises: determining the presence of the host panic capability register (see paragraph 0075 disclosing writing error information into shared memory and reading it to notify the error; the examiner is interpreting this as indicating that the shared memory has been initialized since CPUs write and read the memory and that is how the error notification is made). It/they do not explicitly teach this is done during an initialization of the device.
However, the examiner takes official notice of initialization procedures such as a boot is known in the art.
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to determine the presence of the shared memory early on such as during a boot/initialization because it allow for reading and writing to the shared memory such as is done in Tabei.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON B BRYAN whose telephone number is (571)270-7091. The examiner can normally be reached Mon-Fri, 8-5 First Friday off.
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/JASON B BRYAN/ Primary Examiner, Art Unit 2114
