DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/7/2025 and 8/28/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C.119 (a)-(d). The certified copy has been filed in parent Application No. CN202210644562.4, filed on 6/8/2022.
Claim Objections
Claim 35 objected to because of the following informalities: “…when invoked by the at least one processor of the the target slave node…” should be “…when invoked by the at least one processor of the target slave node…”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 31-36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pascal et al. GB 2587007 A (hereinafter “Pascal”).
As to claim 31:
Pascal discloses:
A slave node, wherein the slave node and a master node are configured in a point-to-multipoint topology (FIG. 1 shows multiple PDs or slaves connected to a single PSE or master, Pascal), and the slave node comprises: at least one processor and a memory coupled to the at least one processor, wherein the memory contains computer instructions, and the at least one processor is configured to invoke the computer instructions, (“there is provided a non-transitory computer-readable medium storing a program which, when executed by a microprocessor or computer system in a device of a power-over-cable system, causes the device to perform the method aforementioned”, Pascal [page 15, line 1]) to enable the slave node to: send a power of the slave node to the master node; (“At step S403, the master terminal obtains the power needs of the terminals that are activated sequentially based on different timeslots, during a sensing phase”, Pascal [page 18, line 20]) receive a power-on instruction from the master node; and connect a link between the master node and the slave node according to the power-on instruction, to power on the slave node. (“The terminals then receive a notification (S405) informing them of whether or not they have been selected for being activated simultaneously. Once again, sending a notification to each terminal is performed sequentially by the master terminal, so that no more than two terminals (including the master terminal) are activated at each time during the notification phase”, Pascal [page 18, line 28]) (“At step S404, power admission is performed by the master terminal. This comprises selecting a set of terminals that can be powered up simultaneously”, Pascal [page 18, line 26])
As to claim 32:
Pascal discloses:
The slave node according to claim 31, wherein the computer instructions, when invoked by the at least one processor, further enable the slave node to: obtain the power of the slave node; (“As another example, the line sensing timeslot 521 allows a specific terminal to request its controller to activate its load resistance using a Load activation request message 930 and another terminal to request its controller to measure the voltage at its bound using a Voltage sensing request message 930 and then waits for a Voltage sensing / Load activation information message responses from their respective controllers”, Pascal [page 20, line 24])
send the power of the slave node to the master node; receive the power-on instruction from the master node; and control, according to the power-on instruction, the link between the master node and the slave node, to power on the slave node. (“The terminals then receive a notification (S405) informing them of whether or not they have been selected for being activated simultaneously. Once again, sending a notification to each terminal is performed sequentially by the master terminal, so that no more than two terminals (including the master terminal) are activated at each time during the notification phase”, Pascal [page 18, line 28]) (“At step S404, power admission is performed by the master terminal. This comprises selecting a set of terminals that can be powered up simultaneously”, Pascal [page 18, line 26])
As to claim 33:
Pascal discloses:
The slave node according to claim 32, wherein the slave node further comprises a switch; the computer instructions, when invoked by the at least one processor, further enable the slave node to control, according to the power-on instruction, the switch to connect the link between the master node and the slave node; and the switch is configured to connect the link between the master node and the slave node according to a control instruction. (“If the slave terminal is not allowed to be active, it configures its controller using another power admission notification message 950, which requests the controller to switch off the power delivery from the PSE, thereby deactivating the terminal”, Pascal [page 21, line 8]) (“The terminals then receive a notification (S405) informing them of whether or not they have been selected for being activated simultaneously. Once again, sending a notification to each terminal is performed sequentially by the master terminal, so that no more than two terminals (including the master terminal) are activated at each time during the notification phase”, Pascal [page 18, line 28]) (“At step S404, power admission is performed by the master terminal. This comprises selecting a set of terminals that can be powered up simultaneously”, Pascal [page 18, line 26])
As to claim 34:
Pascal discloses:
The slave node according to claim 32, wherein the slave node comprises a slave control device and a powered device, the slave control device is decoupled from the powered device, and the slave control device comprises a power sourcing equipment (PSE) chip; (FIG. 1 shows multiple PDs or slaves connected to a single PSE or master, Pascal)
the PSE chip is configured to: determine a power of the powered device based on a feedback current from the powered device, wherein the feedback current is determined by the powered device based on a classification voltage of the PSE chip; (“As another example, the line sensing timeslot 521 allows a specific terminal to request its controller to activate its load resistance using a Load activation request message 930 and another terminal to request its controller to measure the voltage at its bound using a Voltage sensing request message 930 and then waits for a Voltage sensing / Load activation information message responses from their respective controllers”, Pascal [page 20, line 24])
and send the power of the powered device; and the computer instructions, when invoked by the at least one processor, further enable the slave node to: receive the power of the powered device from the PSE chip; and determine the power of the slave node based on the power of the powered device; and the PSE chip is further configured to connect the link between the master node and the slave node according to a control instruction. (“As another example, the sharing timeslot 541 allows an active slave terminal to send its power need to the master terminal, for instance using a voltage sensing feedback notification message 980 which embeds the voltage measurement(s) performed during a sensing time period 520”, Pascal [page 20, line 30]) (“At step S403, the master terminal obtains the power needs of the terminals that are activated sequentially based on different timeslots, during a sensing phase”, Pascal [page 18, line 20])
As to claim 35:
Pascal discloses:
A power supply system, wherein a topology of the power supply system is a point-to-multipoint topology, the power supply system comprises a master node and N first slave nodes, N≥2, and N is an integer, (FIG. 1 shows multiple PDs or slaves connected to a single PSE or master, Pascal) and each of the N first slave nodes comprises at least one processor and a memory coupled to the at least one processor and containing instructions, the instructions, when invoked by the at least one processor of each the N first slave nodes, (“there is provided a non-transitory computer-readable medium storing a program which, when executed by a microprocessor or computer system in a device of a power-over-cable system, causes the device to perform the method aforementioned”, Pascal [page 15, line 1]) cause each of the N first slave nodes to send a power to the master node; (“At step S403, the master terminal obtains the power needs of the terminals that are activated sequentially based on different timeslots, during a sensing phase”, Pascal [page 18, line 20]) the master node comprises at least one processor and a memory coupled to the at least one processor and containing instructions, the instructions, when invoked by the at least one processor of the master node, cause the master node to obtain respective powers of each of the N first slave nodes; (“At step S403, the master terminal obtains the power needs of the terminals that are activated sequentially based on different timeslots, during a sensing phase”, Pascal [page 18, line 20]) and supply power to a target slave node in the N first slave nodes based on the powers of the N first slave nodes and an output power of the master node; (“At step S404, power admission is performed by the master terminal. This comprises selecting a set of terminals that can be powered up simultaneously”, Pascal [page 18, line 26])
and the instructions contained in the memory of the target slave node, when invoked by the at least one processor of the the target slave node, cause the target slave node to: receive a power-on instruction from the master node; and connect a link between the master node and the target slave node according to the power-on instruction, to power on the target slave node. (“The terminals then receive a notification (S405) informing them of whether or not they have been selected for being activated simultaneously. Once again, sending a notification to each terminal is performed sequentially by the master terminal, so that no more than two terminals (including the master terminal) are activated at each time during the notification phase”, Pascal [page 18, line 28]) (“At step S404, power admission is performed by the master terminal. This comprises selecting a set of terminals that can be powered up simultaneously”, Pascal [page 18, line 26])
As to claim 36:
Pascal discloses:
The power supply system according to claim 35, wherein the instructions contained in the memory of each of the N first slave nodes, when invoked, further cause each of the N first slave nodes to: obtain the power of each of the N first slave nodes through power detection or power negotiation. (“As another example, the line sensing timeslot 521 allows a specific terminal to request its controller to activate its load resistance using a Load activation request message 930 and another terminal to request its controller to measure the voltage at its bound using a Voltage sensing request message 930 and then waits for a Voltage sensing / Load activation information message responses from their respective controllers”, Pascal [page 20, line 24])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-23 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Pascal et al. GB 2587007 A (hereinafter “Pascal”) in view of Morris US 20060203796 (hereinafter “Morris”)
As to claim 21:
Pascal discloses:
A master node, wherein the master node and N first slave nodes are configured in a point-to-multipoint topology, N≥2, and N is an integer, (FIG. 1 shows multiple PDs or slaves connected to a single PSE or master, Pascal) and the master node comprises at least one processor and a memory coupled to the at least one processor, wherein the memory contains computer instructions, and the at least one processor is configured to invoke the computer instructions, to enable the master node to: (“there is provided a non-transitory computer-readable medium storing a program which, when executed by a microprocessor or computer system in a device of a power-over-cable system, causes the device to perform the method aforementioned”, Pascal [page 15, line 1])
obtain respective powers of each of the N first slave nodes; (“At step S403, the master terminal obtains the power needs of the terminals that are activated sequentially based on different timeslots, during a sensing phase”, Pascal [page 18, line 20])
and supply power to a target slave node in the N first slave nodes based on the respective powers of the N first slave nodes and an output power of the master node. (“At step S403, the master terminal obtains the power needs of the terminals that are activated sequentially based on different timeslots, during a sensing phase”, Pascal [page 18, line 20]) (“At step S404, power admission is performed by the master terminal. This comprises selecting a set of terminals that can be powered up simultaneously”, Pascal [page 18, line 26])
Pascal as described above does not explicitly teach:
connect links between the master node and all of the N first slave nodes in a time-division manner;
However, Morris further teaches assigning time slots to connect multiple slave nodes to a master node which includes:
connect links between the master node and all of the N first slave nodes in a time-division manner; (FIG. 1 shows a master node communicating with all of the slave nodes in a time division manner, Morris)
Pascal and Morris are analogous because they pertain to master and slave communication.
Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include assigning time slots to connect multiple slave nodes to a master node as described in Morris into Pascal. By modifying the method to include assigning time slots to connect multiple slave nodes to a master node as taught by Morris, the benefits of minimized shutdown and reboot cycles (Pascal [page 14, line 7]) and improved communication efficiency (Morris [0025]) are achieved.
As to claim 22:
Pascal as described above does not explicitly teach:
The master node according to claim 21, wherein the computer instructions, when invoked by the at least one processor, further enable the master node to: connect the links between the master node and all of the N first slave nodes in the time-division manner.
However, Morris further teaches assigning time slots to connect multiple slave nodes to a master node which includes:
The master node according to claim 21, wherein the computer instructions, when invoked by the at least one processor, further enable the master node to: connect the links between the master node and all of the N first slave nodes in the time-division manner. (FIG. 1 shows a master node communicating with all of the slave nodes in a time division manner, Morris)
Pascal and Morris are analogous because they pertain to master and slave communication.
Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include assigning time slots to connect multiple slave nodes to a master node as described in Morris into Pascal. By modifying the method to include assigning time slots to connect multiple slave nodes to a master node as taught by Morris, the benefits of minimized shutdown and reboot cycles (Pascal [page 14, line 7]) and improved communication efficiency (Morris [0025]) are achieved.
As to claim 23:
Pascal discloses:
The master node according to claim 21, wherein the master node comprises a power sourcing equipment (PSE) chip (FIG. 1 shows multiple PDs or slaves connected to a single PSE or master, Pascal), configured to: receive a feedback current from each of the N first slave nodes, wherein each feedback current is determined by its respective one of the N first slave nodes based on a classification voltage of the PSE chip; and determine a power of each of the N first slave nodes based on the feedback current of each first slave node. (“At step S403, the master terminal obtains the power needs of the terminals that are activated sequentially based on different timeslots, during a sensing phase”, Pascal [page 18, line 20]) (“As another example, the sharing timeslot 541 allows an active slave terminal to send its power need to the master terminal, for instance using a voltage sensing feedback notification message 980 which embeds the voltage measurement(s) performed during a sensing time period 520”, Pascal [page 20, line 32]) (“The message 980 is a feedback notification message. It may be used by a slave terminal (source) to provide the master terminal (destination) with the voltage Vin measured by the sensing unit on the cable at its bounds. The measured voltage Vin may be included in the feedback information 981 appended to the message 980. Additional information related to the typical power needs for the slave terminal and its controller, such as power class information, minimum, maximum or average power consumption, may also be part of the feedback information 981”, Pascal [page 30, line 1])
As to claim 30:
Pascal discloses:
The master node according to claim 21, wherein the master node comprises a master control device and a power sourcing equipment, and the master control device is coupled to or decoupled from the power sourcing equipment. (FIG. 1 shows multiple PDs or slaves connected to a single PSE or master, Pascal) (“According to a first aspect of the invention, there is provided a method of controlling activation of terminals connected to a Power Sourcing Equipment, PSE, in a power over cable system, the method comprising: activating terminals pair by pair to obtain, by a master terminal, power needs of the terminals; based on the obtained power needs, selecting, by the master terminal, a set of terminals to be simultaneously powered up by the PSE; and sending, by the master terminal, a notification to each selected terminal in order to inform it that it has been selected for being activated”, Pascal [page 13, line 32])
Claim(s) 24 is rejected under 35 U.S.C. 103 as being unpatentable over Pascal in view of Morris, as applied to claim 21 above, and further in view of Bhagavathula et al. US 11604501 B2 (hereinafter “Bhagavathula”)
As to claim 24:
The combination of Pascal and Morris as described above does not explicitly teach:
The master node according to claim 21, wherein the computer instructions, when invoked by the at least one processor, further enable the master node to: perform power negotiation with each of the N first slave nodes; and determine the power of each of the N first slave nodes based on a negotiation result of the power negotiation.
However, Bhagavathula further teaches power negotiation which includes:
The master node according to claim 21, wherein the computer instructions, when invoked by the at least one processor, further enable the master node to: perform power negotiation with each of the N first slave nodes; and determine the power of each of the N first slave nodes based on a negotiation result of the power negotiation. (“The power distribution across each port of the number of ports may be controlled by a coordinated pair of a master control mechanism and a slave handler mechanism. The master control mechanism may maintain a record of the allocated power across various ports and available power, and may control the slave handler mechanism via a request-response communication interface. In this case, the slave handler mechanism may deliver power based on active power negotiation protocol out of the supported protocols and based on the control requests from the master control mechanism.”, Bhagavathula [22])
Pascal, Bhagavathula, and Morris are analogous because they pertain to master and slave communication.
Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include power negotiation as described in Bhagavathula into Pascal as modified by Morris. By modifying the method to include power negotiation as taught by Bhagavathula, the benefits of minimized shutdown and reboot cycles (Pascal [page 14, line 7]) and improved communication efficiency (Morris [0025] and Bhagavathula [11]) are achieved.
Claim(s) 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Pascal in view of Morris, as applied to claim 21 above, and further in view of Burkland et al. US 7865754 B2 (hereinafter “Burkland”)
As to claim 25:
The combination of Pascal and Morris as described above does not explicitly teach:
The master node according to claim 22, wherein the computer instructions, when invoked by the at least one processor, further enable the master node to: determine, when a sum of the respective powers of each of the N first slave nodes is less than or equal to the output power of the master node, that the target slave node comprises the N first slave nodes; and connect the links between the master node and the N first slave nodes, to supply power to the N first slave nodes.
However, Burkland further teaches power budgeting which includes:
The master node according to claim 22, wherein the computer instructions, when invoked by the at least one processor, further enable the master node to: determine, when a sum of the respective powers of each of the N first slave nodes is less than or equal to the output power of the master node, that the target slave node comprises the N first slave nodes; and connect the links between the master node and the N first slave nodes, to supply power to the N first slave nodes. (“According to an alternate embodiment of the present invention, each time a power port demands power, the power is supplied to the power port while the power budget monitoring circuit of the present invention operates to determine if the total power budget is exceeded. That is, each time a power port demands power, the power is supplied to the power port while the variable current source associated with the power port is activated to supply a portion of the current to be summed into current I.sub.spm. When the increasing current value of current I.sub.spm causes the voltage V.sub.spm to exceed the reference voltage V.sub.ref, the OverBudget signal is asserted to alert control circuitry in PSE 1 that the maximum power budget has been exceeded. PSE 1 can then act to terminate the power supply to the power port”, Burkland [37]) (“As each powered device 52A-D is connected to PSE 1 or as each powered device connected to PSE 1 demands power from the PSE, PSE 1 must determine if the total power demand is within its allowable power budget. The allowable power budget refers to the maximum power that the PSE is capable of supplying to the connected PDs”, Burkland [10]) (“PSE 1 includes multiple power ports for providing power to one or more Powered Devices (PDs). In the present illustration, PSE 1 includes 4 power ports for supporting up to four PDs 52A-D. In the present description, a power port of a PSE refers to a port of the PSE that supplies at least power to a network device connected thereto. The power is provided on a twisted wire pair of an Ethernet cable separate from the twisted wire pair carrying the data signals or on the same twisted wire pair that also carry the data signals.”, Burkland [9])
Pascal, Burkland, and Morris are analogous because they pertain to master and slave communication.
Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include power budgeting as described in Burkland into Pascal as modified by Morris. By modifying the method to include power budgeting as taught by Burkland, the benefits of minimized shutdown and reboot cycles (Pascal [page 14, line 7]), ensuring power budget is not exceeded (Burkland [9]), and improved communication efficiency (Morris [0025]) are achieved.
As to claim 26:
The combination of Pascal and Morris as described above does not explicitly teach:
The master node according to claim 22, wherein the computer instructions, when invoked by the at least one processor, further enable the master node to: determine, when a sum of the respective powers of each of the N first slave nodes is greater than the output power of the master node, that the target slave node comprises M first slave nodes, wherein 1≤M<N; and connect links between the master node and the M first slave nodes, to supply power to the M first slave nodes.
However, Burkland further teaches power budgeting which includes:
The master node according to claim 22, wherein the computer instructions, when invoked by the at least one processor, further enable the master node to: determine, when a sum of the respective powers of each of the N first slave nodes is greater than the output power of the master node, that the target slave node comprises M first slave nodes, wherein 1≤M<N; and connect links between the master node and the M first slave nodes, to supply power to the M first slave nodes. (“As each powered device 52A-D is connected to PSE 1 or as each powered device connected to PSE 1 demands power from the PSE, PSE 1 must determine if the total power demand is within its allowable power budget. The allowable power budget refers to the maximum power that the PSE is capable of supplying to the connected PDs. For instance, assuming that PSE 1 is already connected to and providing power for powered devices 52A, 52C and 52D, when powered device 52B initiates a power request from PSE 1, PSE 1 must determine whether it has sufficient power to supply powered device 52B, in addition to the power it is already supplying to powered devices 52A, 52C and 52D. PSE 1 will either supply power to powered device 52B if the total power budget is not exceeded or deny power to powered device 52B if the total power budget is exceeded”, Burkland [10]) (Examiner’s Note: PSE determines whether or not to provide power to a fourth slave based on whether the total power budget is exceeded or not. If the budget is exceeded, then only 3 slaves are powered)
Pascal, Burkland, and Morris are analogous because they pertain to master and slave communication.
Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include power budgeting as described in Burkland into Pascal as modified by Morris. By modifying the method to include power budgeting as taught by Burkland, the benefits of minimized shutdown and reboot cycles (Pascal [page 14, line 7]), ensuring power budget is not exceeded (Burkland [9]), and improved communication efficiency (Morris [0025]) are achieved.
As to claim 27:
The combination of Pascal and Morris as described above does not explicitly teach:
The master node according to claim 21, wherein the master node is further connected to a second slave node, and the second slave node is a slave node newly added to a system in which there is a first slave node from the N first slave nodes that is already powered; and the computer instructions, when invoked by the at least one processor, further enable the master node to: determine a remaining power of the master node; obtain a power of the second slave node; and supply power to the second slave node if the power of the second slave node is less than or equal to the remaining power.
However, Burkland further teaches power budgeting which includes:
The master node according to claim 21, wherein the master node is further connected to a second slave node, and the second slave node is a slave node newly added to a system in which there is a first slave node from the N first slave nodes that is already powered; and the computer instructions, when invoked by the at least one processor, further enable the master node to: determine a remaining power of the master node; obtain a power of the second slave node; and supply power to the second slave node if the power of the second slave node is less than or equal to the remaining power. (“As each powered device 52A-D is connected to PSE 1 or as each powered device connected to PSE 1 demands power from the PSE, PSE 1 must determine if the total power demand is within its allowable power budget. The allowable power budget refers to the maximum power that the PSE is capable of supplying to the connected PDs. For instance, assuming that PSE 1 is already connected to and providing power for powered devices 52A, 52C and 52D, when powered device 52B initiates a power request from PSE 1, PSE 1 must determine whether it has sufficient power to supply powered device 52B, in addition to the power it is already supplying to powered devices 52A, 52C and 52D. PSE 1 will either supply power to powered device 52B if the total power budget is not exceeded or deny power to powered device 52B if the total power budget is exceeded”, Burkland [10])
Pascal, Burkland, and Morris are analogous because they pertain to master and slave communication.
Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include power budgeting as described in Burkland into Pascal as modified by Morris. By modifying the method to include power budgeting as taught by Burkland, the benefits of minimized shutdown and reboot cycles (Pascal [page 14, line 7]), ensuring power budget is not exceeded (Burkland [9]), and improved communication efficiency (Morris [0025]) are achieved.
Claim(s) 28 is rejected under 35 U.S.C. 103 as being unpatentable over Pascal in view of Morris and Burkland, as applied to claim 27 above, and further in view of Bhagavathula et al. US 11604501 B2 (hereinafter “Bhagavathula”)
As to claim 28:
The combination of Pascal, Burkland, and Morris as described above does not explicitly teach:
The master node according to claim 27, wherein the computer instructions, when invoked by the at least one processor, further enable the master node to: perform power negotiation with the second slave node, to determine the power of the second slave node; or obtain the power of the second slave node from the second slave node.
However, Bhagavathula further teaches power negotiation which includes:
The master node according to claim 27, wherein the computer instructions, when invoked by the at least one processor, further enable the master node to: perform power negotiation with the second slave node, to determine the power of the second slave node; or obtain the power of the second slave node from the second slave node. (“The power distribution across each port of the number of ports may be controlled by a coordinated pair of a master control mechanism and a slave handler mechanism. The master control mechanism may maintain a record of the allocated power across various ports and available power, and may control the slave handler mechanism via a request-response communication interface. In this case, the slave handler mechanism may deliver power based on active power negotiation protocol out of the supported protocols and based on the control requests from the master control mechanism.”, Bhagavathula [22])
Pascal, Burkland, Bhagavathula, and Morris are analogous because they pertain to master and slave communication.
Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include power negotiation as described in Bhagavathula into Pascal as modified by Morris. By modifying the method to include power negotiation as taught by Bhagavathula, the benefits of minimized shutdown and reboot cycles (Pascal [page 14, line 7]), ensuring power budget is not exceeded (Burkland [9]), and improved communication efficiency (Morris [0025] and Bhagavathula [11]) are achieved.
Claim(s) 29 is rejected under 35 U.S.C. 103 as being unpatentable over Pascal in view of Morris, as applied to claim 22 above, and further in view of Rune US 20030081603 (hereinafter “Rune”)
As to claim 29:
The combination of Pascal and Morris as described above does not explicitly teach:
The master node according to claim 22, wherein the computer instructions, when invoked by the at least one processor, further enable the master node to: send a target packet to each of the N first slave nodes, wherein the target packet indicates a time period in which the master node is connected to each of the N first slave nodes, to enable the master node to be connected to one of the N first slave nodes in a same time period.
However, Rune further teaches time slot indication which includes:
The master node according to claim 22, wherein the computer instructions, when invoked by the at least one processor, further enable the master node to: send a target packet to each of the N first slave nodes, wherein the target packet indicates a time period in which the master node is connected to each of the N first slave nodes, to enable the master node to be connected to one of the N first slave nodes in a same time period. (“the predefined time slot can be based upon the AM_ADDR of the slave node and the clock of the master node. In accordance with this aspect, the master clock cycle can be divided into sub-cycles of, for example, 128 frames each, and each slave node is assigned a predefined time slot in each subcycle. The position of a particular slave node's predefined time slot in the subcycle can be defined by the AM_ADDR of the slave node, for example, by adding an offset to the beginning of the subcycle. The size of the offset can be dependent upon the AM_ADDR, for example, predefined time slot=(AM_ADDR-1)*Offs frames, wherein Offs is preferably 18 if the subcycle length is 128 frames.”, Rune [0079]) (FIG. 6, 7, and 10A-10D, Rune)
Pascal, Rune, and Morris are analogous because they pertain to master and slave communication.
Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include time slot indication as described in Rune into Pascal as modified by Morris. By modifying the method to include time slot indication as taught by Rune, the benefits of minimized shutdown and reboot cycles (Pascal [page 14, line 7]), improved information delivery (Rune [0079]), and improved communication efficiency (Morris [0025]) are achieved.
Claim(s) 37 is rejected under 35 U.S.C. 103 as being unpatentable over Pascal et al. GB 2587007 A (hereinafter “Pascal”) in view of Burkland et al. US 7865754 B2 (hereinafter “Burkland”)
As to claim 37:
Pascal as described above does not explicitly teach:
The power supply system according to claim 35, wherein the power supply system further comprises a second slave node, and the second slave node is a slave node newly added to the system in which there is a first slave node of the N first slave nodes that is already powered; and the instructions contained in the memory of the master node, when invoked, further cause the master node to: determine a remaining power of the master node; obtain a power of the second slave node; and supply power to the second slave node if the power of the second slave node is less than or equal to the remaining power.
However, Burkland further teaches power budgeting which includes:
The power supply system according to claim 35, wherein the power supply system further comprises a second slave node, and the second slave node is a slave node newly added to the system in which there is a first slave node of the N first slave nodes that is already powered; and the instructions contained in the memory of the master node, when invoked, further cause the master node to: determine a remaining power of the master node; obtain a power of the second slave node; and supply power to the second slave node if the power of the second slave node is less than or equal to the remaining power. (“As each powered device 52A-D is connected to PSE 1 or as each powered device connected to PSE 1 demands power from the PSE, PSE 1 must determine if the total power demand is within its allowable power budget. The allowable power budget refers to the maximum power that the PSE is capable of supplying to the connected PDs. For instance, assuming that PSE 1 is already connected to and providing power for powered devices 52A, 52C and 52D, when powered device 52B initiates a power request from PSE 1, PSE 1 must determine whether it has sufficient power to supply powered device 52B, in addition to the power it is already supplying to powered devices 52A, 52C and 52D. PSE 1 will either supply power to powered device 52B if the total power budget is not exceeded or deny power to powered device 52B if the total power budget is exceeded”, Burkland [10])
Pascal and Burkland are analogous because they pertain to master and slave communication.
Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include power budgeting as described in Burkland into Pascal. By modifying the method to include power budgeting as taught by Burkland, the benefits of minimized shutdown and reboot cycles (Pascal [page 14, line 7]) and ensuring power budget is not exceeded (Burkland [9]) are achieved.
Claim(s) 38 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Pascal et al. GB 2587007 A (hereinafter “Pascal”) in view of Bhagavathula et al. US 11604501 B2 (hereinafter “Bhagavathula”)
As to claim 38:
Pascal as described above does not explicitly teach:
The power supply system according to claim 35, wherein the instructions contained in the memory of the master node, when invoked, further cause the master node to: perform power negotiation with each of the N first slave nodes.
However, Bhagavathula further teaches power negotiation which includes:
The power supply system according to claim 35, wherein the instructions contained in the memory of the master node, when invoked, further cause the master node to: perform power negotiation with each of the N first slave nodes. (“The power distribution across each port of the number of ports may be controlled by a coordinated pair of a master control mechanism and a slave handler mechanism. The master control mechanism may maintain a record of the allocated power across various ports and available power, and may control the slave handler mechanism via a request-response communication interface. In this case, the slave handler mechanism may deliver power based on active power negotiation protocol out of the supported protocols and based on the control requests from the master control mechanism.”, Bhagavathula [22])
Pascal and Bhagavathula are analogous because they pertain to master and slave communication.
Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include power negotiation as described in Bhagavathula into Pascal. By modifying the method to include power negotiation as taught by Bhagavathula, the benefits of minimized shutdown and reboot cycles (Pascal [page 14, line 7]) and improved communication efficiency (Bhagavathula [11]) are achieved.
As to claim 39:
Pascal as described above does not explicitly teach:
The power supply system according to claim 38, wherein the instructions contained in the memory of the master node, when invoked, further cause the master node to: determine a power of each of the N first slave nodes based on a negotiation result of the power negotiation.
However, Bhagavathula further teaches power negotiation which includes:
The power supply system according to claim 38, wherein the instructions contained in the memory of the master node, when invoked, further cause the master node to: determine a power of each of the N first slave nodes based on a negotiation result of the power negotiation. (“The power distribution across each port of the number of ports may be controlled by a coordinated pair of a master control mechanism and a slave handler mechanism. The master control mechanism may maintain a record of the allocated power across various ports and available power, and may control the slave handler mechanism via a request-response communication interface. In this case, the slave handler mechanism may deliver power based on active power negotiation protocol out of the supported protocols and based on the control requests from the master control mechanism.”, Bhagavathula [22])
Pascal and Bhagavathula are analogous because they pertain to master and slave communication.
Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include power negotiation as described in Bhagavathula into Pascal. By modifying the method to include power negotiation as taught by Bhagavathula, the benefits of minimized shutdown and reboot cycles (Pascal [page 14, line 7]) and improved communication efficiency (Bhagavathula [11]) are achieved.
Claim(s) 40 is rejected under 35 U.S.C. 103 as being unpatentable over Pascal et al. GB 2587007 A (hereinafter “Pascal”) in view of Burkland et al. US 7865754 B2 (hereinafter “Burkland”)
As to claim 40:
Pascal as described above does not explicitly teach:
The power supply system according to claim 35, wherein the instructions contained in the memory of the master node, when invoked, further cause the master node to: send a target packet to each of the N first slave nodes, wherein the target packet indicates a time period in which the master node is connected to each of the N first slave nodes, to enable the master node to be connected to one of the N first slave nodes in a same time period.
However, Rune further teaches time slot indication which includes:
The power supply system according to claim 35, wherein the instructions contained in the memory of the master node, when invoked, further cause the master node to: send a target packet to each of the N first slave nodes, wherein the target packet indicates a time period in which the master node is connected to each of the N first slave nodes, to enable the master node to be connected to one of the N first slave nodes in a same time period. (“the predefined time slot can be based upon the AM_ADDR of the slave node and the clock of the master node. In accordance with this aspect, the master clock cycle can be divided into sub-cycles of, for example, 128 frames each, and each slave node is assigned a predefined time slot in each subcycle. The position of a particular slave node's predefined time slot in the subcycle can be defined by the AM_ADDR of the slave node, for example, by adding an offset to the beginning of the subcycle. The size of the offset can be dependent upon the AM_ADDR, for example, predefined time slot=(AM_ADDR-1)*Offs frames, wherein Offs is preferably 18 if the subcycle length is 128 frames.”, Rune [0079]) (FIG. 6, 7, and 10A-10D, Rune)
Pascal and Rune are analogous because they pertain to master and slave communication.
Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include time slot indication as described in Rune into Pascal. By modifying the method to include time slot indication as taught by Rune, the benefits of minimized shutdown and reboot cycles (Pascal [page 14, line 7]) and improved information delivery (Rune [0079]).
Conclusion
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/A.C.K./
Examiner
Art Unit 2471
/MOHAMMAD S ADHAMI/Primary Examiner, Art Unit 2471
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