Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al (US20080198671, “Wang”).
As to claim 1, 17, 20:
Wang teaches a system (system of circuitry; Fig. 1; 0017) comprising:
a set of memory components of a memory sub-system (host with processor and memory system; 0017, 0019; RAM; 0030), associated method of operation (0009, claims), and medium storage for storing instructions to perform the method (computer memory, such as RAM; 0017, 0019, 0030); and
at least one processing device operatively coupled to the set of memory components (write control logic, the at least one processing device being configured to perform operations comprising: receiving a request to store a set of data to the set of memory components (write control logic receive write requests; 0020-0024); determining whether the set of data corresponds to a periodic commit stream or other operations (interpret commit stream operation as a write operation; determine the command type from three possible command types; 0021, 0024); selecting one or more write cursors from a plurality of write cursors to associate with the set of data in response to determining whether the set of data corresponds to the periodic commit stream or the other operations (select write pointer based on command type; 0021, 0023, 0024); and programming the set of data to one or more of the set of memory components according to a data layout associated with the selected one or more write cursors (schedule command for execution based on write cursor, such as write event; 0040, 0041, 0023, 0024).
As to claim 2, 18:
Wang teaches a first write cursor of the plurality of write cursors corresponds to a first data layout, and wherein a second write cursor of the plurality of write cursors corresponds to a second data layout (different data type have different assigned layout/section in queue, write event indicate the data type; 0009, 0032).
As to claim 3, 19:
Wang teaches the first write cursor is selected in response to determining that the set of data corresponds to the periodic commit stream, and wherein the second write cursor is selected in response to determining that the set of data corresponds to the other operation (select write pointer based on command type; 0021, 0023, 0024).
As to claim 6:
Wang teaches the operations comprising: tracking patterns of discard commands received from a host to determine whether the set of data corresponds to the periodic commit stream or the other operations (track read/write events, determine data associated with command type, select write pointer based on command type; 0024).
Allowable Subject Matter
Claims 4, 5, and 7-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 4, the prior art does not further suggest the system of claim 2, wherein the first write cursor groups a first collection of data on the one or more of the set of memory components together into a first set of block stripes, and wherein the second write cursor stores a second collection of data on the one or more of the set of memory components in a second set of block stripes.
As to claim 5, the prior art does not further suggest the system of claim 1, wherein the periodic commit stream corresponds to a circular buffer maintained by a host, the host invalidating data associated with the circular buffer in response to the other operation.
As to claim 7, the prior art does not further suggest the system of claim 6, wherein each discard command comprises an identification of a set of logical block addresses (LBAs) that are invalid.
As to claim 8, the prior art does not further suggest the system of claim 6, the operations comprising: dividing an entire logical address space associated with the set of memory components into a plurality of regions, each region of the plurality of regions representing a different portion of the logical address space; and storing a table that associates each region of the plurality of regions with a respective discard counter.
Claims 9-16 are allowable for incorporating the limitations of claim 8, and further limitations.
Conclusion
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/THAN NGUYEN/Primary Examiner, Art Unit 2138