CTNF 18/970,325 CTNF 90082 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-3 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US Pub. 20170315415, Yang) in view of Nomura (US Pub. 20130235294) . As per claim 1, Yang teaches (in figures 1-2B) an electronic device, comprising: a first substrate (substrate 118); a second substrate (substrate 136) disposed opposite to the first substrate; a data line (data line 106) disposed on the first substrate and extending along a first direction (direction A2); a scan line (scan line 104) disposed on the first substrate, wherein the scan line has an extension part (portion of scan line 104 other than gate electrode 116) extending along a second direction (direction A1) and a gate electrode (gate electrode 116) extending along the first direction (direction A2), the gate electrode has an arc-shaped connection side (see figure 2A) connecting with the extension part;, and wherein the data line and the gate electrode overlap with each other. Yang does not teach a first spacer disposed on the first substrate; and a second spacer disposed between the first spacer and the second substrate, wherein a length of the second spacer is greater than a width of the gate electrode along the second direction and wherein the first spacer, the second spacer, the data line, and the gate electrode overlap with each other, and the first spacer crosses the gate electrode of the scan line and the extension part of the scan line along the first direction. Nomura teaches (in figures 3-6) providing a first spacer (spacer section 67) on the first substrate (transparent substrate 21); and a second spacer (spacer section 74) disposed between the first spacer (spacer section 67) and a second substrate (transparent substate 31), wherein the second spacer (spacer section 74), a data line (source line 63), and a scan line (gate line 61) overlap with each other (see figure 3) at the intersection of the data line (source line 63) and the scan line (gate line 61), and the first spacer (spacer section 67) covers the entire width of the scan line along the first direction (Y direction) (see figure 3) in order to maintain the cell gap while preventing damage to the display (paragraphs 75 and 91). Additionally, Nomura teaches that the lengths and the widths of the first spacer (spacer section 67) and the second spacer (spacer section 74) are result effective variables in that if the lengths are too short the spacers are more likely to become misaligned and damage the opposite substrate and if the widths are too large the light-shielding region would need to be increased lowering transmittance (paragraphs 89-92) additionally if the widths are to small the strength of the spacers will decrease. As it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (See MPEP § 2144.05 (II) (A) and (B)) it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the spacers from Nomura in the device of Yang and set the lengths and widths of the spacers such that a length of the second spacer is greater than a width of the gate electrode along the second direction and the first spacer crosses the gate electrode of the scan line and the extension part of the scan line along the first direction in order to maintain the cell gap while preventing damage and a lowering of transmittance of the display. As per claim 2, Yang teaches (in figures 1-2B) a drain electrode (drain electrode 114) disposed on the first substrate (substrate 118) and having a protruding part (extending portion 114A). As per claim 3, Yang teaches (in figures 1-2B) that the protruding part of the drain electrode (extending portion 114A) is adjacent to the data line (data line 106), and in the second direction (direction A1), a minimum distance between the protruding part of the drain electrode and the data line is greater than 0 (see figure 2A). Yang does not teach that a minimum distance between the protruding part of the drain electrode and the data line is less than a maximum width of the first spacer. However, Nomura teaches that the width of the first spacer (spacer section 67) is result effective variables in that if the width is too large the light-shielding region would need to be increased lowering transmittance (paragraphs 89-92) additionally if the width is to small the strength of the spacers will decrease. As it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (See MPEP § 2144.05 (II) (A) and (B)) it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to set the width of the first spacer such that a minimum distance between the protruding part of the drain electrode and the data line is less than a maximum width of the first spacer in order to prevent damage and a lowering of transmittance of the display. As per claim 5, Yang teaches (in figures 1-2B) that the drain electrode (drain electrode 114) further comprises a main part (portion of drain electrode excluding extending portion 114A) extending along the second direction (direction A1) and, the protruding part of the drain electrode (extending portion 114A) extends along the first direction (direction A2), and the protruding part does not overlap with the main part along the second direction (see figure 2A). As per claim 6, Yang teaches (in figures 1-2B) a semiconductor layer (semiconductor layer 152) disposed on the first substrate (substrate 118), wherein the semiconductor layer extends along the first direction (direction A2)(see figure 2A). As per claim 7, Yang teaches (in figures 1-2B) an electronic device, comprising: a substrate (substrate 118); a metal element (data line 106) disposed on the substrate (substrate 118) and extending along a first direction (direction A2); a scan line (scan line 104) disposed on the substrate (substrate 118), wherein the scan line has an extension part (portion of scan line 104 other than gate electrode 116) extending along a second direction (direction A1) and a protruding part (gate electrode 116) extending along the first direction (direction A2) different from the second direction (direction A1), the protruding part has an arc-shaped connection side connecting with the extension part (see figure 2A); wherein in a top view, the protruding part of the scan line (gate electrode 116), and the metal element (data line 106) overlap with each other. Yang does not teach a spacer disposed on the substrate wherein in a top view, the spacer, the protruding part of the scan line, and the metal element overlapping with each other. However, Nomura teaches (in figures 3-6) providing a spacer (spacer sections 67 and 74) on the first substrate (transparent substrate 21); wherein in a top view the spacer (spacer sections 67 and 74), a metal element (source line 63), and a scan line (gate line 61 and gate electrode 61a) overlap with each other (see figure 3) at the intersection of the metal element (source line 63) and the scan line (gate line 61) (see figure 3) in order to maintain the cell gap while preventing damage to the display (paragraphs 75 and 91). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the spacers from Nomura in the device of Yang in order to maintain the cell gap while preventing damage and a lowering of transmittance of the display. As per claim 8, Yang in view of Nomura does not explicitly teach a width of the spacer is greater than a width of the protruding part of the scan line along the second direction. However, Nomura teaches that the lengths and the widths of the spacer (spacer sections 67 and 74) are result effective variables in that if the lengths are too short the spacer sections are more likely to become misaligned and damage the opposite substrate and if the widths are too large the light-shielding region would need to be increased lowering transmittance (paragraphs 89-92) additionally if the widths are too small the strength of the spacers will decrease. As it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (See MPEP § 2144.05 (II) (A) and (B)) it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the spacers from Nomura in the device of Yang and set the lengths and widths of the spacer such that a width of the spacer is greater than the protruding part of the scan line along the second direction in order to maintain the cell gap while preventing damage and a lowering of transmittance of the display. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER P GROSS whose telephone number is (571)272-5660. The examiner can normally be reached Monday-Friday 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth can be reached at (571) 272-9791. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEXANDER P GROSS/Primary Examiner, Art Unit 2871 Application/Control Number: 18/970,325 Page 2 Art Unit: 2871 Application/Control Number: 18/970,325 Page 3 Art Unit: 2871 Application/Control Number: 18/970,325 Page 4 Art Unit: 2871 Application/Control Number: 18/970,325 Page 5 Art Unit: 2871 Application/Control Number: 18/970,325 Page 6 Art Unit: 2871 Application/Control Number: 18/970,325 Page 7 Art Unit: 2871
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