Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 05 December 2024 for application number 18/970,368. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1 – 20 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 21 December 2023 (Provisional 63/613,328).
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3, 6, 7, 10, 11, 13, 14, 16, 17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Akavaram et al. [hereafter as Akavaram], US Pub. No. 2024/0319913 A1 in view of Earhart [hereafter as Earhart], US Pub. No. 2016/0274970 A1.
As per claim 1, Akavaram discloses a memory system comprising:
one or more memory devices arranged having logical units, each logical unit to hold data of the logical units [“In some aspects, the main storage can be divided into multiple logical partitions or volumes, each of which can be assigned a unique logical unit number (LUN) (e.g., LUN 210a, 210b, . . . , and 210n shown in FIG. 2). The host (e.g., host 102) can access each LUN independently, treating each LUN as a separate storage device.”] [para. 0030];
one or more buffers structured to hold data using a first level-cell mode of data storage [“It is faster to write new data to the write buffer than the main storage because the write buffer is configured with faster memory (e.g., SLC memory) than the main storage.”] [para. 0036];
an interface [“In some aspects, the storage device 104 may be configured to provide a write buffer 114 to support a boosted write function (e.g., a turbo write) to increase write speed or throughput of the storage device 104. For example, the host 102 can send commands to the memory controller 110 via the interface 108 to enable or disable the boosted write function.”] [para. 0026] arranged to:
direct data from the first set of the logical units to the one or more buffers [“In some aspects, the main storage can be divided into multiple LUNs (e.g., LUNs 306a, 306b, . . . , and 306n shown in FIG. 3). In this example, each LUN can be associated with a dedicated write buffer.”] [para. 0031];
direct data from the second set of the logical units to a storage area of the memory system by bypassing the one or more buffers, the storage area having a multi-level cell (MLC) mode of data storage, the MLC mode of data storage being a higher level storage mode than the first level-cell mode of data storage of the one or more buffers [“At 610, if a buffer flush operation is in progress in the first write buffer, the host can send a command to the storage device to write the new data to a second write buffer (e.g., a secondary write buffer), bypassing the primary write buffer (e.g., first write buffer).”] [para. 0045] [“The flash memory can provide a main storage for user data, for example, using multi-level cell (MLC) or triple-level cell (TLC) memory.”] [para. 0021] [“It is faster to write new data to the write buffer than the main storage because the write buffer is configured with faster memory (e.g., SLC memory) than the main storage.”] [para. 0036].
However, Akavaram does not explicitly disclose data of a data type different from data types in other logical units;
configure a first set of the logical units to a first performance setting;
configure a second set of the logical units to a second performance setting.
Earhart teaches data of a data type different from data types in other logical units [“As these parameters are set on a per partition basis, it enables straightforward implementation of multiple features such as SLC caching, mixing data security levels, support of multiple types of virtual devices and volumes simultaneously, and supporting different levels of protection based on data type or source as just a few examples.”] [para. 0073] [para. 0100];
configure a first set of the logical units to a first performance setting [“As these parameters are set on a per partition basis, it enables straightforward implementation of multiple features such as SLC caching, mixing data security levels, support of multiple types of virtual devices and volumes simultaneously, and supporting different levels of protection based on data type or source as just a few examples.”] [para. 0073] [paras. 0064 – 0072];
configure a second set of the logical units to a second performance setting [“As these parameters are set on a per partition basis, it enables straightforward implementation of multiple features such as SLC caching, mixing data security levels, support of multiple types of virtual devices and volumes simultaneously, and supporting different levels of protection based on data type or source as just a few examples.”] [para. 0073] [paras. 0064 – 0072].
Akavaram and Earhart are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Akavaram with Earhart in order to modify Akavaram for “data of a data type different from data types in other logical units;
configure a first set of the logical units to a first performance setting;
configure a second set of the logical units to a second performance setting” as taught by Earhart. One of ordinary skill in the art would be motivated to combine Akavaram with Earhart before the effective filing date of the claimed invention to improve a system by providing “for efficient use of memory within the storage array and offers performance improvements including the availability of multiple, bi-directional data streams that are mapped to different partitions within storage system.” [Earhart, para. 0025].
Claim 10 is rejected with like reasoning as claim 1 above, except for the following remaining claim limitations:
a processing device to execute instructions, stored in the memory system, to cause the memory system to perform operations, the operations including;
partitioning the one or more memory devices
a first attribute assigned to the first set;
a second attribute assigned to the second set.
Akavaram discloses a processing device to execute instructions, stored in the memory system, to cause the memory system to perform operations, the operations [“program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein.”] [para. 0020] including;
partitioning the one or more memory devices [“the main storage can be divided into multiple logical partitions”] [para. 0030].
Earhart teaches a first attribute assigned to the first set [“These partitions may be configured individually with a desired partition size, data block size, storage density, physical memory attributes, protection attributes, security level, quality of service requirements, data type, data source, data stream attributes, and the like.”] [para. 0025] [para. 0026];
a second attribute assigned to the second set [“These partitions may be configured individually with a desired partition size, data block size, storage density, physical memory attributes, protection attributes, security level, quality of service requirements, data type, data source, data stream attributes, and the like.”] [para. 0025] [para. 0026].
Claim 16 is rejected with like reasoning as claims 1 and 10 above.
As per claim 2, Akavaram in view of Earhart discloses the memory system of claim 1, Akavaram discloses wherein the interface is arranged to flush data in the one or more buffers to the storage area [“When a write buffer is full, the storage device can perform a write buffer flush operation to move the data in the write buffer to the main storage.”] [para. 0021].
Claims 11 and 19 are rejected with like reasoning.
As per claim 3, Akavaram in view of Earhart discloses the memory system of claim 1, Akavaram discloses wherein the one or more buffers is a shared buffer [“all LUNs can share the write buffers.”] [para. 0030].
As per claim 6, Akavaram in view of Earhart discloses the memory system of claim 1, Akavaram discloses wherein the first level-cell mode of data storage is a single-level cell (SLC) mode of data storage [“write buffers can be configured as SLC buffers”] [para. 0031].
Claim 13 is rejected with like reasoning.
As per claim 7, Akavaram in view of Earhart discloses the memory system of claim 1, Akavaram discloses wherein the MLC mode of data storage is a triple-level cell (TLC) mode of data storage [“the main storage may be implemented by MLC or TLC memory.”] [para. 0049].
Claim 14 is rejected with like reasoning.
As per claim 17, Akavaram in view of Earhart discloses the method of claim 16, Earhart teaches wherein the method includes partitioning one or more memory devices of the memory system to include multiple sets of logical units, each logical unit to hold data of a data type different from data types in other logical units of the partitioned logical units [“FIG. 11 illustrates an example sequential writing process. Write requests to the storage array are mapped to a partition. Write data can be steered to different partitions based on data type, host ID, or data source.”] [para. 0100].
Claim 20 is rejected with like reasoning as claims 13 and 14 above.
Claims 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Akavaram et al. [hereafter as Akavaram], US Pub. No. 2024/0319913 A1 in view of Earhart [hereafter as Earhart], US Pub. No. 2016/0274970 A1 as applied to claims 1 and 16 above, and further in view of Yeh [hereafter as Yeh], US Patent No. 9,613,705 B1.
As per claim 4, Akavaram in view of Earhart discloses the memory system of claim 1, however, Akavaram and Earhart do not explicitly disclose wherein the second performance setting is a setting identifying that data is to be directed to the storage area avoiding use of the one or more buffers.
Yeh teaches wherein the second performance setting is a setting identifying that data is to be directed to the storage area avoiding use of the one or more buffers [“Accordingly, even if aforesaid at least one part of the first data is directly stored into the storage area 602 while skipping the buffer area 601”] [col. 13, lines 35-37].
Akavaram, Earhart, and Yeh are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Akavaram and Earhart with Yeh in order to modify Akavaram and Earhart “wherein the second performance setting is a setting identifying that data is to be directed to the storage area avoiding use of the one or more buffers” as taught by Yeh. One of ordinary skill in the art would be motivated to combine Akavaram and Earhart with Yeh before the effective filing date of the claimed invention to improve a system by providing where “the writing speed decreased by the fully written buffer area may be improved.” [Yeh, Abstract].
As per claim 18, Akavaram in view of Earhart discloses the method of claim 16, however Akavaram and Earhart do not explicitly disclose wherein the method includes:
configuring the first set of logical units to a first performance setting; and
configuring the second set of logical units to a second performance setting.
Yeh teaches wherein the method includes:
configuring the first set of logical units to a first performance setting [“The first physical units are configured initially to be programmed based on a first programming mode. The second physical units are configured initially to be programmed based on a second programming mode.”] [col. 2, lines 6-9]; and
configuring the second set of logical units to a second performance setting [“The first physical units are configured initially to be programmed based on a first programming mode. The second physical units are configured initially to be programmed based on a second programming mode.”] [col. 2, lines 6-9].
Akavaram, Earhart, and Yeh are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Akavaram and Earhart with Yeh in order to modify Akavaram and Earhart “wherein the method includes:
configuring the first set of logical units to a first performance setting; and
configuring the second set of logical units to a second performance setting” as taught by Yeh. One of ordinary skill in the art would be motivated to combine Akavaram and Earhart with Yeh before the effective filing date of the claimed invention to improve a system by providing where “the writing speed decreased by the fully written buffer area may be improved.” [Yeh, Abstract].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Akavaram et al. [hereafter as Akavaram], US Pub. No. 2024/0319913 A1 in view of Earhart [hereafter as Earhart], US Pub. No. 2016/0274970 A1 as applied to claim 1 above, and further in view of Mehra et al. [hereafter as Mehra], US Pub. No. 2013/0067191 A1.
As per claim 5, Akavaram in view of Earhart discloses the memory system of claim 1, Akavaram discloses data is to be directed to the one or more buffers [“It is faster to write new data to the write buffer than the main storage because the write buffer is configured with faster memory (e.g., SLC memory) than the main storage.”] [para. 0036].
However, Akavaram and Earhart do not explicitly disclose wherein the first performance setting is a setting identifying that data is to be directed.
Mehra teaches wherein the first performance setting is a setting identifying that data is to be directed [“storage devices 102 of different sizes and/or different performance characteristics (e.g., the first and second storage devices 102 in FIG. 3 may have different total capacities generated by different manufacturers with different storage controllers). Additionally, as further compared with the exemplary scenario 200 illustrated in FIG. 2, the logical disk manager database 306 may enable the coexistence of a pool 202 with other partitions 104 that are not included in the pool 202 (e.g., the first partition 104 on the first storage device 102), and that may be accessible to and usable by systems (e.g., storage controllers and software) that are not capable of using the logical disk manager database 306.”] [para. 0028] [“The segregation of the capacity of the storage device into volumes may provide various advantages (e.g., different partitions may isolate different groups of data; may be used to manifest different volumes; or may be differently organized to store different types of data, and/or to store data for access on different computers or devices that utilize different types of partitions).”] [para. 0021].
Akavaram, Earhart, and Mehra are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Akavaram and Earhart with Mehra in order to modify Akavaram and Earhart “wherein the first performance setting is a setting identifying that data is to be directed” as taught by Mehra. One of ordinary skill in the art would be motivated to combine Akavaram and Earhart with Mehra before the effective filing date of the claimed invention to improve a system by providing for the ability where “In these and other ways, extents … may be allocated to spaces … to enable various features such as improved performance and thin provisioning.” [Mehra, para. 0051].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Akavaram et al. [hereafter as Akavaram], US Pub. No. 2024/0319913 A1 in view of Earhart [hereafter as Earhart], US Pub. No. 2016/0274970 A1 as applied to claim 1 above, and further in view of Emori [hereafter as Emori], US Pub. No. 2009/0193246 A1.
As per claim 8, Akavaram in view of Earhart discloses the memory system of claim 1, Earhart teaches wherein the first set of the logical units has data types including boot data [Data type and source—e.g. system, host, local array, network, etc.], operating system data [Data type and source—e.g. system], host, local array, network, etc.], and over-the-air data [Data type and source—e.g. … network, etc.] [“There are many partition parameters to allow the controller to he optimized to many storage arrays and hosts. The categories of parameters are: [0065] Data block size. [0066] Physical storage cell density—e.g. SLC (Single Level Cell MLC (Multi Level Cell), TLC (Triple Level Cell), etc. [0067] Protection—number of codeword levels, codeword sizes, ECC type and overhead, etc. [0068] Security—type of encryption, key and password handling, access rights, and digital rights management attributes. [0069] Quality of Service—different priorities of traffic, support of isochronous streams, etc. [0070] Data type and source—e.g. system, host, local array, network, etc. [0071] Physical—number of data block stripes, number of data blocks per data block stripe, location of data blocks in the partition. [0072] Data stream definition—interface type (e.g. fixed blocks, stream, bulk USB, etc.), file/data format (e.g. host block definition, file system awareness, etc.), interface source—for controllers with multiple active interfaces, etc.”] [paras. 0064 – 0071].
However, Akavaram and Earhart do not explicitly disclose map data, speech data, application data.
Emori teaches map data, speech data, application data [“In the partition #1, map data used by the navigation application and CDDB used by the audio application are stored. In the partition #2, an audio file used by the audio application and telephone book data used by the telematics application are stored. In the partition #3, maintenance data not directly used by the above-described applications, such as backup data are stored. In the partition #4, shared resource data such as images shared for building a GUI by the above-described applications are stored. In the partition #5, navigation state data used by the navigation application are stored.”] [para. 0031] [“…various data and speech are transmitted/received to/from the person.”] [para. 0035].
Akavaram, Earhart, and Emori are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Akavaram and Earhart with Emori in order to modify Akavaram and Earhart for “map data, speech data, application data” as taught by Emori. One of ordinary skill in the art would be motivated to combine Akavaram and Earhart with Emori before the effective filing date of the claimed invention to improve a system by providing for the ability “to reduce the length of time required for completing the start-up of the application.” [Emori, para. 0017].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Akavaram et al. [hereafter as Akavaram], US Pub. No. 2024/0319913 A1 in view of Earhart [hereafter as Earhart], US Pub. No. 2016/0274970 A1 as applied to claim 10 above, and further in view of Yu et al. [hereafter as Yu], US Pub. No. 2011/0066818 A1.
As per claim 9, Akavaram in view of Earhart discloses the memory system of claim 1, however Akavaram and Earhart do not explicitly disclose wherein the second set of the logical units includes a logical unit containing data video recorder data type.
Yu teaches wherein the second set of the logical units includes a logical unit containing data video recorder data type [“Additionally, the memory management circuit 1046 sets the second partition for storing data belonging to an video file type, and sets the output flow rate limit of the second partition as 900 KB per second.”] [para. 0061].
Akavaram, Earhart, and Yu are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Akavaram and Earhart with Yu in order to modify Akavaram and Earhart “wherein the second set of the logical units includes a logical unit containing data video recorder data type” as taught by Yu. One of ordinary skill in the art would be motivated to combine Akavaram and Earhart with Yu before the effective filing date of the claimed invention to improve a system by providing for the ability “to prevent the read data from being copied to the host or slow down the speed of copying the read data to the host”. [Yu, Abstract].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Akavaram et al. [hereafter as Akavaram], US Pub. No. 2024/0319913 A1 in view of Earhart [hereafter as Earhart], US Pub. No. 2016/0274970 A1 as applied to claim 10 above, and further in view of Tanpairoj et al. [hereafter as Tanpairoj], US Pub. No. 2021/0200700 A1.
As per claim 15, Akavaram in view of Earhart discloses the memory system of claim 10, however Akavaram and Earhart do not explicitly disclose wherein the memory system is structured in an in-vehicle infotainment system.
Tanpairoj teaches wherein the memory system is structured in an in-vehicle infotainment system [“FIG. 10 shows an environment 1000 including an example electronic device 1001 having a host device 1010 and a memory system 1020 (e.g., memory system 110) as part of one or more apparatuses 1030-1050. Apparatuses include any device that may include an electronic device, such as electronic device 1001. The electronic device 1001 may be any device capable of executing instructions (sequential or otherwise). Example apparatuses include a vehicle 1030 (e.g., as part of an infotainment system, a control system, or the like), a drone 1050 (e.g., as part of a control system), furniture or appliances 1040 (e.g., as part of a sensor system, an entertainment or infotainment system), or the like. In other examples, although not shown, apparatuses may include aeronautical, marine, Internet of Things (IOT), and other devices.”] [para. 0073].
Akavaram, Earhart, and Tanpairoj are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Akavaram and Earhart with Tanpairoj in order to modify Akavaram and Earhart “wherein the memory system is structured in an in-vehicle infotainment system” as taught by Tanpairoj. One of ordinary skill in the art would be motivated to combine Akavaram and Earhart with Tanpairoj before the effective filing date of the claimed invention to improve a system by providing for the ability for “monitoring communications from a host device for a notification that a battery of the host device has entered a charging state and performing a background operation of the memory device responsive to receiving this notification… so that impact on performance and battery life will not be noticed by the user.” [Tanpairoj, Abstract and para. 0019].
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 20 have received a first action on the merits and are subject of a first action non-final. Claim 1 – 11 and 13 – 20 are rejected under a 103 rejection.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected based claim, but is considered as containing allowable subject matter. This claim would be allowable if rewritten or amended to include all of the limitations of the base claim and any intervening claims in independent form.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 12 the prior art of record, neither anticipates, nor renders obvious the first attribute assigned to the first set of logical units includes a burst write performance and the second attribute assigned to the second set of logical units includes a lifetime performance.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD WADDY JR whose telephone number is (571)272-5156. The examiner can normally be reached M-Th 8am-5pm.
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/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135