Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) filed on 01/29/2025 and 09/15/2025 has/have been considered by the Examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8, 10, 11-17, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lewis (US 20220156075 A1).
As to claim 1, Lewis teaches a method, comprising:
performing fault detection on a plurality of cores of a processor to determine a target core that is faulty, the target core being one of the plurality of cores (see paragraph 0089, disclosing monitoring cores and determining that one of the cores is stuck);
updating, based on a target task executed by the target core, tasks executed by the plurality of cores, to enable a core other than the target core in the plurality of cores to execute the target task (see Fig. 2, Fig. 6, and corresponding text and paragraphs 0090-095, disclosing disabling a stuck core and moving threads from the stuck core to another core); and
controlling the core other than the target core in the plurality of cores to execute an updated task, and bringing the target core offline (see Fig. 2, Fig. 6, and corresponding text and paragraphs 0090-095, disclosing disabling a stuck core and moving threads from the stuck core to another core and continuing execution of the thread on another core).
As to claim 2, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) wherein updating, based on the target task executed by the target core, the tasks executed by the plurality of cores, to enable the core other than the target core in the plurality of cores to execute the target task comprises:
updating, based on the target task, core allocation information to indicate that the core other than the target core is executing the target task, wherein the core allocation information indicates the plurality of cores and the tasks executed by the plurality of cores (see figs. 4-6, disclosing tables that represent information in core memories that indicate threads and tasks that are executed in the different cores); and
controlling the core other than the target core in the plurality of cores to execute the updated task, and bringing the target core offline comprises:
controlling the core other than the target core in the plurality of cores to execute the updated task based on the updated core allocation information, and bringing the target core offline (see Fig. 2, Fig. 6, and corresponding text and paragraphs 0090-095, disclosing disabling a stuck core and copying memory contents/moving threads from the stuck core to another core and continuing execution of the thread on another core).
As to claim 3, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) controlling the core other than the target core in the plurality of cores to execute the updated task, and bringing the target core offline comprises:
controlling the plurality of cores to end current tasks, controlling the core other than the target core in the plurality of cores to execute the updated task, and bringing the target core offline (see paragraphs 0078 0079, disclosing halting threads on a stuck core and pausing the core to which memory contents are to be copied and see Fig. 2, Fig. 6, and corresponding text and paragraphs 0090-095, disclosing disabling a stuck core and copying memory contents/moving threads from the stuck core to another core and continuing execution of the thread on another core).
As to claim 4, the reference(s) teach(es) claim 2 as detailed above. It/they further teach(es) updating, based on the target task, the core allocation information to indicate that the core other than the target core is executing the target task comprises: determining, based on the core allocation information, a first core, other than the target core, from the plurality of cores; and updating, based on the first core and the target task, the core allocation information to indicate that the target task is executed by the first core (see paragraphs 0092-0093, disclosing identifying an idle core (the examiner interprets that some information indicates an idle state such as having no instructions in an instruction cache as in paragraph 0060 and also disclosing supervising unit tracking priority of assigned threads selecting a replacement core with lower priority threads than the stuck unit; the examiner interprets there is some information indicating that priority).
As to claim 5, the reference(s) teach(es) claim 2 as detailed above. It/they further teach(es) updating, based on the target task, the core allocation information to indicate that the core other than the target core is executing the target task comprises: determining, based on the core allocation information, a second core from a target core group; and updating, based on the second core and the target task, the core allocation information to indicate that the target task is executed by the second core, and updating an execution status, in the core allocation information, of a second task executed by the second core to non-execution status (see paragraph 0093, disclosing halting execution of lower priority threads in a core to use as a replacement for the faulty core’s higher priority threads).
As to claim 8, the reference(s) teach(es) claim 2 as detailed above. It/they further teach(es) updating, based on the target task, the core allocation information to indicate that the core other than the target core is executing the target task comprises: when the target core belongs to a target core group, updating an execution status of the target task in the core allocation information to non-execution status (see paragraphs 0090 and 0094, disclosing setting a bit in a status register to indicate a core is stuck or setting a bit to disable instruction execution for threads).
As to claim 10, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) performing fault detection on the plurality of cores of the processor to determine the target core that is faulty comprises: testing at least one performance indicator for each of the plurality of cores, to obtain second fault detection results of the plurality of cores, wherein the second fault detection results indicates a test result corresponding to the at least one performance indicator of the target core (see paragraph 0060, disclosing determining that instructions are not committing when a counter reaches a threshold and storing information in an error register); and determining, when the second fault detection results of the target core indicates that the test result corresponding to the at least one performance indicator of the target core is inconsistent with a target result, that the target core is faulty (see claim 7, paragraph 0062, 0089, 0090 and 0105, disclosing a supervisor that reads the status register to determine the error in the core).
As to claim 11, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) updating, based on the target task executed by the target core, the tasks executed by the plurality of cores, to enable the core other than the target core in the plurality of cores to execute the target task comprises: updating, based on the target task executed by the target core, when a quantity of offline cores is less than an offline quantity threshold, the tasks executed by the plurality of cores, to enable the core other than the target core in the plurality of cores to execute the target task (see paragraph 0093, disclosing that when no idle cores are available, selecting a core with lower priorities as a replacement core and shuffling threads between cores.)
As to claim 12, Lewis teaches computing device comprising at least one processor and a memory, the at least one processor comprising a plurality of cores, the plurality of cores including a target core (see fig. 2 and corresponding text), and the memory storing a computer program that, when executed by the at least one processor, causes the computing device to perform:
updating, based on a target task executed by the target core, tasks executed by the plurality of cores, to enable a core other than the target core in the plurality of cores to execute the target task (see Fig. 2, Fig. 6, and corresponding text and paragraphs 0090-095, disclosing disabling a stuck core and moving threads from the stuck core to another core); and
controlling the core other than the target core in the plurality of cores to execute an updated task, and bringing the target core offline (see Fig. 2, Fig. 6, and corresponding text and paragraphs 0090-095, disclosing disabling a stuck core and copying memory contents/moving threads from the stuck core to another core and continuing execution of the thread on another core).
As to claim 13, the reference(s) teach(es) claim 12 as detailed above. It/they further teach(es) updating, based on the target task, core allocation information to indicate that the core other than the target core is executing the target task, wherein the core allocation information indicates the plurality of cores and the tasks executed by the plurality of cores (see figs. 4-6, disclosing tables that represent information in core memories that indicate threads and tasks that are executed in the different cores); and
controlling the core other than the target core in the plurality of cores to execute an updated task, and bringing the target core offline comprises: controlling the core other than the target core in the plurality of cores to execute the updated task based on the updated core allocation information, and bringing the target core offline (see Fig. 2, Fig. 6, and corresponding text and paragraphs 0090-095, disclosing disabling a stuck core and copying memory contents/moving threads from the stuck core to another core and continuing execution of the thread on another core).
As to claim 14, the reference(s) teach(es) claim 12 as detailed above. It/they further teach(es) the at least one processor is configured to perform: controlling the plurality of cores to end current tasks, controlling the core other than the target core in the plurality of cores to execute the updated task, and bringing the target core offline (see paragraphs 0078 0079, disclosing halting threads on a stuck core and pausing the core to which memory contents are to be copied and see Fig. 2, Fig. 6, and corresponding text and paragraphs 0090-095, disclosing disabling a stuck core and copying memory contents/moving threads from the stuck core to another core and continuing execution of the thread on another core).
As to claim 15, the reference(s) teach(es) claim 13 as detailed above. It/they further teach(es) the at least one processor is configured to perform: determining, based on the core allocation information, a first core other than the target core, from the plurality of cores; and updating, based on the first core and the target task, the core allocation information to indicate that the target task is executed by the first core (see paragraphs 0092-0093, disclosing identifying an idle core (the examiner interprets that some information indicates an idle state such as having no instructions in an instruction cache as in paragraph 0060 and also disclosing supervising unit tracking priority of assigned threads selecting a replacement core with lower priority threads than the stuck unit; the examiner interprets there is some information indicating that priority).
As to claim 16, the reference(s) teach(es) claim 13 as detailed above. It/they further teach(es)the at least one processor is configured to perform: determining, based on the core allocation information, a second core from a target core group; and updating, based on the second core and the target task, the core allocation information to indicate that the target task is executed by the second core, and updating an execution status, in the core allocation information, of a second task executed by the second core to non-execution status (see paragraph 0093, disclosing halting execution of lower priority threads in a core to use as a replacement for the faulty core’s higher priority threads).
As to claim 17, the reference(s) teach(es) claim 13 as detailed above. It/they further teach(es) the at least one processor is configured to perform when the target core belongs to a target core group, updating an execution status of the target task in the core allocation information to non-execution status. (see paragraphs 0090 and 0094, disclosing setting a bit in a status register to indicate a core is stuck or setting a bit to disable instruction execution for threads).
As to claim 19, the reference(s) teach(es) claim 12 as detailed above. It/they further teach(es) the at least one processor is configured to perform testing at least one performance indicator for each of the plurality of cores, to obtain second fault detection results of the plurality of cores, wherein the second fault detection results indicates a test result corresponding to the at least one performance indicator of the target core; and determining, when the second fault detection results of the target core indicates that the test result corresponding to the at least one performance indicator of the target core is inconsistent with a target result, that the target core is faulty. (see paragraph 0060, disclosing determining that instructions are not committing when a counter reaches a threshold and storing information in an error register); and determining, when the second fault detection results of the target core indicates that the test result corresponding to the at least one performance indicator of the target core is inconsistent with a target result, that the target core is faulty (see claim 7, paragraph 0062, 0089, 0090 and 0105, disclosing a supervisor that reads the status register to determine the error in the core).
As to claim 20, it is rejected on grounds corresponding to rejected claim 1 because they are substantially equivalent.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lewis in view of Kondou (US 20140068792 A1).
As to claim 6, the reference(s) teach(es) claim 5 as detailed above. It/they do not explicitly teach updating, based on the second core and the target task, the core allocation information to indicate that the target task is executed by the second core, and updating the execution status, in the core allocation information, of the second task executed by the second core to non-execution status comprises one of the following: updating, based on the second core and the target task, the core allocation information to indicate that the target task is executed by the second core by running a thread based on a target thread identifier, and updating the execution status, in the core allocation information, of the second task to non-execution status, wherein the target thread identifier is a thread identifier of a thread that is run by the target core when the target core executes the target task; or exchanging, based on the second core and the target task, the target task and the second task in the core allocation information, updating the core allocation information to indicate that the target task is executed by the second core by running the thread based on the target thread identifier, and updating the core allocation information to indicate the second task is creating a thread based on a core identifier of the second core without executing the second task.
However, Lewis does teach the steps of claim 5 and Kondou teaches the use of a domain table that maps threads to cores and has status information for those threads (see Fig. 8 and paragraphs 0094, 0095, and 0137; the examiner is interpreting the combination of Lews and Kondou’s methods as teaching at least the first option recited in claim 6).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Lewis with the methods of Kondou because it enables replacement of resources when there is abnormality such as with a replacement of a core (see paragraphs 0137 and 159-160).
As to claim 7, the reference(s) teach(es) claim 5 as detailed above. It/they further teach creating a plurality of threads based on the updated core allocation information and binding a thread corresponding to the target task in the plurality of threads to the second core (Fig. 6, and corresponding text and paragraphs 0090-095, disclosing copying memory contents/moving threads from the stuck core to another core and continuing execution of the threads on another core), and controlling the core other than the target core in the plurality of cores to run, based on the updated core allocation information, a thread other than a thread corresponding to the second task in the plurality of threads (see Fig. 6, and corresponding text and paragraph 0093, disclosing that when no idle cores are available, selecting a core with lower priorities as a replacement core for the higher priority threads of the failed core.)
It/they do(es) not explicitly core identifiers of the plurality of cores, wherein a thread identifier of a thread run by the second core is a target thread identifier.
However, Kondou teaches the use of a domain table that maps threads to cores and has status information for those threads (see Fig. 8 and paragraphs 0094, 0095, and 0137)
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Lewis with the methods of Kondou because it enables replacement of resources when there is abnormality such as with a replacement of a core (see paragraphs 0137 and 159-160).
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lewis in view of Crawford (US 20080163014 A1).
As to claim 9, the reference(s) teach(es) claim 1 as detailed above. It/they do not explicitly teach(es) performing fault detection on the plurality of cores of the processor to determine the target core that is faulty comprises: collecting statistics on cache errors reported by the plurality of cores, to obtain first fault detection results of the plurality of cores, wherein the first fault detection results indicates a quantity of cache errors reported by the target core; and determining, when the first fault detection results of the target core indicates that the quantity of cache errors reported by the target core reaches a target threshold, that the target core is faulty.
However, Crawford teaches taking offline processors affected by a cache that has degraded when detecting that the number of cache errors is beyond a threshold (see Fig. 1 and paragraphs 0025 and 0032).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Lewis with the teachings of Crawford because it enables graceful recovery and prevents more catastrophic errors (see paragraph 0025).
As to claim 18, the reference(s) teach(es) claim 12 as detailed above. It/they do not explicitly teach(es) the at least one processor is configured to perform collecting statistics on cache errors reported by the plurality of cores, to obtain first fault detection results of the plurality of cores, wherein the first fault detection results indicates a quantity of cache errors reported by the target core; and determining, when the first fault detection results of the target core indicates that the quantity of cache errors reported by the target core reaches a target threshold, that the target core is faulty. However, Crawford teaches taking offline processors affected by a cache that has degraded when detecting that the number of cache errors is beyond a threshold (see Fig. 1 and paragraphs 0025 and 0032).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Lewis with the teachings of Crawford because it enables graceful recovery and prevents more catastrophic errors (see paragraph 0025).
Conclusion
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/JASON B BRYAN/ Primary Examiner, Art Unit 2114