DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to because in figure 3, 113 is disclosed but location is not shown on any figure or in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SHIMIZU (US 20160233167 hereinafter Shimizu).
In regards to claim 1, Shimizu discloses;” A printed circuit board (abstract) comprising: an interconnection portion including one or more insulating layers, one or more interconnection layers, and one or more via layers (Fig. 1 (200, 202)) and having a cavity penetrating (Fig. 1 (206, paragraph 0030) through at least a portion of the one or more insulating layers; an electronic component (Fig. 1 (10)) disposed in the cavity; a first insulating material disposed in at least a portion of the cavity and burying at least a portion of the electronic component (Fig. 1 (10)); a second insulating material disposed on the first insulating material (Fig. 1 (400)); and a micro-via (Fig. 9C (210)) penetrating through at least a portion of the second insulating material and connected to the electronic component (Fig. 9C (shown)), wherein the micro-via has a width smaller than at least one of the one or more via layers (Fig. 1 (210) is smaller than via ( 209)).”
In regards to claim 2, Shimizu discloses;” The printed circuit board of claim 1, wherein the one or more insulating layers include a first insulating layer (Fig. 1 (204)) and a second insulating layer disposed on the first insulating layer (Fig. 1 (400)), and the one or more via layers include a first via penetrating through the first insulating layer and a second via penetrating through at least a portion of the second insulating layer (Fig. 1 (208, 209, paragraph 0036)).”
In regards to claim 3, Shimizu discloses;” The printed circuit board of claim 2, wherein the
cavity penetrates throughs at least a portion of the second insulating layer (Fig. 1 (shown)).”
In regards to claim 6, Shimizu discloses;” The printed circuit board of claim 1, wherein the
micro-via (Fig. 9C (210)) is spaced apart from one or more insulating layers (Fig. 9C (204)).”
In regards to claim 7, Shimizu discloses;” The printed circuit board of claim 1, wherein the
micro-via (Fig. 9C (210)) is spaced apart from the first insulating material (Fig. 9C (204)).”
In regards to claim 9, Shimizu discloses;” The printed circuit board of claim 1, wherein the
second insulating material includes a reinforcing material (Fig. 1 (400), paragraph 0040)).”
In regards to claim 10, Shimizu discloses;” The printed circuit board of claim 1, wherein the
first insulating material does not include a fiber reinforcing material (Fig. 1 (204), paragraph’s 0033, 0028)).”
In regards to claim 11, Shimizu discloses;” The printed circuit board of claim 1, wherein the
second insulating material includes a material different from the first insulating material (Fig. 1 (204,400), paragraphs 0028, 0040)).”
In regards to claim 12, Shimizu discloses;” The printed circuit board of claim 11, wherein the second insulating material is more rigid than the first insulating material (glass cloth is more ridged than Silicon oxide (400 MPa vs. <6 MPa)).”
In regards to claim 14, Shimizu discloses;” A printed circuit board (abstract) comprising: an interconnection portion including one or more insulating layers and one or more interconnection layers and having a cavity penetrating through at least a portion of the one or more insulating layers (Fig. 1 (200, 202)); a first insulating material disposed in at least a portion of the cavity (Fig. 1 (204)); and a second insulating material (Fig. 1 (400)) disposed on the first insulating material and including a reinforcing material (paragraph 0040), wherein an uppermost interconnection layer among the one or more interconnection layers includes a first pad, and an upper surface of the first pad is located within the second insulating material (Fig. 1 (shown)).”
In regards to claim 15, Shimizu discloses;” The printed circuit board of claim 14, wherein a
boundary surface of the first insulating material and the second insulating material is located between the upper surface and a lower surface of the first pad (Fig. 1 (210 is between 204 and 400)).”
In regards to claim 16, Shimizu discloses;” The printed circuit board of claim 14, further comprising: an electronic component (Fig. 1 (10)) disposed within the cavity and having a connection pad disposed on an upper surface thereof, wherein an upper surface of the connection pad is located within the second insulating material (Fig. 1 (shown)).”
Allowable Subject Matter
Claims 4 ,5, 8, 13, 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL F MCALLISTER whose telephone number is (571)272-2453. The examiner can normally be reached Monday-Friday 7 AM-4 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL F MCALLISTER/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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