DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramaswami et al (US Pat. Pub. 2013/0093488; hereinafter referred to as Ramaswami) in view of Williams et al (US Pat. 6,137,333; hereinafter referred to as Williams) in view of Raja et al (US Pat. 11,923,853; hereinafter referred to as Raja).
As per claim 1: Ramaswami teaches a test device for a memory device, the test device comprising:
oscillator configured to output an oscillation signal (Fig. 17, 1710); and
an output circuit configured to determine a period of the oscillation signal (Fig. 17, 420), wherein the output circuit is configured to:
count a number of rising edges of the oscillation signal (Fig. 5, 406) while a first operation signal is maintained at a high level (Fig. 5, 408); and
determine an access time of the memory device based on the counted number of the rising edges, and a period of the oscillation signal (paragraphs 41 and 53; any number of parameters including setup time can be determined and verified as shown in Fig. 3).
Not explicitly disclosed is a first exclusive OR (XOR) gate configured to output a first operation signal by performing an XOR operation between a clock signal and an output signal output from the memory device. However, Williams in an analogous art teaches an XOR gate configured to output a first operation signal by performing an XOR operation between a clock signal and an output signal output from a memory device (col. 3, lines 45-48).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to determine a memory access time by counting edges of an oscillation frequency. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Raja suggests using an oscillation frequency to measure memory access time (col. 5, lines 11-15).
As per claim 11: Ramaswami teaches a test method for a memory device, the test method comprising:
determining a period of an oscillation signal (Fig. 5, 502), output from an oscillator (Fig. 17, 1710);
counting a number of rising edges of the oscillation signal that occur (Fig. 5, 406) while a first operation signal is maintained at a high level (Fig. 5, 408); and
determining an access time of the memory device based on the counted number of the rising edges, and the period of the oscillation signal (paragraphs 41 and 53; any number of parameters including setup time can be determined and verified as shown in Fig. 3).
Not explicitly disclosed is a first operation signal is a result of an exclusive OR (XOR) operation between a clock signal and an output signal output from the memory device. However, Williams in an analogous art teaches an XOR gate configured to output a first operation signal by performing an XOR operation between a clock signal and an output signal output from a memory device (col. 3, lines 45-48).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to determine a memory access time by counting edges of an oscillation frequency. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it is suggested by Raja (col. 5, lines 11-15).
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ramaswami in view of Williams in view of Raja in view of Seshadri et al (US Pat. 6,965,520; hereinafter referred to as Seshadri).
As per claim 2:
Ramaswami et al teach the test device of claim 1 above. Not explicitly disclosed is further comprising: a first chain circuit and a second chain circuit, each being configured to receive the clock signal and each comprising a plurality of inverters; and a control logic circuit connected to the first chain circuit and the second chain circuit, wherein the control logic circuit is configured to control the first chain circuit and the second chain circuit such that the first chain circuit and the second chain circuit output delayed clocks to which delay times equal to different integer multiples of a unit delay time are respectively applied, and wherein the unit delay time corresponds to a time delayed by one of the plurality of inverters. However, Seshadri in an analogous art teaches:
a first chain circuit and a second chain circuit, each being configured to receive the clock signal and each comprising a plurality of inverters (Fig. 4, 46); and
a control logic circuit connected to the first chain circuit and the second chain circuit (Fig. 3B, 44),
wherein the control logic circuit is configured to control the first chain circuit and the second chain circuit such that the first chain circuit and the second chain circuit output delayed clocks to which delay times equal to different integer multiples of a unit delay time are respectively applied (Fig. 4; unit delay times are equal to integer multiples of the number of delay elements in each chain as shown), and
wherein the unit delay time corresponds to a time delayed by one of the plurality of inverters (Fig. 4, 46).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the delay chain of Seshadri in the system of Ramaswami et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Ramaswami suggests using tunable delay lines (paragraph 41).
Allowable Subject Matter
Claims 16-20 are allowed.
Claims 3-10, 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: As per claim 16, the main reason for allowance is the inclusion of a second XOR gate and corresponding features. In particular, none of the prior art of record teach or fairly suggest: a second XOR gate configured to perform an XOR operation between a signal output from the first chain circuit and a signal output from the second chain circuit; and an output circuit configured to determine a period of the oscillation signal, wherein the output circuit is configured to: determine an access time of the memory device based on a number of rising edges of the oscillation signal that occur while a first operation signal output from the first XOR gate is maintained at a high level, and the period of the oscillation signal; and determine a unit delay time based on a number of rising edges of the oscillation signal that occur while a second operation signal output from the second XOR gate is maintained at a high level; particularly in combination with each and every other limitation of claim 16.
Similarly, none of the prior art of record teach or fairly suggest each of the limitations as recited in claims 3, 10, and 12, particularly in combination with all the limitations of the intervening and parent claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111
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