DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding the argument that the magnitude of Manne's guardband does not appear to be impacted by any changes between active power states for any cores.
Responsee: Manne teaching an improvement in power controller by adjusting the margins (i.e. guardbands) according to the number of idle cores [par. 7] wherein the power controller provides a power supply voltage to the active one of the data processor cores by adding a variable voltage guardband determined by the number of idle signals received from the data processor cores [par. 13 and 28].
Manne teaches for each processor module 210 in Fig 2 (Fig. 3 is a block diagram of CPU core module 210 of Fig. 2, each processor module is shown to have multiple cores as stated in par. 7]. CPU core module [par.39 -41] the guardband determination circuit 440 provides the VOLTAGE GUARDBAND OFFSET to adder 450 in response to a number of idle CPU core modules 210 indicated by signals C IDLE. The VOLTAGE GUARDBAND OFFSET value is based on the number of idle cores of the each CPU core module 210. The power controller 220 provides a common power supply voltage or respective power supply voltages to active CPU core modules 210 with a voltage guardband related to a number of active cores.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of the following parents applications as shown below. Although the claims at issue are not identical, they are not patentably distinct from each other.
For US 10955893 and US 12235703. Claims 1 includes all the limitations of claims 1, 11 and 20 and therefore are rejected as anticipated by claim 1 of US 10955893. Similarly claim 8 of US 12235703 discloses all the limitations in claims 1, 11 and 20.
For US 9606605 and US 10101788. Claims 1 of the cited patents disclose providing appropriate voltage to the components based on mode of operation with a reduce voltage margin based on the difference between first and second voltage droops (loss). Claim 8 disclose similar feature but for adjusting the frequency instead of voltage.
For US 11422606. Claim 1 discloses the components as being pipelines and the execution status (mode of operation) of the pipeline causes the change in supply voltage taking into account the voltage margin to compensates for the changes in power loss based the mode of operation of the pipelines.
For US 11740676 and US 12235703 Claims 9 of US 11740676 and claim 8 of US 12235703 disclose providing appropriate voltage and frequency to the components based on mode of operation with a reduce voltage margin based differences based on the difference in voltage margin included in the power supplied based on the operating modes of the components
Dependent claims 2-10 and 11-19 disclose various generic features that are found in the dependent of the parents and therefore rejected accordingly.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9, 11-18 and 20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Manne 20140181537.
Regarding Claim 1. Manne teaches system [Fig. 1-8], comprising:
multiple components [Fig. 2, core modules 210], wherein respective components are configured to operate in different modes with different power supply loads; [Fig. 2, par. 13, 18 25-27, 31, Multi-core data processor 200 g includes multiple data processor cores in the form of a set of CPU core modules operating in different P-states based on available headroom and workload of an application], and
control circuitry [Fig. 4, power controller 220, par. 8, 27 and 38] configured to:
determine a first voltage margin to be included in a power supply voltage magnitude requested for the components based on current operating modes of the multiple components [Fig. 4-7; par. 4, 13-17, P-state (operating mode); P-table is determined based on the voltage that will ensure proper operation at a given frequency, but also provide sufficient margin/guardband. Fig. 7. Par. 55, S 710 S720]
detect that a first component of the multiple components has changed its operating mode from a first active operating mode that supports a first set of one or more operations and a second set of one or more operations to a second active operating mode that supports the first set of one or more operations but not the second set of one or more operations [Fig 1-5, Par. 3, 7, 23, 26, 28, 31-33 and 36. P-state is a voltage and frequency combination. An operating system (OS) determines the frequency required to complete the current tasks, such as real-time execution of an application program, and causes an on-chip power state controller to set the clock frequency accordingly. Each CPU core module 210 has the capability to fetch and execute instructions corresponding to one or more threads and executed by cores 310 and 320 (i.e. different operations). In an active mode, the module operates in different P-states and is detected by the voltage controller 220 based on the number of idle cores of each CPU core modules (some of the thread are not executed in second mode). Depending on how many active threads available, some core are active while other are inactive. The change in active/indactive cores are detected by power controller 220.
in response to the detection, modify at least one parameter of the following parameters to recover a portion of the first voltage margin: a power supply voltage magnitude; and an operating frequency of at least a portion of the system; [par. 4, 27-30, appropriate power supply voltage and guardband/margin at a given frequency to an active CPU core module, and/or improves performance; par. 13, saves power by providing a lower power supply voltage by changing guardband]
wherein a magnitude of the modification is based on an estimated difference between a first amount of dynamic power supply voltage loss before the change in operating mode and a second amount of dynamic power supply voltage loss after the change in operating mode [par. 15, 41, 46, As activity level increases, the nominal power supply voltage decreases based on the voltage drop; data processor can accommodate this additional voltage drop by increasing the power supply voltage (VID). Power controller 400 detects power supply voltage droop based on the active/inactive cores, the voltage droop increases monotonically with the number of active threads; guardband determination circuit provides VOLTAGE GUARDBAND OFFSET, which adder 450 adds to the unmodified VID and provide it to the voltage regulator 630]
Claim 2, Manne teaches the system of claim 1, wherein the control circuitry is further configured to delay a requested change in operating mode for the first component based on one or more current operating conditions [Fig. 4 and 7, calculate guardband at step 720 and voltage/frequency based on guardband prior to applying the changes at step 750]
Claim 3. Manne teaches the system of claim 2, wherein the delay permits a modification in voltage margin to occur. [Fig. 4 and 7, calculate guardband at step 720 and voltage/frequency based on guardband prior to applying the changes at step 750]
Claim 4. Manne teaches the system of claim 1, wherein the first component is a graphics processor [par. 58, GPU]
Claim 5. Manne teaches the system of claim 4, wherein the change in operating mode includes activation of a sub-component of the graphics processor [par. 58, cores of GPU]
Claim 6. Manne teaches the system of claim 1, wherein the modification is based on a table of power supply voltage magnitudes and frequency settings that are permitted for the multiple components [par. Par. 34-39 46-51 power state/lookup table]
Claim 7. Manne teaches the system of claim 1, wherein the modification is based on a combination of assigned weights corresponding to current active components and respective assigned weights corresponding to different operating points [par. 23 and 26-27 and 39 intensity of a task, the scheduler determines how to schedule the threads on the cores; the power supply voltage is set to a level required by the highest P-state CPU core].
Claim 8. Manne teaches the system of claim 1, wherein the system is a computing device that includes the multiple components, the control circuitry, and network interface circuitry [see Fig. 2].
Claim 9. Manne teaches the system of claim 1, wherein the modification includes modification of both the power supply voltage magnitude and the operating frequency of the system [par. 027, Power controller 220 has the capability to throttle each of power supply voltage and CLK signal frequency].
Claim 11 and 20 repeat the limitation of claim 1 and therefore rejected accordingly.
Claims 12-18 repeat the limitations of claims 2-7 and 8-10 respectively and are therefore rejected based on the same ground.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Manne.
Claim 10 and 19. Manne teaches the system of claim 1 and 11 respectively, and wherein the multiple components include: one or more image processing components [par. 58] and other types of processing types but does not specify display and audio controller. However. Manne discloses [par 59] that the system includes various types of processing device [DPS, APU, CPU] in a non-limiting manner. Thus, it would have been obvious to one having ordinary skills in the art before the effective filing date to include display and audio controller since these components are common in circuit design [Manne, par. 58].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM HUYNH whose telephone number is (571)272-4147. The examiner can normally be reached M-Th 6:00am-4:0pm.
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/KIM HUYNH/Primary Patent Examiner, Art Unit 2176
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