DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 2-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7, 9-16, 18 and 19 of U.S. Patent No. 12,182,447. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are substantially similar with minor differences and not distinguishing the overall appearance of one over the other. Note: the claims of instant application are anticipated by the claims of the parent, as outlined in the table below.
Current application–18/970,574
U.S. Patent – 12,182,447
2. A memory sub-system, comprising: a frontend manager coupled with a host system and configured to: receive, from the host system using a first command and signaling scheme, one or more commands for accessing the memory sub-system;
a backend manager coupled with a memory device of the memory sub-system and configured to: receive, from the memory device using a second command and signaling scheme, communications based at least in part on the one or more commands, wherein the second command and signaling scheme is different from the first command and signaling scheme; and
a translation manager coupled with the frontend manager and the backend manager and configured to facilitate communication between the frontend manager and the backend manager.
3. The memory sub-system of claim 2, wherein the backend manager is configured to: perform an access operation associated with the memory device based at least in part on the frontend manager receiving the one or more commands for accessing the memory sub-system, wherein receiving the communications from the memory device is based at least in part on performing the access operation.
1. An apparatus, comprising: a frontend manager coupled with a host system to, the frontend manager configured to: receive, from the host system using a first command and signaling scheme …, one or more commands for accessing the memory sub-system; and process the received one or more commands;
a backend manager coupled with a memory device of the memory sub-system to: perform an access operation associated with the memory device based at least in part on the frontend manager processing the received one or more commands; and
receive, from the memory device using a second command and signaling scheme between the memory device, and receive, …, communications based at least in part on performing the access operation; and
a translation manager coupled with the frontend manager and the backend manager and configured to facilitate communication between the frontend manager and the backend manager.
4. The memory sub-system of claim 2, wherein the translation manager is implemented by one or more cores, and wherein, to facilitate communication between the frontend manager and the backend manager, the one or more cores are configured to: convert the received one or more commands from the first command and signaling scheme of the frontend manager to the second command and signaling scheme of the backend manager and converting the communications from the second command and signaling scheme of the backend manager to the first command and signaling scheme of the frontend manager.
2. The apparatus of claim 1, wherein the translation manager is implemented by one or more cores, the one or more cores to facilitate communication between the frontend manager and the backend manager by converting the received one or more commands from the first command and signaling scheme of the frontend manager to the second command and signaling scheme of the backend manager and converting the communications from the second command and signaling scheme of the backend manager to the first command and signaling scheme of the frontend manager.
5. The memory sub-system of claim 2, wherein the frontend manager is implemented by a first core, and wherein the first core is configured to process the received one or more commands.
3. The apparatus of claim 1, wherein the frontend manager implemented by a first core, the first core for processing the one or more commands.
6. The memory sub-system of claim 5, wherein the translation manager is implemented by a third core, and wherein the third core is configured to identify the first core based at least in part on querying a plurality of cores of the frontend manager.
4. The apparatus of claim 3, wherein the translation manager is implemented by a third core, the third core for identifying the first core based, at least in part, on querying a plurality of cores of the frontend manager.
7. The memory sub-system of claim 2, wherein the backend manager is implemented by a second core, and wherein the second core is configured to process the communications received from the memory device.
5. The apparatus of claim 1, wherein the backend manager is implemented by a second core, the second core for performing the access operation and processing the communications received from the memory device.
8. The memory sub-system of claim 7, wherein the translation manager is implemented by a third core, and wherein the third core is configured to identify the second core based at least in part on querying a plurality of cores of the backend manager.
6. The apparatus of claim 5, wherein the translation manager is implemented by a third core, the third core for identifying the second core based, at least in part, on querying a plurality of cores of the backend manager.
9. The memory sub-system of claim 2, wherein: the one or more commands comprise at least one read command; the frontend manager is implemented by one or more cores that are configured to perform a first portion of a read operation associated with the at least one read command; and the backend manager is implemented by one or more cores that are configured to perform a second portion of the read operation.
7. The apparatus of claim 1, wherein: the one or more commands comprise at least one read command; the frontend manager is implemented by one or more cores for performing a first portion of a read operation associated with the at least one read command; and the backend manager is implemented by one or more cores for performing a second portion of the read operation.
10. The memory sub-system of claim 2, wherein: the one or more commands comprise at least one erase command; the frontend manager is implemented by one or more cores that are configured to perform a first portion of an erase operation associated with the at least one erase command; and the backend manager is implemented by one or more cores that are configured to perform a second portion of the erase operation.
9. The apparatus of claim 1, wherein: the one or more commands comprise at least one erase command; the frontend manager is implemented by one or more cores for performing a first portion of an erase operation associated with the at least one erase command; and the backend manager is implemented by one or more cores for performing a second portion of the erase operation.
11. A method, comprising: receiving, at a frontend manager of a memory sub-system and from a host system using a first command and signaling scheme, one or more commands for accessing the memory sub-system;
receiving, at a backend manager of the memory sub-system and form a memory device using a second command and signaling scheme, communications based at least in part on the one or more commands, wherein the second command and signaling scheme is different from the first command and signaling scheme; and
facilitating, using a translation manager, communication between the frontend manager and the backend manager.
12. The method of claim 11, further comprising: performing an access operation associated with the memory device based at least in part on receiving the one or more commands for … based at least in part on performing the access operation.
10. A method, comprising: receiving, from a host system using a first command and signaling scheme between the host system and a frontend manager of a memory sub-system, one or more commands for accessing the memory sub-system; processing, using the frontend manager, the received one or more commands;
performing, using a backend manager, an access operation associated with a memory device of the memory sub-system based at least in part on the received one or more commands;
receiving, at the backend manager using a second command and signaling scheme between the memory device and the backend manager of the memory sub-system and different from the first command and signaling scheme, communications from the memory device based at least in part on performing the access operation; and
facilitating, using a translation manager, communication between the frontend manager and the backend manager.
13. The method of claim 11, wherein facilitating the communication comprises: converting the received one or more commands from the first command and signaling scheme of the frontend manager to the second command and signaling scheme of the backend manager; and converting the communications from the second command and signaling scheme of the backend manager to the first command and signaling scheme of the frontend manager.
11. The method of claim 10, wherein facilitating the communication comprises: converting the received one or more commands from the first command and signaling scheme of the frontend manager to the second command and signaling scheme of the backend manager; and converting the communications from the second command and signaling scheme of the backend manager to the first command and signaling scheme of the frontend manager.
14. The method of claim 11, further comprising: processing the received one or more commands using a first core of the frontend manager.
12. The method of claim 10, wherein: processing the received one or more commands comprises processing, using a first core of the frontend manager,…
15. The method of claim 14, further comprising: identifying, using a third core of the translation manager, the first core of the frontend manager based at least in part on querying a plurality of cores of the frontend manager.
13. The method of claim 12, further comprising: identifying, using a third core of the translation manager, the first core of the frontend manager based at least in part on querying a plurality of cores of the frontend manager.
16. The method of claim 11, further comprising: receiving the communications from the memory device using a second core of the backend manager.
14. The method of claim 10, further comprising: …receiving the communications from the memory device, using a second core of the backend manager.
17. The method of claim 16, further comprising: identifying, using a third core of the translation manager, the second core of the backend manager based at least in part on querying a plurality of cores of the backend manager.
15. The method of claim 14, further comprising: identifying, using a third core of the translation manager, the third core of the backend manager based, at least in part, on querying a plurality of cores of the backend manager.
18. The method of claim 11, wherein the one or more commands comprise at least one read command, and the method further comprises: performing, using one or more cores of the frontend manager, a first portion of a read operation associated with the at least one read command; and performing, using one or more cores of the backend manager, a second portion of the read operation.
16. The method of claim 10, wherein the one or more commands comprise at least one read command, and the method further comprises: performing, using one or more cores of the frontend manager, a first portion of a read operation associated with the at least one read command; and performing, using one or more cores of the backend manager, a second portion of the read operation.
19. The method of claim 11, wherein the one or more commands comprise at least one erase command, and the method further comprises: performing, using one or more cores of the frontend manager, a first portion of an erase operation associated with the at least one erase command; and performing, using one or more cores of the backend manager, a second portion of the erase operation.
18. The method of claim 10, wherein the one or more commands comprise at least one erase command, and the method further comprises: performing, using one or more cores of the frontend manager, a first portion of an erase operation associated with the at least one erase command; and performing, using one or more cores of the backend manager, a second portion of the erase operation.
20. A memory sub-system, comprising: a frontend manager, the frontend manager coupled with a host system to
receive, from the host system using a first command and signaling scheme, a write command to store data in the memory sub-system;
a backend manager coupled with a memory device of the memory sub-system to communicate, to the memory device using a second command and signaling scheme, the data based at least in part on the write command, wherein the second command and signaling scheme is different from the first command and signaling scheme; and
a translation manager coupled with the frontend manager and the backend manager and configured to facilitate communication between the frontend manager and the backend manager.
19. An apparatus, comprising: a frontend manager coupled with a host system to: receive, from the host system using a first command and signaling scheme between the host system and the frontend manager of a memory sub-system, a write command to store data in the memory sub-system; and process the received write command;
a backend manager coupled with a memory device of the memory sub-system to: perform an access operation associated with the memory device based at least in part on the frontend manager processing the received write command; and communicate, to the memory device using a second command and signaling scheme between the memory device and the backend manager of the memory sub-system and different from the first command and signaling scheme, …; and
a translation manager coupled with the frontend manager and the backend manager and configured to facilitate communication between the frontend manager and the backend manager.
Allowable Subject Matter
Claims 2-21 are objected to because of the presence of the obviousness type double patenting rejection (see above) but would be allowable if the rejection is overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Venkatesh et al. (US 2018/0165381), Guyer (US 2021/0133122), OH et al. (US 2019/0166262), Koo et al. (US 2019/0163625), Yun et al. (US 2017/0031632), Crews et al. (US 10,108,559) and Berman et al. (US 10,423,568) do teach a multiprocessor system and method configured to dynamically select a processor core for processing I/O operations.
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Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS MAMO whose telephone number is (571)270-1726. The examiner can normally be reached Mon-Thu, 7 AM - 5 PM.
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/Elias Mamo/Primary Examiner, Art Unit 2184